1 /*
2 * Copyright (c) 2009-2024 Arm Limited.
3 * Copyright (c) 2018-2022 Arm China.
4 * All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19
20 /*
21 * CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File
22 */
23
24 #if defined ( __ICCARM__ )
25 #pragma system_include /* treat file as system include file for MISRA check */
26 #elif defined (__clang__)
27 #pragma clang system_header /* treat file as system include file */
28 #elif defined ( __GNUC__ )
29 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
30 #endif
31
32 #ifndef __CORE_STAR_H_GENERIC
33 #define __CORE_STAR_H_GENERIC
34
35 #include <stdint.h>
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif
40
41 /**
42 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
43 CMSIS violates the following MISRA-C:2004 rules:
44
45 \li Required Rule 8.5, object/function definition in header file.<br>
46 Function definitions in header files are used to allow 'inlining'.
47
48 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
49 Unions are used for effective representation of core registers.
50
51 \li Advisory Rule 19.7, Function-like macro defined.<br>
52 Function-like macros are used to allow more efficient code.
53 */
54
55
56 /*******************************************************************************
57 * CMSIS definitions
58 ******************************************************************************/
59 /**
60 \ingroup STAR-MC1
61 @{
62 */
63
64 #include "cmsis_version.h"
65
66 /* Macro Define for STAR-MC1 */
67
68 #define __STAR_MC (1U) /*!< STAR-MC Core */
69
70 /** __FPU_USED indicates whether an FPU is used or not.
71 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
72 */
73 #if defined ( __CC_ARM )
74 #if defined (__TARGET_FPU_VFP)
75 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
76 #define __FPU_USED 1U
77 #else
78 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #define __FPU_USED 0U
80 #endif
81 #else
82 #define __FPU_USED 0U
83 #endif
84
85 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
86 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
87 #define __DSP_USED 1U
88 #else
89 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
90 #define __DSP_USED 0U
91 #endif
92 #else
93 #define __DSP_USED 0U
94 #endif
95
96 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
97 #if defined (__ARM_FP)
98 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
99 #define __FPU_USED 1U
100 #else
101 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
102 #define __FPU_USED 0U
103 #endif
104 #else
105 #define __FPU_USED 0U
106 #endif
107
108 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
109 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
110 #define __DSP_USED 1U
111 #else
112 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
113 #define __DSP_USED 0U
114 #endif
115 #else
116 #define __DSP_USED 0U
117 #endif
118
119 #elif defined (__ti__)
120 #if defined (__ARM_FP)
121 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
122 #define __FPU_USED 1U
123 #else
124 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
125 #define __FPU_USED 0U
126 #endif
127 #else
128 #define __FPU_USED 0U
129 #endif
130
131 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
132 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
133 #define __DSP_USED 1U
134 #else
135 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
136 #define __DSP_USED 0U
137 #endif
138 #else
139 #define __DSP_USED 0U
140 #endif
141
142 #elif defined ( __GNUC__ )
143 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
144 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
145 #define __FPU_USED 1U
146 #else
147 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
148 #define __FPU_USED 0U
149 #endif
150 #else
151 #define __FPU_USED 0U
152 #endif
153
154 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
155 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
156 #define __DSP_USED 1U
157 #else
158 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
159 #define __DSP_USED 0U
160 #endif
161 #else
162 #define __DSP_USED 0U
163 #endif
164
165 #elif defined ( __ICCARM__ )
166 #if defined (__ARMVFP__)
167 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
168 #define __FPU_USED 1U
169 #else
170 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
171 #define __FPU_USED 0U
172 #endif
173 #else
174 #define __FPU_USED 0U
175 #endif
176
177 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
178 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
179 #define __DSP_USED 1U
180 #else
181 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
182 #define __DSP_USED 0U
183 #endif
184 #else
185 #define __DSP_USED 0U
186 #endif
187
188 #elif defined ( __TI_ARM__ )
189 #if defined (__TI_VFP_SUPPORT__)
190 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
191 #define __FPU_USED 1U
192 #else
193 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
194 #define __FPU_USED 0U
195 #endif
196 #else
197 #define __FPU_USED 0U
198 #endif
199
200 #elif defined ( __TASKING__ )
201 #if defined (__FPU_VFP__)
202 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
203 #define __FPU_USED 1U
204 #else
205 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
206 #define __FPU_USED 0U
207 #endif
208 #else
209 #define __FPU_USED 0U
210 #endif
211
212 #elif defined ( __CSMC__ )
213 #if ( __CSMC__ & 0x400U)
214 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
215 #define __FPU_USED 1U
216 #else
217 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
218 #define __FPU_USED 0U
219 #endif
220 #else
221 #define __FPU_USED 0U
222 #endif
223
224 #endif
225
226 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
227
228
229 #ifdef __cplusplus
230 }
231 #endif
232
233 #endif /* __CORE_STAR_H_GENERIC */
234
235 #ifndef __CMSIS_GENERIC
236
237 #ifndef __CORE_STAR_H_DEPENDANT
238 #define __CORE_STAR_H_DEPENDANT
239
240 #ifdef __cplusplus
241 extern "C" {
242 #endif
243
244 /* check device defines and use defaults */
245 #if defined __CHECK_DEVICE_DEFINES
246 #ifndef __STAR_REV
247 #define __STAR_REV 0x0000U
248 #warning "__STAR_REV not defined in device header file; using default!"
249 #endif
250
251 #ifndef __FPU_PRESENT
252 #define __FPU_PRESENT 0U
253 #warning "__FPU_PRESENT not defined in device header file; using default!"
254 #endif
255
256 #ifndef __MPU_PRESENT
257 #define __MPU_PRESENT 0U
258 #warning "__MPU_PRESENT not defined in device header file; using default!"
259 #endif
260
261 #ifndef __SAUREGION_PRESENT
262 #define __SAUREGION_PRESENT 0U
263 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
264 #endif
265
266 #ifndef __DSP_PRESENT
267 #define __DSP_PRESENT 0U
268 #warning "__DSP_PRESENT not defined in device header file; using default!"
269 #endif
270
271 #ifndef __ICACHE_PRESENT
272 #define __ICACHE_PRESENT 0U
273 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
274 #endif
275
276 #ifndef __DCACHE_PRESENT
277 #define __DCACHE_PRESENT 0U
278 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
279 #endif
280
281 #ifndef __DTCM_PRESENT
282 #define __DTCM_PRESENT 0U
283 #warning "__DTCM_PRESENT not defined in device header file; using default!"
284 #endif
285
286 #ifndef __NVIC_PRIO_BITS
287 #define __NVIC_PRIO_BITS 3U
288 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
289 #endif
290
291 #ifndef __Vendor_SysTickConfig
292 #define __Vendor_SysTickConfig 0U
293 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
294 #endif
295 #endif
296
297 /* IO definitions (access restrictions to peripheral registers) */
298 /**
299 \defgroup CMSIS_glob_defs CMSIS Global Defines
300
301 <strong>IO Type Qualifiers</strong> are used
302 \li to specify the access to peripheral variables.
303 \li for automatic generation of peripheral register debug information.
304 */
305 #ifdef __cplusplus
306 #define __I volatile /*!< Defines 'read only' permissions */
307 #else
308 #define __I volatile const /*!< Defines 'read only' permissions */
309 #endif
310 #define __O volatile /*!< Defines 'write only' permissions */
311 #define __IO volatile /*!< Defines 'read / write' permissions */
312
313 /* following defines should be used for structure members */
314 #define __IM volatile const /*! Defines 'read only' structure member permissions */
315 #define __OM volatile /*! Defines 'write only' structure member permissions */
316 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
317
318 /*@} end of group STAR-MC1 */
319
320
321
322 /*******************************************************************************
323 * Register Abstraction
324 Core Register contain:
325 - Core Register
326 - Core NVIC Register
327 - Core SCB Register
328 - Core SysTick Register
329 - Core Debug Register
330 - Core MPU Register
331 - Core SAU Register
332 - Core FPU Register
333 ******************************************************************************/
334 /**
335 \defgroup CMSIS_core_register Defines and Type Definitions
336 \brief Type definitions and defines for STAR-MC1 processor based devices.
337 */
338
339 /**
340 \ingroup CMSIS_core_register
341 \defgroup CMSIS_CORE Status and Control Registers
342 \brief Core Register type definitions.
343 @{
344 */
345
346 /**
347 \brief Union type to access the Application Program Status Register (APSR).
348 */
349 typedef union
350 {
351 struct
352 {
353 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
354 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
355 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
356 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
357 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
358 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
359 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
360 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
361 } b; /*!< Structure used for bit access */
362 uint32_t w; /*!< Type used for word access */
363 } APSR_Type;
364
365 /** \brief APSR Register Definitions */
366 #define APSR_N_Pos 31U /*!< APSR: N Position */
367 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
368
369 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
370 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
371
372 #define APSR_C_Pos 29U /*!< APSR: C Position */
373 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
374
375 #define APSR_V_Pos 28U /*!< APSR: V Position */
376 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
377
378 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
379 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
380
381 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
382 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
383
384
385 /**
386 \brief Union type to access the Interrupt Program Status Register (IPSR).
387 */
388 typedef union
389 {
390 struct
391 {
392 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
393 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
394 } b; /*!< Structure used for bit access */
395 uint32_t w; /*!< Type used for word access */
396 } IPSR_Type;
397
398 /** \brief IPSR Register Definitions */
399 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
400 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
401
402
403 /**
404 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
405 */
406 typedef union
407 {
408 struct
409 {
410 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
411 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
412 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
413 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
414 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
415 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
416 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
417 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
418 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
419 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
420 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
421 } b; /*!< Structure used for bit access */
422 uint32_t w; /*!< Type used for word access */
423 } xPSR_Type;
424
425 /** \brief xPSR Register Definitions */
426 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
427 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
428
429 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
430 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
431
432 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
433 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
434
435 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
436 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
437
438 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
439 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
440
441 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
442 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
443
444 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
445 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
446
447 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
448 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
449
450 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
451 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
452
453
454 /**
455 \brief Union type to access the Control Registers (CONTROL).
456 */
457 typedef union
458 {
459 struct
460 {
461 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
462 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
463 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
464 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
465 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
466 } b; /*!< Structure used for bit access */
467 uint32_t w; /*!< Type used for word access */
468 } CONTROL_Type;
469
470 /** \brief CONTROL Register Definitions */
471 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
472 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
473
474 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
475 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
476
477 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
478 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
479
480 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
481 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
482
483 /*@} end of group CMSIS_CORE */
484
485
486 /**
487 \ingroup CMSIS_core_register
488 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
489 \brief Type definitions for the NVIC Registers
490 @{
491 */
492
493 /**
494 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
495 */
496 typedef struct
497 {
498 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
499 uint32_t RESERVED0[16U];
500 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
501 uint32_t RESERVED1[16U];
502 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
503 uint32_t RESERVED2[16U];
504 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
505 uint32_t RESERVED3[16U];
506 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
507 uint32_t RESERVED4[16U];
508 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
509 uint32_t RESERVED5[16U];
510 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
511 uint32_t RESERVED6[580U];
512 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
513 } NVIC_Type;
514
515 /** \brief NVIC Software Triggered Interrupt Register Definitions */
516 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
517 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
518
519 /*@} end of group CMSIS_NVIC */
520
521
522 /**
523 \ingroup CMSIS_core_register
524 \defgroup CMSIS_SCB System Control Block (SCB)
525 \brief Type definitions for the System Control Block Registers
526 @{
527 */
528
529 /**
530 \brief Structure type to access the System Control Block (SCB).
531 */
532 typedef struct
533 {
534 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
535 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
536 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
537 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
538 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
539 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
540 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
541 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
542 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
543 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
544 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
545 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
546 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
547 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
548 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
549 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
550 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
551 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
552 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
553 uint32_t RESERVED0[1U];
554 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
555 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
556 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
557 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
558 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
559 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
560 uint32_t RESERVED_ADD1[21U];
561 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
562 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
563 uint32_t RESERVED3[69U];
564 __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */
565 uint32_t RESERVED4[15U];
566 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
567 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
568 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
569 uint32_t RESERVED5[1U];
570 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
571 uint32_t RESERVED6[1U];
572 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
573 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
574 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
575 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
576 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
577 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
578 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
579 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
580 } SCB_Type;
581
582 typedef struct
583 {
584 __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */
585 uint32_t RESERVED0[3U];
586 __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */
587 __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */
588 } EMSS_Type;
589
590 /** \brief SCB CPUID Register Definitions */
591 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
592 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
593
594 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
595 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
596
597 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
598 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
599
600 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
601 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
602
603 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
604 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
605
606 /** \brief SCB Interrupt Control State Register Definitions */
607 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
608 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
609
610 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
611 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
612
613 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
614 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
615
616 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
617 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
618
619 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
620 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
621
622 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
623 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
624
625 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
626 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
627
628 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
629 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
630
631 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
632 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
633
634 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
635 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
636
637 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
638 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
639
640 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
641 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
642
643 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
644 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
645
646 /** \brief SCB Vector Table Offset Register Definitions */
647 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
648 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
649
650 /** \brief SCB Application Interrupt and Reset Control Register Definitions */
651 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
652 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
653
654 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
655 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
656
657 #define SCB_AIRCR_ENDIANNESS_Pos 15U /*!< SCB AIRCR: ENDIANNESS Position */
658 #define SCB_AIRCR_ENDIANNESS_Msk (1UL << SCB_AIRCR_ENDIANNESS_Pos) /*!< SCB AIRCR: ENDIANNESS Mask */
659
660 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
661 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
662
663 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
664 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
665
666 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
667 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
668
669 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
670 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
671
672 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
673 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
674
675 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
676 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
677
678 /** \brief SCB System Control Register Definitions */
679 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
680 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
681
682 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
683 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
684
685 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
686 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
687
688 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
689 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
690
691 /** \brief SCB Configuration Control Register Definitions */
692 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
693 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
694
695 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
696 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
697
698 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
699 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
700
701 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
702 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
703
704 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
705 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
706
707 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
708 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
709
710 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
711 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
712
713 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
714 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
715
716 /** \brief SCB System Handler Control and State Register Definitions */
717 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
718 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
719
720 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
721 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
722
723 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
724 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
725
726 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
727 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
728
729 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
730 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
731
732 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
733 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
734
735 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
736 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
737
738 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
739 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
740
741 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
742 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
743
744 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
745 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
746
747 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
748 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
749
750 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
751 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
752
753 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
754 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
755
756 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
757 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
758
759 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
760 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
761
762 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
763 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
764
765 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
766 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
767
768 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
769 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
770
771 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
772 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
773
774 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
775 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
776
777 /** \brief SCB Configurable Fault Status Register Definitions */
778 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
779 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
780
781 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
782 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
783
784 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
785 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
786
787 /** \brief SCB MemManage Fault Status Register Definitions (part of SCB Configurable Fault Status Register) */
788 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
789 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
790
791 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
792 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
793
794 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
795 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
796
797 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
798 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
799
800 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
801 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
802
803 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
804 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
805
806 /** \brief SCB BusFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
807 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
808 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
809
810 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
811 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
812
813 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
814 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
815
816 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
817 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
818
819 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
820 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
821
822 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
823 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
824
825 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
826 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
827
828 /** \brief SCB UsageFault Status Register Definitions (part of SCB Configurable Fault Status Register) */
829 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
830 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
831
832 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
833 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
834
835 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
836 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
837
838 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
839 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
840
841 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
842 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
843
844 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
845 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
846
847 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
848 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
849
850 /** \brief SCB Hard Fault Status Register Definitions */
851 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
852 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
853
854 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
855 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
856
857 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
858 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
859
860 /** \brief SCB Debug Fault Status Register Definitions */
861 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
862 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
863
864 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
865 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
866
867 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
868 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
869
870 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
871 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
872
873 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
874 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
875
876 /** \brief SCB Non-Secure Access Control Register Definitions */
877 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
878 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
879
880 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
881 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
882
883 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
884 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
885
886 /** \brief SCB Cache Level ID Register Definitions */
887 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
888 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
889
890 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
891 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
892
893 #define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */
894 #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */
895
896 #define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */
897 #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */
898
899 /** \brief SCB Cache Type Register Definitions */
900 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
901 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
902
903 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
904 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
905
906 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
907 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
908
909 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
910 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
911
912 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
913 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
914
915 /** \brief SCB Cache Size ID Register Definitions */
916 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
917 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
918
919 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
920 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
921
922 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
923 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
924
925 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
926 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
927
928 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
929 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
930
931 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
932 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
933
934 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
935 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
936
937 /** \brief SCB Cache Size Selection Register Definitions */
938 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
939 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
940
941 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
942 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
943
944 /** \brief SCB Software Triggered Interrupt Register Definitions */
945 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
946 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
947
948 /** \brief SCB D-Cache line Invalidate by Set-way Register Definitions */
949 #define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */
950 #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */
951
952 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
953 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
954
955 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
956 #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
957
958 /** \brief SCB D-Cache Clean line by Set-way Register Definitions */
959 #define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */
960 #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */
961
962 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
963 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
964
965 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
966 #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
967
968 /** \brief SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
969 #define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */
970 #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */
971
972 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
973 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
974
975 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
976 #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
977
978 /* ArmChina: Implementation Defined */
979 /** \brief Instruction Tightly-Coupled Memory Control Register Definitions */
980 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
981 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
982
983 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
984 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
985
986 /** \brief Data Tightly-Coupled Memory Control Register Definitions */
987 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
988 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
989
990 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
991 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
992
993 /** \brief L1 Cache Control Register Definitions */
994 #define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */
995 #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */
996
997 #define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */
998 #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */
999
1000 #define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */
1001 #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */
1002
1003 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
1004 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
1005
1006 /*@} end of group CMSIS_SCB */
1007
1008
1009 /**
1010 \ingroup CMSIS_core_register
1011 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
1012 \brief Type definitions for the System Control and ID Register not in the SCB
1013 @{
1014 */
1015
1016 /**
1017 \brief Structure type to access the System Control and ID Register not in the SCB.
1018 */
1019 typedef struct
1020 {
1021 uint32_t RESERVED0[1U];
1022 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1023 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1024 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1025 } SCnSCB_Type;
1026
1027 /** \brief SCnSCB Interrupt Controller Type Register Definitions */
1028 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1029 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1030
1031 /*@} end of group CMSIS_SCnotSCB */
1032
1033
1034 /**
1035 \ingroup CMSIS_core_register
1036 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1037 \brief Type definitions for the System Timer Registers.
1038 @{
1039 */
1040
1041 /**
1042 \brief Structure type to access the System Timer (SysTick).
1043 */
1044 typedef struct
1045 {
1046 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1047 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1048 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1049 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1050 } SysTick_Type;
1051
1052 /** \brief SysTick Control / Status Register Definitions */
1053 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1054 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1055
1056 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1057 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1058
1059 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1060 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1061
1062 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1063 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1064
1065 /** \brief SysTick Reload Register Definitions */
1066 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1067 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1068
1069 /** \brief SysTick Current Register Definitions */
1070 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1071 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1072
1073 /** \brief SysTick Calibration Register Definitions */
1074 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1075 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1076
1077 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1078 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1079
1080 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1081 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1082
1083 /*@} end of group CMSIS_SysTick */
1084
1085
1086 /**
1087 \ingroup CMSIS_core_register
1088 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1089 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1090 @{
1091 */
1092
1093 /**
1094 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1095 */
1096 typedef struct
1097 {
1098 __OM union
1099 {
1100 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) Stimulus Port 8-bit */
1101 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) Stimulus Port 16-bit */
1102 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) Stimulus Port 32-bit */
1103 } PORT [32U]; /*!< Offset: 0x000 ( /W) Stimulus Port Registers */
1104 uint32_t RESERVED0[864U];
1105 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) Trace Enable Register */
1106 uint32_t RESERVED1[15U];
1107 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) Trace Privilege Register */
1108 uint32_t RESERVED2[15U];
1109 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) Trace Control Register */
1110 uint32_t RESERVED3[32U];
1111 uint32_t RESERVED4[43U];
1112 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Lock Access Register */
1113 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Lock Status Register */
1114 uint32_t RESERVED5[1U];
1115 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1116 } ITM_Type;
1117
1118 /** \brief ITM Stimulus Port Register Definitions */
1119 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1120 #define ITM_STIM_DISABLED_Msk (1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1121
1122 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1123 #define ITM_STIM_FIFOREADY_Msk (1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1124
1125 /** \brief ITM Trace Privilege Register Definitions */
1126 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1127 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1128
1129 /** \brief ITM Trace Control Register Definitions */
1130 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1131 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1132
1133 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1134 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1135
1136 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1137 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1138
1139 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1140 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1141
1142 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1143 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1144
1145 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1146 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1147
1148 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1149 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1150
1151 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1152 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1153
1154 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1155 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1156
1157 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1158 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1159
1160 /** \brief ITM Lock Status Register Definitions */
1161 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1162 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1163
1164 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1165 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1166
1167 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1168 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1169
1170 /*@}*/ /* end of group CMSIS_ITM */
1171
1172
1173 /**
1174 \ingroup CMSIS_core_register
1175 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1176 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1177 @{
1178 */
1179
1180 /**
1181 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1182 */
1183 typedef struct
1184 {
1185 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1186 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1187 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1188 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1189 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1190 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1191 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1192 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1193 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1194 uint32_t RESERVED1[1U];
1195 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1196 uint32_t RESERVED2[1U];
1197 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1198 uint32_t RESERVED3[1U];
1199 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1200 uint32_t RESERVED4[1U];
1201 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1202 uint32_t RESERVED5[1U];
1203 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1204 uint32_t RESERVED6[1U];
1205 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1206 uint32_t RESERVED7[1U];
1207 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1208 uint32_t RESERVED8[1U];
1209 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1210 uint32_t RESERVED9[1U];
1211 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1212 uint32_t RESERVED10[1U];
1213 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1214 uint32_t RESERVED11[1U];
1215 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1216 uint32_t RESERVED12[1U];
1217 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1218 uint32_t RESERVED13[1U];
1219 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1220 uint32_t RESERVED14[1U];
1221 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1222 uint32_t RESERVED15[1U];
1223 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1224 uint32_t RESERVED16[1U];
1225 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1226 uint32_t RESERVED17[1U];
1227 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1228 uint32_t RESERVED18[1U];
1229 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1230 uint32_t RESERVED19[1U];
1231 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1232 uint32_t RESERVED20[1U];
1233 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1234 uint32_t RESERVED21[1U];
1235 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1236 uint32_t RESERVED22[1U];
1237 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1238 uint32_t RESERVED23[1U];
1239 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1240 uint32_t RESERVED24[1U];
1241 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1242 uint32_t RESERVED25[1U];
1243 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1244 uint32_t RESERVED26[1U];
1245 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1246 uint32_t RESERVED27[1U];
1247 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1248 uint32_t RESERVED28[1U];
1249 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1250 uint32_t RESERVED29[1U];
1251 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1252 uint32_t RESERVED30[1U];
1253 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1254 uint32_t RESERVED31[1U];
1255 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1256 uint32_t RESERVED32[934U];
1257 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1258 uint32_t RESERVED33[1U];
1259 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1260 } DWT_Type;
1261
1262 /** \brief DWT Control Register Definitions */
1263 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1264 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1265
1266 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1267 #define DWT_CTRL_NOTRCPKT_Msk (1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1268
1269 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1270 #define DWT_CTRL_NOEXTTRIG_Msk (1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1271
1272 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1273 #define DWT_CTRL_NOCYCCNT_Msk (1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1274
1275 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1276 #define DWT_CTRL_NOPRFCNT_Msk (1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1277
1278 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1279 #define DWT_CTRL_CYCDISS_Msk (1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1280
1281 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1282 #define DWT_CTRL_CYCEVTENA_Msk (1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1283
1284 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1285 #define DWT_CTRL_FOLDEVTENA_Msk (1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1286
1287 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1288 #define DWT_CTRL_LSUEVTENA_Msk (1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1289
1290 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1291 #define DWT_CTRL_SLEEPEVTENA_Msk (1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1292
1293 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1294 #define DWT_CTRL_EXCEVTENA_Msk (1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1295
1296 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1297 #define DWT_CTRL_CPIEVTENA_Msk (1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1298
1299 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1300 #define DWT_CTRL_EXCTRCENA_Msk (1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1301
1302 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1303 #define DWT_CTRL_PCSAMPLENA_Msk (1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1304
1305 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1306 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1307
1308 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1309 #define DWT_CTRL_CYCTAP_Msk (1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1310
1311 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1312 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1313
1314 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1315 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1316
1317 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1318 #define DWT_CTRL_CYCCNTENA_Msk (1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1319
1320 /** \brief DWT CPI Count Register Definitions */
1321 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1322 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1323
1324 /** \brief DWT Exception Overhead Count Register Definitions */
1325 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1326 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1327
1328 /** \brief DWT Sleep Count Register Definitions */
1329 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1330 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1331
1332 /** \brief DWT LSU Count Register Definitions */
1333 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1334 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1335
1336 /** \brief DWT Folded-instruction Count Register Definitions */
1337 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1338 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1339
1340 /** \brief DWT Comparator Function Register Definitions */
1341 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1342 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1343
1344 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1345 #define DWT_FUNCTION_MATCHED_Msk (1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1346
1347 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1348 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1349
1350 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1351 #define DWT_FUNCTION_ACTION_Msk (1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1352
1353 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1354 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1355
1356 /*@}*/ /* end of group CMSIS_DWT */
1357
1358 /**
1359 \ingroup CMSIS_core_register
1360 \defgroup CMSIS_BPU Breakpoint Unit (BPU)
1361 \brief Type definitions for the Breakpoint Unit (BPU)
1362 @{
1363 */
1364
1365 /**
1366 \brief Structure type to access the Breakpoint Unit Register (BPU).
1367 */
1368 typedef struct
1369 {
1370 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1371 uint32_t RESERVED1;
1372 __IOM uint32_t COMP0; /*!< Offset: 0x008 (R/W) Comparator Register 0 */
1373 __IOM uint32_t COMP1; /*!< Offset: 0x00C (R/W) Comparator Register 1 */
1374 __IOM uint32_t COMP2; /*!< Offset: 0x010 (R/W) Comparator Register 2 */
1375 __IOM uint32_t COMP3; /*!< Offset: 0x014 (R/W) Comparator Register 3 */
1376 __IOM uint32_t COMP4; /*!< Offset: 0x018 (R/W) Comparator Register 0 */
1377 __IOM uint32_t COMP5; /*!< Offset: 0x01C (R/W) Comparator Register 0 */
1378 __IOM uint32_t COMP6; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1379 __IOM uint32_t COMP7; /*!< Offset: 0x024 (R/W) Comparator Register 0 */
1380 uint32_t RESERVED2[997];
1381 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Type Register */
1382 uint32_t RESERVED3[3];
1383 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Architecture Register */
1384 } BPU_Type;
1385
1386 /** \brief BPU Control Register Definitions */
1387 #define BPU_CTRL_REV_Pos 28U /*!< BPU CTRL: REV Position */
1388 #define BPU_CTRL_REV_Msk (0xFUL << BPU_CTRL_REV_Pos) /*!< BPU CTRL: REV Mask */
1389
1390 #define BPU_CTRL_NUM_CODE_H_Pos 12U /*!< BPU CTRL: NUM_CODE_H Position */
1391 #define BPU_CTRL_NUM_CODE_H_Msk (0x7UL << BPU_CTRL_NUM_CODE_H_Pos) /*!< BPU CTRL: NUM_CODE_H Mask */
1392
1393 #define BPU_CTRL_NUM_LIT_Pos 8U /*!< BPU CTRL: NUM_LIT Position */
1394 #define BPU_CTRL_NUM_LIT_Msk (0xFUL << BPU_CTRL_NUM_LIT_Pos) /*!< BPU CTRL: NUM_LIT Mask */
1395
1396 #define BPU_CTRL_NUM_CODE_L_Pos 4U /*!< BPU CTRL: NUM_CODE_L Position */
1397 #define BPU_CTRL_NUM_CODE_L_Msk (0xFUL << BPU_CTRL_NUM_CODE_L_Pos) /*!< BPU CTRL: NUM_CODE_L Mask */
1398
1399 #define BPU_CTRL_KEY_Pos 1U /*!< BPU CTRL: KEY Position */
1400 #define BPU_CTRL_KEY_Msk (0x1UL << BPU_CTRL_KEY_Pos) /*!< BPU CTRL: KEY Mask */
1401
1402 #define BPU_CTRL_ENABLE_Pos 0U /*!< BPU CTRL: ENABLE Position */
1403 #define BPU_CTRL_ENABLE_Msk (0x1UL << BPU_CTRL_ENABLE_Pos) /*!< BPU CTRL: ENABLE Mask */
1404
1405 /** \brief BPU Comparator Register Definitions */
1406 #define BPU_COMP_BPADDR_Pos 1U /*!< BPU COMP: BPADDR Position */
1407 #define BPU_COMP_BPADDR_Msk (0x7FFFFFFFUL << BPU_COMP_BPADDR_Pos) /*!< BPU COMP: BPADDR Mask */
1408
1409 #define BPU_COMP_BE_Pos 0U /*!< BPU COMP: BE Position */
1410 #define BPU_COMP_BE_Msk (0x1UL << BPU_COMP_BE_Pos) /*!< BPU COMP: BE Mask */
1411
1412 /*@}*/ /* end of group CMSIS_BPU */
1413
1414
1415 /**
1416 \ingroup CMSIS_core_register
1417 \defgroup CMSIS_TPIU Trace Port Interface Unit (TPIU)
1418 \brief Type definitions for the Trace Port Interface Unit (TPIU)
1419 @{
1420 */
1421
1422 /**
1423 \brief Structure type to access the Trace Port Interface Unit Register (TPIU).
1424 */
1425 typedef struct
1426 {
1427 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1428 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1429 uint32_t RESERVED0[2U];
1430 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1431 uint32_t RESERVED1[55U];
1432 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1433 uint32_t RESERVED2[131U];
1434 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1435 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1436 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1437 uint32_t RESERVED3[759U];
1438 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1439 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1440 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1441 uint32_t RESERVED4[1U];
1442 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1443 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1444 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1445 uint32_t RESERVED5[39U];
1446 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1447 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1448 uint32_t RESERVED7[8U];
1449 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1450 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1451 } TPIU_Type;
1452
1453 /** \brief TPIU Asynchronous Clock Prescaler Register Definitions */
1454 #define TPIU_ACPR_PRESCALER_Pos 0U /*!< TPIU ACPR: PRESCALER Position */
1455 #define TPIU_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPIU_ACPR_PRESCALER_Pos*/) /*!< TPIU ACPR: PRESCALER Mask */
1456
1457 /** \brief TPIU Selected Pin Protocol Register Definitions */
1458 #define TPIU_SPPR_TXMODE_Pos 0U /*!< TPIU SPPR: TXMODE Position */
1459 #define TPIU_SPPR_TXMODE_Msk (0x3UL /*<< TPIU_SPPR_TXMODE_Pos*/) /*!< TPIU SPPR: TXMODE Mask */
1460
1461 /** \brief TPIU Formatter and Flush Status Register Definitions */
1462 #define TPIU_FFSR_FtNonStop_Pos 3U /*!< TPIU FFSR: FtNonStop Position */
1463 #define TPIU_FFSR_FtNonStop_Msk (1UL << TPIU_FFSR_FtNonStop_Pos) /*!< TPIU FFSR: FtNonStop Mask */
1464
1465 #define TPIU_FFSR_TCPresent_Pos 2U /*!< TPIU FFSR: TCPresent Position */
1466 #define TPIU_FFSR_TCPresent_Msk (1UL << TPIU_FFSR_TCPresent_Pos) /*!< TPIU FFSR: TCPresent Mask */
1467
1468 #define TPIU_FFSR_FtStopped_Pos 1U /*!< TPIU FFSR: FtStopped Position */
1469 #define TPIU_FFSR_FtStopped_Msk (1UL << TPIU_FFSR_FtStopped_Pos) /*!< TPIU FFSR: FtStopped Mask */
1470
1471 #define TPIU_FFSR_FlInProg_Pos 0U /*!< TPIU FFSR: FlInProg Position */
1472 #define TPIU_FFSR_FlInProg_Msk (1UL /*<< TPIU_FFSR_FlInProg_Pos*/) /*!< TPIU FFSR: FlInProg Mask */
1473
1474 /** \brief TPIU Formatter and Flush Control Register Definitions */
1475 #define TPIU_FFCR_TrigIn_Pos 8U /*!< TPIU FFCR: TrigIn Position */
1476 #define TPIU_FFCR_TrigIn_Msk (1UL << TPIU_FFCR_TrigIn_Pos) /*!< TPIU FFCR: TrigIn Mask */
1477
1478 #define TPIU_FFCR_FOnMan_Pos 6U /*!< TPIU FFCR: FOnMan Position */
1479 #define TPIU_FFCR_FOnMan_Msk (1UL << TPIU_FFCR_FOnMan_Pos) /*!< TPIU FFCR: FOnMan Mask */
1480
1481 #define TPIU_FFCR_EnFCont_Pos 1U /*!< TPIU FFCR: EnFCont Position */
1482 #define TPIU_FFCR_EnFCont_Msk (1UL << TPIU_FFCR_EnFCont_Pos) /*!< TPIU FFCR: EnFCont Mask */
1483
1484 /** \brief TPIU Periodic Synchronization Control Register Definitions */
1485 #define TPIU_PSCR_PSCount_Pos 0U /*!< TPIU PSCR: PSCount Position */
1486 #define TPIU_PSCR_PSCount_Msk (0x1FUL /*<< TPIU_PSCR_PSCount_Pos*/) /*!< TPIU PSCR: TPSCount Mask */
1487
1488 /** \brief TPIU TRIGGER Register Definitions */
1489 #define TPIU_TRIGGER_TRIGGER_Pos 0U /*!< TPIU TRIGGER: TRIGGER Position */
1490 #define TPIU_TRIGGER_TRIGGER_Msk (1UL /*<< TPIU_TRIGGER_TRIGGER_Pos*/) /*!< TPIU TRIGGER: TRIGGER Mask */
1491
1492 /** \brief TPIU Integration Test FIFO Test Data 0 Register Definitions */
1493 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD0: ATB Interface 2 ATVALIDPosition */
1494 #define TPIU_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 ATVALID Mask */
1495
1496 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD0: ATB Interface 2 byte count Position */
1497 #define TPIU_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 2 byte count Mask */
1498
1499 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Position */
1500 #define TPIU_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 ATVALID Mask */
1501
1502 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD0: ATB Interface 1 byte count Position */
1503 #define TPIU_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 byte countt Mask */
1504
1505 #define TPIU_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPIU ITFTTD0: ATB Interface 1 data2 Position */
1506 #define TPIU_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data2 Mask */
1507
1508 #define TPIU_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPIU ITFTTD0: ATB Interface 1 data1 Position */
1509 #define TPIU_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPIU_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPIU ITFTTD0: ATB Interface 1 data1 Mask */
1510
1511 #define TPIU_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPIU ITFTTD0: ATB Interface 1 data0 Position */
1512 #define TPIU_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPIU_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPIU ITFTTD0: ATB Interface 1 data0 Mask */
1513
1514 /** \brief TPIU Integration Test ATB Control Register 2 Register Definitions */
1515 #define TPIU_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID2S Position */
1516 #define TPIU_ITATBCTR2_AFVALID2S_Msk (1UL << TPIU_ITATBCTR2_AFVALID2S_Pos) /*!< TPIU ITATBCTR2: AFVALID2SS Mask */
1517
1518 #define TPIU_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR2: AFVALID1S Position */
1519 #define TPIU_ITATBCTR2_AFVALID1S_Msk (1UL << TPIU_ITATBCTR2_AFVALID1S_Pos) /*!< TPIU ITATBCTR2: AFVALID1SS Mask */
1520
1521 #define TPIU_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY2S Position */
1522 #define TPIU_ITATBCTR2_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY2S Mask */
1523
1524 #define TPIU_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR2: ATREADY1S Position */
1525 #define TPIU_ITATBCTR2_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR2: ATREADY1S Mask */
1526
1527 /** \brief TPIU Integration Test FIFO Test Data 1 Register Definitions */
1528 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Position */
1529 #define TPIU_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 ATVALID Mask */
1530
1531 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPIU ITFTTD1: ATB Interface 2 byte count Position */
1532 #define TPIU_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 byte count Mask */
1533
1534 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Position */
1535 #define TPIU_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 ATVALID Mask */
1536
1537 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPIU ITFTTD1: ATB Interface 1 byte count Position */
1538 #define TPIU_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPIU_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPIU ITFTTD1: ATB Interface 1 byte countt Mask */
1539
1540 #define TPIU_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPIU ITFTTD1: ATB Interface 2 data2 Position */
1541 #define TPIU_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data2 Mask */
1542
1543 #define TPIU_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPIU ITFTTD1: ATB Interface 2 data1 Position */
1544 #define TPIU_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPIU_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPIU ITFTTD1: ATB Interface 2 data1 Mask */
1545
1546 #define TPIU_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPIU ITFTTD1: ATB Interface 2 data0 Position */
1547 #define TPIU_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPIU_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPIU ITFTTD1: ATB Interface 2 data0 Mask */
1548
1549 /** \brief TPIU Integration Test ATB Control Register 0 Definitions */
1550 #define TPIU_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID2S Position */
1551 #define TPIU_ITATBCTR0_AFVALID2S_Msk (1UL << TPIU_ITATBCTR0_AFVALID2S_Pos) /*!< TPIU ITATBCTR0: AFVALID2SS Mask */
1552
1553 #define TPIU_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPIU ITATBCTR0: AFVALID1S Position */
1554 #define TPIU_ITATBCTR0_AFVALID1S_Msk (1UL << TPIU_ITATBCTR0_AFVALID1S_Pos) /*!< TPIU ITATBCTR0: AFVALID1SS Mask */
1555
1556 #define TPIU_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY2S Position */
1557 #define TPIU_ITATBCTR0_ATREADY2S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY2S Mask */
1558
1559 #define TPIU_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPIU ITATBCTR0: ATREADY1S Position */
1560 #define TPIU_ITATBCTR0_ATREADY1S_Msk (1UL /*<< TPIU_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPIU ITATBCTR0: ATREADY1S Mask */
1561
1562 /** \brief TPIU Integration Mode Control Register Definitions */
1563 #define TPIU_ITCTRL_Mode_Pos 0U /*!< TPIU ITCTRL: Mode Position */
1564 #define TPIU_ITCTRL_Mode_Msk (0x3UL /*<< TPIU_ITCTRL_Mode_Pos*/) /*!< TPIU ITCTRL: Mode Mask */
1565
1566 /** \brief TPIU DEVID Register Definitions */
1567 #define TPIU_DEVID_NRZVALID_Pos 11U /*!< TPIU DEVID: NRZVALID Position */
1568 #define TPIU_DEVID_NRZVALID_Msk (1UL << TPIU_DEVID_NRZVALID_Pos) /*!< TPIU DEVID: NRZVALID Mask */
1569
1570 #define TPIU_DEVID_MANCVALID_Pos 10U /*!< TPIU DEVID: MANCVALID Position */
1571 #define TPIU_DEVID_MANCVALID_Msk (1UL << TPIU_DEVID_MANCVALID_Pos) /*!< TPIU DEVID: MANCVALID Mask */
1572
1573 #define TPIU_DEVID_PTINVALID_Pos 9U /*!< TPIU DEVID: PTINVALID Position */
1574 #define TPIU_DEVID_PTINVALID_Msk (1UL << TPIU_DEVID_PTINVALID_Pos) /*!< TPIU DEVID: PTINVALID Mask */
1575
1576 #define TPIU_DEVID_FIFOSZ_Pos 6U /*!< TPIU DEVID: FIFOSZ Position */
1577 #define TPIU_DEVID_FIFOSZ_Msk (0x7UL << TPIU_DEVID_FIFOSZ_Pos) /*!< TPIU DEVID: FIFOSZ Mask */
1578
1579 #define TPIU_DEVID_NrTraceInput_Pos 0U /*!< TPIU DEVID: NrTraceInput Position */
1580 #define TPIU_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPIU_DEVID_NrTraceInput_Pos*/) /*!< TPIU DEVID: NrTraceInput Mask */
1581
1582 /** \brief TPIU DEVTYPE Register Definitions */
1583 #define TPIU_DEVTYPE_SubType_Pos 4U /*!< TPIU DEVTYPE: SubType Position */
1584 #define TPIU_DEVTYPE_SubType_Msk (0xFUL /*<< TPIU_DEVTYPE_SubType_Pos*/) /*!< TPIU DEVTYPE: SubType Mask */
1585
1586 #define TPIU_DEVTYPE_MajorType_Pos 0U /*!< TPIU DEVTYPE: MajorType Position */
1587 #define TPIU_DEVTYPE_MajorType_Msk (0xFUL << TPIU_DEVTYPE_MajorType_Pos) /*!< TPIU DEVTYPE: MajorType Mask */
1588
1589 /*@}*/ /* end of group CMSIS_TPIU */
1590
1591
1592 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1593 /**
1594 \ingroup CMSIS_core_register
1595 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1596 \brief Type definitions for the Memory Protection Unit (MPU)
1597 @{
1598 */
1599
1600 /**
1601 \brief Structure type to access the Memory Protection Unit (MPU).
1602 */
1603 typedef struct
1604 {
1605 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1606 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1607 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1608 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1609 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1610 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1611 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1612 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1613 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1614 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1615 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1616 uint32_t RESERVED0[1];
1617 union {
1618 __IOM uint32_t MAIR[2];
1619 struct {
1620 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1621 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1622 };
1623 };
1624 } MPU_Type;
1625
1626 #define MPU_TYPE_RALIASES 4U
1627
1628 /** \brief MPU Type Register Definitions */
1629 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1630 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1631
1632 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1633 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1634
1635 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1636 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1637
1638 /** \brief MPU Control Register Definitions */
1639 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1640 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1641
1642 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1643 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1644
1645 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1646 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1647
1648 /** \brief MPU Region Number Register Definitions */
1649 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1650 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1651
1652 /** \brief MPU Region Base Address Register Definitions */
1653 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1654 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1655
1656 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1657 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1658
1659 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1660 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1661
1662 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1663 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1664
1665 /** \brief MPU Region Limit Address Register Definitions */
1666 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1667 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1668
1669 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1670 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1671
1672 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1673 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Mask */
1674
1675 /** \brief MPU Memory Attribute Indirection Register 0 Definitions */
1676 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1677 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1678
1679 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1680 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1681
1682 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1683 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1684
1685 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1686 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1687
1688 /** \brief MPU Memory Attribute Indirection Register 1 Definitions */
1689 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1690 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1691
1692 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1693 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1694
1695 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1696 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1697
1698 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1699 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1700
1701 /*@} end of group CMSIS_MPU */
1702 #endif
1703
1704
1705 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1706 /**
1707 \ingroup CMSIS_core_register
1708 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1709 \brief Type definitions for the Security Attribution Unit (SAU)
1710 @{
1711 */
1712
1713 /**
1714 \brief Structure type to access the Security Attribution Unit (SAU).
1715 */
1716 typedef struct
1717 {
1718 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1719 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1720 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1721 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1722 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1723 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1724 #else
1725 uint32_t RESERVED0[3];
1726 #endif
1727 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1728 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1729 } SAU_Type;
1730
1731 /** \brief SAU Control Register Definitions */
1732 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1733 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1734
1735 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1736 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1737
1738 /** \brief SAU Type Register Definitions */
1739 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1740 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1741
1742 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1743 /** \brief SAU Region Number Register Definitions */
1744 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1745 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1746
1747 /** \brief SAU Region Base Address Register Definitions */
1748 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1749 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1750
1751 /** \brief SAU Region Limit Address Register Definitions */
1752 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1753 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1754
1755 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1756 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1757
1758 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1759 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1760
1761 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1762
1763 /** \brief SAU Secure Fault Status Register Definitions */
1764 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1765 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1766
1767 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1768 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1769
1770 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1771 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1772
1773 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1774 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1775
1776 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1777 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1778
1779 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1780 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1781
1782 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1783 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1784
1785 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1786 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1787
1788 /*@} end of group CMSIS_SAU */
1789 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1790
1791
1792 /**
1793 \ingroup CMSIS_core_register
1794 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1795 \brief Type definitions for the Floating Point Unit (FPU)
1796 @{
1797 */
1798
1799 /**
1800 \brief Structure type to access the Floating Point Unit (FPU).
1801 */
1802 typedef struct
1803 {
1804 uint32_t RESERVED0[1U];
1805 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1806 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1807 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1808 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1809 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1810 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1811 } FPU_Type;
1812
1813 /** \brief FPU Floating-Point Context Control Register Definitions */
1814 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1815 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1816
1817 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1818 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1819
1820 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1821 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1822
1823 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1824 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1825
1826 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1827 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1828
1829 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1830 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1831
1832 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1833 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1834
1835 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1836 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1837
1838 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1839 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1840
1841 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1842 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1843
1844 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1845 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1846
1847 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1848 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1849
1850 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1851 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1852
1853 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1854 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1855
1856 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1857 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1858
1859 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1860 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1861
1862 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1863 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1864
1865 /** \brief FPU Floating-Point Context Address Register Definitions */
1866 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1867 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1868
1869 /** \brief FPU Floating-Point Default Status Control Register Definitions */
1870 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1871 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1872
1873 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1874 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1875
1876 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1877 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1878
1879 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1880 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1881
1882 /** \brief FPU Media and VFP Feature Register 0 Definitions */
1883 #define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: Rounding modes bits Position */
1884 #define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: Rounding modes bits Mask */
1885
1886 #define FPU_MVFR0_FPShortvec_Pos 24U /*!< MVFR0: Short vectors bits Position */
1887 #define FPU_MVFR0_FPShortvec_Msk (0xFUL << FPU_MVFR0_FPShortvec_Pos) /*!< MVFR0: Short vectors bits Mask */
1888
1889 #define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: Square root bits Position */
1890 #define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: Square root bits Mask */
1891
1892 #define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: Divide bits Position */
1893 #define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */
1894
1895 #define FPU_MVFR0_FPExceptrap_Pos 12U /*!< MVFR0: Exception trapping bits Position */
1896 #define FPU_MVFR0_FPExceptrap_Msk (0xFUL << FPU_MVFR0_FPExceptrap_Pos) /*!< MVFR0: Exception trapping bits Mask */
1897
1898 #define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: Double-precision bits Position */
1899 #define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: Double-precision bits Mask */
1900
1901 #define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: Single-precision bits Position */
1902 #define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: Single-precision bits Mask */
1903
1904 #define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMD registers bits Position */
1905 #define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMD registers bits Mask */
1906
1907 /** \brief FPU Media and VFP Feature Register 1 Definitions */
1908 #define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: Fused MAC bits Position */
1909 #define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: Fused MAC bits Mask */
1910
1911 #define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1912 #define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1913
1914 #define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1915 #define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1916
1917 #define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1918 #define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1919
1920 /** \brief FPU Media and VFP Feature Register 2 Definitions */
1921 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: VFP Misc bits Position */
1922 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: VFP Misc bits Mask */
1923
1924 /*@} end of group CMSIS_FPU */
1925
1926
1927 /**
1928 \ingroup CMSIS_core_register
1929 \defgroup CMSIS_DCB Debug Control Block
1930 \brief Type definitions for the Debug Control Block Registers
1931 @{
1932 */
1933
1934 /**
1935 \brief Structure type to access the Debug Control Block Registers (DCB).
1936 */
1937 typedef struct
1938 {
1939 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1940 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1941 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1942 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1943 uint32_t RESERVED0[1U];
1944 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1945 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1946 } DCB_Type;
1947
1948 /** \brief DCB Debug Halting Control and Status Register Definitions */
1949 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1950 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1951
1952 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1953 #define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1954
1955 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1956 #define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1957
1958 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1959 #define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1960
1961 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1962 #define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1963
1964 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1965 #define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1966
1967 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1968 #define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1969
1970 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1971 #define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1972
1973 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1974 #define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1975
1976 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1977 #define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1978
1979 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1980 #define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1981
1982 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1983 #define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1984
1985 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1986 #define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1987
1988 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1989 #define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1990
1991 /** \brief DCB Debug Core Register Selector Register Definitions */
1992 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1993 #define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1994
1995 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1996 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1997
1998 /** \brief DCB Debug Core Register Data Register Definitions */
1999 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
2000 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
2001
2002 /** \brief DCB Debug Exception and Monitor Control Register Definitions */
2003 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
2004 #define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
2005
2006 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
2007 #define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
2008
2009 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
2010 #define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
2011
2012 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
2013 #define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
2014
2015 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
2016 #define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
2017
2018 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
2019 #define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
2020
2021 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
2022 #define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
2023
2024 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
2025 #define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
2026
2027 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
2028 #define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
2029
2030 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
2031 #define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
2032
2033 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
2034 #define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
2035
2036 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
2037 #define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
2038
2039 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
2040 #define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
2041
2042 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
2043 #define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
2044
2045 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
2046 #define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
2047
2048 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
2049 #define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
2050
2051 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
2052 #define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
2053
2054 /** \brief DCB Debug Authentication Control Register Definitions */
2055 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
2056 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
2057
2058 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
2059 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
2060
2061 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
2062 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
2063
2064 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
2065 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
2066
2067 /** \brief DCB Debug Security Control and Status Register Definitions */
2068 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
2069 #define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
2070
2071 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
2072 #define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
2073
2074 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
2075 #define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
2076
2077 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
2078 #define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
2079
2080 /*@} end of group CMSIS_DCB */
2081
2082
2083 /**
2084 \ingroup CMSIS_core_register
2085 \defgroup CMSIS_DIB Debug Identification Block
2086 \brief Type definitions for the Debug Identification Block Registers
2087 @{
2088 */
2089
2090 /**
2091 \brief Structure type to access the Debug Identification Block Registers (DIB).
2092 */
2093 typedef struct
2094 {
2095 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
2096 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
2097 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
2098 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
2099 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
2100 } DIB_Type;
2101
2102 /** \brief DIB SCS Software Lock Access Register Definitions */
2103 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
2104 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
2105
2106 /** \brief DIB SCS Software Lock Status Register Definitions */
2107 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
2108 #define DIB_DLSR_nTT_Msk (1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
2109
2110 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
2111 #define DIB_DLSR_SLK_Msk (1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
2112
2113 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
2114 #define DIB_DLSR_SLI_Msk (1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
2115
2116 /** \brief DIB Debug Authentication Status Register Definitions */
2117 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
2118 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
2119
2120 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
2121 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
2122
2123 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
2124 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
2125
2126 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
2127 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
2128
2129 /** \brief DIB SCS Device Architecture Register Definitions */
2130 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
2131 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
2132
2133 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
2134 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
2135
2136 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
2137 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
2138
2139 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
2140 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
2141
2142 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
2143 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
2144
2145 /** \brief DIB SCS Device Type Register Definitions */
2146 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
2147 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
2148
2149 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
2150 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2151
2152 /*@} end of group CMSIS_DIB */
2153
2154
2155 /**
2156 \ingroup CMSIS_core_register
2157 \defgroup CMSIS_core_bitfield Core register bit field macros
2158 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2159 @{
2160 */
2161
2162 /**
2163 \brief Mask and shift a bit field value for use in a register bit range.
2164 \param[in] field Name of the register bit field.
2165 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2166 \return Masked and shifted value.
2167 */
2168 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2169
2170 /**
2171 \brief Mask and shift a register value to extract a bit field value.
2172 \param[in] field Name of the register bit field.
2173 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2174 \return Masked and shifted bit field value.
2175 */
2176 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2177
2178 /*@} end of group CMSIS_core_bitfield */
2179
2180
2181 /**
2182 \ingroup CMSIS_core_register
2183 \defgroup CMSIS_core_base Core Definitions
2184 \brief Definitions for base addresses, unions, and structures.
2185 @{
2186 */
2187
2188 /* Memory mapping of Core Hardware */
2189 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2190 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2191 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2192 #define BPU_BASE (0xE0002000UL) /*!< BPU Base Address */
2193 #define TPIU_BASE (0xE0040000UL) /*!< TPIU Base Address */
2194 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2195 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2196 #define EMSS_BASE (0xE001E000UL) /*!<Enhanced Memory SubSystem Base Address */
2197
2198 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2199 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2200 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2201
2202 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2203 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2204 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2205 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2206 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2207 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2208 #define BPU ((BPU_Type *) BPU_BASE ) /*!< BPU configuration struct */
2209 #define TPIU ((TPIU_Type *) TPIU_BASE ) /*!< TPIU configuration struct */
2210 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2211 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2212 #define EMSS ((EMSS_Type *) EMSS_BASE ) /*!<Ehanced MSS Registers struct */
2213
2214 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2215 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2216 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2217 #endif
2218
2219 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2220 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2221 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2222 #endif
2223
2224 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2225 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2226
2227 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2228 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2229 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2230 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2231 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2232 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2233 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2234
2235 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2236 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2237 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2238 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2239 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2240 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2241
2242 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2243 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2244 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2245 #endif
2246
2247 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2248 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2249
2250 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2251 /*@} */
2252
2253
2254 /**
2255 \defgroup CMSIS_deprecated_aliases Backwards Compatibility Aliases
2256 \brief Alias definitions present for backwards compatibility for deprecated symbols.
2257 @{
2258 */
2259
2260 #ifndef CMSIS_DISABLE_DEPRECATED
2261
2262 #define SCB_AIRCR_ENDIANESS_Pos SCB_AIRCR_ENDIANNESS_Pos
2263 #define SCB_AIRCR_ENDIANESS_Msk SCB_AIRCR_ENDIANNESS_Msk
2264
2265 #endif // CMSIS_DISABLE_DEPRECATED
2266
2267 /*@} */
2268
2269
2270 /*******************************************************************************
2271 * Hardware Abstraction Layer
2272 Core Function Interface contains:
2273 - Core NVIC Functions
2274 - Core SysTick Functions
2275 - Core Debug Functions
2276 - Core Register Access Functions
2277 ******************************************************************************/
2278 /**
2279 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2280 */
2281
2282
2283
2284 /* ########################## NVIC functions #################################### */
2285 /**
2286 \ingroup CMSIS_Core_FunctionInterface
2287 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2288 \brief Functions that manage interrupts and exceptions via the NVIC.
2289 @{
2290 */
2291
2292 #ifdef CMSIS_NVIC_VIRTUAL
2293 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2294 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2295 #endif
2296 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2297 #else
2298 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2299 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2300 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2301 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2302 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2303 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2304 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2305 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2306 #define NVIC_GetActive __NVIC_GetActive
2307 #define NVIC_SetPriority __NVIC_SetPriority
2308 #define NVIC_GetPriority __NVIC_GetPriority
2309 #define NVIC_SystemReset __NVIC_SystemReset
2310 #define SW_SystemReset __SW_SystemReset
2311 #endif /* CMSIS_NVIC_VIRTUAL */
2312
2313 #ifdef CMSIS_VECTAB_VIRTUAL
2314 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2315 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2316 #endif
2317 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2318 #else
2319 #define NVIC_SetVector __NVIC_SetVector
2320 #define NVIC_GetVector __NVIC_GetVector
2321 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2322
2323 #define NVIC_USER_IRQ_OFFSET 16
2324
2325
2326 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2327
2328 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2329 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2330
2331 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2332 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2333 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2334 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2335 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2336 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2337 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2338 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2339
2340 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2341 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2342 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2343 #else
2344 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2345 #endif
2346
2347
2348 /**
2349 \brief Set Priority Grouping
2350 \details Sets the priority grouping field using the required unlock sequence.
2351 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2352 Only values from 0..7 are used.
2353 In case of a conflict between priority grouping and available
2354 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2355 \param [in] PriorityGroup Priority grouping field.
2356 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2357 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2358 {
2359 uint32_t reg_value;
2360 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2361
2362 reg_value = SCB->AIRCR; /* read old register configuration */
2363 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2364 reg_value = (reg_value |
2365 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2366 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2367 SCB->AIRCR = reg_value;
2368 }
2369
2370
2371 /**
2372 \brief Get Priority Grouping
2373 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2374 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2375 */
__NVIC_GetPriorityGrouping(void)2376 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2377 {
2378 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2379 }
2380
2381
2382 /**
2383 \brief Enable Interrupt
2384 \details Enables a device specific interrupt in the NVIC interrupt controller.
2385 \param [in] IRQn Device specific interrupt number.
2386 \note IRQn must not be negative.
2387 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2388 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2389 {
2390 if ((int32_t)(IRQn) >= 0)
2391 {
2392 __COMPILER_BARRIER();
2393 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2394 __COMPILER_BARRIER();
2395 }
2396 }
2397
2398
2399 /**
2400 \brief Get Interrupt Enable status
2401 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2402 \param [in] IRQn Device specific interrupt number.
2403 \return 0 Interrupt is not enabled.
2404 \return 1 Interrupt is enabled.
2405 \note IRQn must not be negative.
2406 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2407 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2408 {
2409 if ((int32_t)(IRQn) >= 0)
2410 {
2411 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2412 }
2413 else
2414 {
2415 return(0U);
2416 }
2417 }
2418
2419
2420 /**
2421 \brief Disable Interrupt
2422 \details Disables a device specific interrupt in the NVIC interrupt controller.
2423 \param [in] IRQn Device specific interrupt number.
2424 \note IRQn must not be negative.
2425 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2426 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2427 {
2428 if ((int32_t)(IRQn) >= 0)
2429 {
2430 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2431 __DSB();
2432 __ISB();
2433 }
2434 }
2435
2436
2437 /**
2438 \brief Get Pending Interrupt
2439 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2440 \param [in] IRQn Device specific interrupt number.
2441 \return 0 Interrupt status is not pending.
2442 \return 1 Interrupt status is pending.
2443 \note IRQn must not be negative.
2444 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2445 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2446 {
2447 if ((int32_t)(IRQn) >= 0)
2448 {
2449 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2450 }
2451 else
2452 {
2453 return(0U);
2454 }
2455 }
2456
2457
2458 /**
2459 \brief Set Pending Interrupt
2460 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2461 \param [in] IRQn Device specific interrupt number.
2462 \note IRQn must not be negative.
2463 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2464 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2465 {
2466 if ((int32_t)(IRQn) >= 0)
2467 {
2468 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2469 }
2470 }
2471
2472
2473 /**
2474 \brief Clear Pending Interrupt
2475 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2476 \param [in] IRQn Device specific interrupt number.
2477 \note IRQn must not be negative.
2478 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2479 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2480 {
2481 if ((int32_t)(IRQn) >= 0)
2482 {
2483 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2484 }
2485 }
2486
2487
2488 /**
2489 \brief Get Active Interrupt
2490 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2491 \param [in] IRQn Device specific interrupt number.
2492 \return 0 Interrupt status is not active.
2493 \return 1 Interrupt status is active.
2494 \note IRQn must not be negative.
2495 */
__NVIC_GetActive(IRQn_Type IRQn)2496 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2497 {
2498 if ((int32_t)(IRQn) >= 0)
2499 {
2500 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2501 }
2502 else
2503 {
2504 return(0U);
2505 }
2506 }
2507
2508
2509 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2510 /**
2511 \brief Get Interrupt Target State
2512 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2513 \param [in] IRQn Device specific interrupt number.
2514 \return 0 if interrupt is assigned to Secure
2515 \return 1 if interrupt is assigned to Non Secure
2516 \note IRQn must not be negative.
2517 */
NVIC_GetTargetState(IRQn_Type IRQn)2518 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2519 {
2520 if ((int32_t)(IRQn) >= 0)
2521 {
2522 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2523 }
2524 else
2525 {
2526 return(0U);
2527 }
2528 }
2529
2530
2531 /**
2532 \brief Set Interrupt Target State
2533 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2534 \param [in] IRQn Device specific interrupt number.
2535 \return 0 if interrupt is assigned to Secure
2536 1 if interrupt is assigned to Non Secure
2537 \note IRQn must not be negative.
2538 */
NVIC_SetTargetState(IRQn_Type IRQn)2539 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2540 {
2541 if ((int32_t)(IRQn) >= 0)
2542 {
2543 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2544 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2545 }
2546 else
2547 {
2548 return(0U);
2549 }
2550 }
2551
2552
2553 /**
2554 \brief Clear Interrupt Target State
2555 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2556 \param [in] IRQn Device specific interrupt number.
2557 \return 0 if interrupt is assigned to Secure
2558 1 if interrupt is assigned to Non Secure
2559 \note IRQn must not be negative.
2560 */
NVIC_ClearTargetState(IRQn_Type IRQn)2561 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2562 {
2563 if ((int32_t)(IRQn) >= 0)
2564 {
2565 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2566 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2567 }
2568 else
2569 {
2570 return(0U);
2571 }
2572 }
2573 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2574
2575
2576 /**
2577 \brief Set Interrupt Priority
2578 \details Sets the priority of a device specific interrupt or a processor exception.
2579 The interrupt number can be positive to specify a device specific interrupt,
2580 or negative to specify a processor exception.
2581 \param [in] IRQn Interrupt number.
2582 \param [in] priority Priority to set.
2583 \note The priority cannot be set for every processor exception.
2584 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2585 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2586 {
2587 if ((int32_t)(IRQn) >= 0)
2588 {
2589 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2590 }
2591 else
2592 {
2593 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2594 }
2595 }
2596
2597
2598 /**
2599 \brief Get Interrupt Priority
2600 \details Reads the priority of a device specific interrupt or a processor exception.
2601 The interrupt number can be positive to specify a device specific interrupt,
2602 or negative to specify a processor exception.
2603 \param [in] IRQn Interrupt number.
2604 \return Interrupt Priority.
2605 Value is aligned automatically to the implemented priority bits of the microcontroller.
2606 */
__NVIC_GetPriority(IRQn_Type IRQn)2607 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2608 {
2609
2610 if ((int32_t)(IRQn) >= 0)
2611 {
2612 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2613 }
2614 else
2615 {
2616 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2617 }
2618 }
2619
2620
2621 /**
2622 \brief Encode Priority
2623 \details Encodes the priority for an interrupt with the given priority group,
2624 preemptive priority value, and subpriority value.
2625 In case of a conflict between priority grouping and available
2626 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2627 \param [in] PriorityGroup Used priority group.
2628 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2629 \param [in] SubPriority Subpriority value (starting from 0).
2630 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2631 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2632 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2633 {
2634 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2635 uint32_t PreemptPriorityBits;
2636 uint32_t SubPriorityBits;
2637
2638 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2639 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2640
2641 return (
2642 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2643 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2644 );
2645 }
2646
2647
2648 /**
2649 \brief Decode Priority
2650 \details Decodes an interrupt priority value with a given priority group to
2651 preemptive priority value and subpriority value.
2652 In case of a conflict between priority grouping and available
2653 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2654 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2655 \param [in] PriorityGroup Used priority group.
2656 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2657 \param [out] pSubPriority Subpriority value (starting from 0).
2658 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2659 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2660 {
2661 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2662 uint32_t PreemptPriorityBits;
2663 uint32_t SubPriorityBits;
2664
2665 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2666 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2667
2668 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2669 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2670 }
2671
2672
2673 /**
2674 \brief Set Interrupt Vector
2675 \details Sets an interrupt vector in SRAM based interrupt vector table.
2676 The interrupt number can be positive to specify a device specific interrupt,
2677 or negative to specify a processor exception.
2678 VTOR must been relocated to SRAM before.
2679 \param [in] IRQn Interrupt number
2680 \param [in] vector Address of interrupt handler function
2681 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2682 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2683 {
2684 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2685 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2686 __DSB();
2687 }
2688
2689
2690 /**
2691 \brief Get Interrupt Vector
2692 \details Reads an interrupt vector from interrupt vector table.
2693 The interrupt number can be positive to specify a device specific interrupt,
2694 or negative to specify a processor exception.
2695 \param [in] IRQn Interrupt number.
2696 \return Address of interrupt handler function
2697 */
__NVIC_GetVector(IRQn_Type IRQn)2698 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2699 {
2700 uint32_t *vectors = (uint32_t *) ((uintptr_t) SCB->VTOR);
2701 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2702 }
2703
2704
2705 /**
2706 \brief System Reset
2707 \details Initiates a system reset request to reset the MCU.
2708 */
__NVIC_SystemReset(void)2709 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2710 {
2711 __DSB(); /* Ensure all outstanding memory accesses included
2712 buffered write are completed before reset */
2713 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2714 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2715 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2716 __DSB(); /* Ensure completion of memory access */
2717
2718 for(;;) /* wait until reset */
2719 {
2720 __NOP();
2721 }
2722 }
2723
2724 /**
2725 \brief Software Reset
2726 \details Initiates a system reset request to reset the CPU.
2727 */
__SW_SystemReset(void)2728 __NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
2729 {
2730 __DSB(); /* Ensure all outstanding memory accesses including
2731 buffered write are completed before reset */
2732 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2733 (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
2734 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
2735 SCB_AIRCR_SYSRESETREQ_Msk );
2736 __DSB(); /* Ensure completion of memory access */
2737
2738 for(;;) /* wait until reset */
2739 {
2740 __NOP();
2741 }
2742 }
2743
2744
2745 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2746 /**
2747 \brief Set Priority Grouping (non-secure)
2748 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2749 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2750 Only values from 0..7 are used.
2751 In case of a conflict between priority grouping and available
2752 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2753 \param [in] PriorityGroup Priority grouping field.
2754 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2755 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2756 {
2757 uint32_t reg_value;
2758 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2759
2760 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2761 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2762 reg_value = (reg_value |
2763 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2764 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2765 SCB_NS->AIRCR = reg_value;
2766 }
2767
2768
2769 /**
2770 \brief Get Priority Grouping (non-secure)
2771 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2772 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2773 */
TZ_NVIC_GetPriorityGrouping_NS(void)2774 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2775 {
2776 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2777 }
2778
2779
2780 /**
2781 \brief Enable Interrupt (non-secure)
2782 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2783 \param [in] IRQn Device specific interrupt number.
2784 \note IRQn must not be negative.
2785 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2786 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2787 {
2788 if ((int32_t)(IRQn) >= 0)
2789 {
2790 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2791 }
2792 }
2793
2794
2795 /**
2796 \brief Get Interrupt Enable status (non-secure)
2797 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2798 \param [in] IRQn Device specific interrupt number.
2799 \return 0 Interrupt is not enabled.
2800 \return 1 Interrupt is enabled.
2801 \note IRQn must not be negative.
2802 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2803 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2804 {
2805 if ((int32_t)(IRQn) >= 0)
2806 {
2807 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2808 }
2809 else
2810 {
2811 return(0U);
2812 }
2813 }
2814
2815
2816 /**
2817 \brief Disable Interrupt (non-secure)
2818 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2819 \param [in] IRQn Device specific interrupt number.
2820 \note IRQn must not be negative.
2821 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2822 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2823 {
2824 if ((int32_t)(IRQn) >= 0)
2825 {
2826 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2827 }
2828 }
2829
2830
2831 /**
2832 \brief Get Pending Interrupt (non-secure)
2833 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2834 \param [in] IRQn Device specific interrupt number.
2835 \return 0 Interrupt status is not pending.
2836 \return 1 Interrupt status is pending.
2837 \note IRQn must not be negative.
2838 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2839 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2840 {
2841 if ((int32_t)(IRQn) >= 0)
2842 {
2843 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2844 }
2845 else
2846 {
2847 return(0U);
2848 }
2849 }
2850
2851
2852 /**
2853 \brief Set Pending Interrupt (non-secure)
2854 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2855 \param [in] IRQn Device specific interrupt number.
2856 \note IRQn must not be negative.
2857 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2858 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2859 {
2860 if ((int32_t)(IRQn) >= 0)
2861 {
2862 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2863 }
2864 }
2865
2866
2867 /**
2868 \brief Clear Pending Interrupt (non-secure)
2869 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2870 \param [in] IRQn Device specific interrupt number.
2871 \note IRQn must not be negative.
2872 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2873 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2874 {
2875 if ((int32_t)(IRQn) >= 0)
2876 {
2877 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2878 }
2879 }
2880
2881
2882 /**
2883 \brief Get Active Interrupt (non-secure)
2884 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2885 \param [in] IRQn Device specific interrupt number.
2886 \return 0 Interrupt status is not active.
2887 \return 1 Interrupt status is active.
2888 \note IRQn must not be negative.
2889 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2890 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2891 {
2892 if ((int32_t)(IRQn) >= 0)
2893 {
2894 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2895 }
2896 else
2897 {
2898 return(0U);
2899 }
2900 }
2901
2902
2903 /**
2904 \brief Set Interrupt Priority (non-secure)
2905 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2906 The interrupt number can be positive to specify a device specific interrupt,
2907 or negative to specify a processor exception.
2908 \param [in] IRQn Interrupt number.
2909 \param [in] priority Priority to set.
2910 \note The priority cannot be set for every non-secure processor exception.
2911 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2912 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2913 {
2914 if ((int32_t)(IRQn) >= 0)
2915 {
2916 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2917 }
2918 else
2919 {
2920 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2921 }
2922 }
2923
2924
2925 /**
2926 \brief Get Interrupt Priority (non-secure)
2927 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2928 The interrupt number can be positive to specify a device specific interrupt,
2929 or negative to specify a processor exception.
2930 \param [in] IRQn Interrupt number.
2931 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2932 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2933 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2934 {
2935
2936 if ((int32_t)(IRQn) >= 0)
2937 {
2938 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2939 }
2940 else
2941 {
2942 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2943 }
2944 }
2945 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2946
2947 /*@} end of CMSIS_Core_NVICFunctions */
2948
2949 /* ########################## MPU functions #################################### */
2950
2951 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2952
2953 #include "m-profile/armv8m_mpu.h"
2954
2955 #endif
2956
2957
2958 /* ########################## FPU functions #################################### */
2959 /**
2960 \ingroup CMSIS_Core_FunctionInterface
2961 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2962 \brief Function that provides FPU type.
2963 @{
2964 */
2965
2966 /**
2967 \brief get FPU type
2968 \details returns the FPU type
2969 \returns
2970 - \b 0: No FPU
2971 - \b 1: Single precision FPU
2972 - \b 2: Double + Single precision FPU
2973 */
SCB_GetFPUType(void)2974 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2975 {
2976 uint32_t mvfr0;
2977
2978 mvfr0 = FPU->MVFR0;
2979 if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U)
2980 {
2981 return 2U; /* Double + Single precision FPU */
2982 }
2983 else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U)
2984 {
2985 return 1U; /* Single precision FPU */
2986 }
2987 else
2988 {
2989 return 0U; /* No FPU */
2990 }
2991 }
2992
2993
2994 /*@} end of CMSIS_Core_FpuFunctions */
2995
2996
2997
2998 /* ########################## SAU functions #################################### */
2999 /**
3000 \ingroup CMSIS_Core_FunctionInterface
3001 \defgroup CMSIS_Core_SAUFunctions SAU Functions
3002 \brief Functions that configure the SAU.
3003 @{
3004 */
3005
3006 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3007
3008 /**
3009 \brief Enable SAU
3010 \details Enables the Security Attribution Unit (SAU).
3011 */
TZ_SAU_Enable(void)3012 __STATIC_INLINE void TZ_SAU_Enable(void)
3013 {
3014 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
3015 }
3016
3017
3018
3019 /**
3020 \brief Disable SAU
3021 \details Disables the Security Attribution Unit (SAU).
3022 */
TZ_SAU_Disable(void)3023 __STATIC_INLINE void TZ_SAU_Disable(void)
3024 {
3025 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
3026 }
3027
3028 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3029
3030 /*@} end of CMSIS_Core_SAUFunctions */
3031
3032
3033
3034
3035 /* ################################## Debug Control function ############################################ */
3036 /**
3037 \ingroup CMSIS_Core_FunctionInterface
3038 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
3039 \brief Functions that access the Debug Control Block.
3040 @{
3041 */
3042
3043
3044 /**
3045 \brief Set Debug Authentication Control Register
3046 \details writes to Debug Authentication Control register.
3047 \param [in] value value to be writen.
3048 */
DCB_SetAuthCtrl(uint32_t value)3049 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
3050 {
3051 __DSB();
3052 __ISB();
3053 DCB->DAUTHCTRL = value;
3054 __DSB();
3055 __ISB();
3056 }
3057
3058
3059 /**
3060 \brief Get Debug Authentication Control Register
3061 \details Reads Debug Authentication Control register.
3062 \return Debug Authentication Control Register.
3063 */
DCB_GetAuthCtrl(void)3064 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
3065 {
3066 return (DCB->DAUTHCTRL);
3067 }
3068
3069
3070 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3071 /**
3072 \brief Set Debug Authentication Control Register (non-secure)
3073 \details writes to non-secure Debug Authentication Control register when in secure state.
3074 \param [in] value value to be writen
3075 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)3076 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
3077 {
3078 __DSB();
3079 __ISB();
3080 DCB_NS->DAUTHCTRL = value;
3081 __DSB();
3082 __ISB();
3083 }
3084
3085
3086 /**
3087 \brief Get Debug Authentication Control Register (non-secure)
3088 \details Reads non-secure Debug Authentication Control register when in secure state.
3089 \return Debug Authentication Control Register.
3090 */
TZ_DCB_GetAuthCtrl_NS(void)3091 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3092 {
3093 return (DCB_NS->DAUTHCTRL);
3094 }
3095 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3096
3097 /*@} end of CMSIS_Core_DCBFunctions */
3098
3099
3100
3101
3102 /* ################################## Debug Identification function ############################################ */
3103 /**
3104 \ingroup CMSIS_Core_FunctionInterface
3105 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
3106 \brief Functions that access the Debug Identification Block.
3107 @{
3108 */
3109
3110
3111 /**
3112 \brief Get Debug Authentication Status Register
3113 \details Reads Debug Authentication Status register.
3114 \return Debug Authentication Status Register.
3115 */
DIB_GetAuthStatus(void)3116 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3117 {
3118 return (DIB->DAUTHSTATUS);
3119 }
3120
3121
3122 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3123 /**
3124 \brief Get Debug Authentication Status Register (non-secure)
3125 \details Reads non-secure Debug Authentication Status register when in secure state.
3126 \return Debug Authentication Status Register.
3127 */
TZ_DIB_GetAuthStatus_NS(void)3128 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3129 {
3130 return (DIB_NS->DAUTHSTATUS);
3131 }
3132 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3133
3134 /*@} end of CMSIS_Core_DCBFunctions */
3135
3136
3137 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3138 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3139
3140 /* ########################## Cache functions #################################### */
3141 /**
3142 \ingroup CMSIS_Core_FunctionInterface
3143 \defgroup CMSIS_Core_CacheFunctions Cache Functions
3144 \brief Functions that configure Instruction and Data cache.
3145 @{
3146 */
3147
3148 /* Cache Size ID Register Macros */
3149 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
3150 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
3151
3152 #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3153 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3154
3155 /**
3156 \brief Enable I-Cache
3157 \details Turns on I-Cache
3158 */
SCB_EnableICache(void)3159 __STATIC_FORCEINLINE void SCB_EnableICache (void)
3160 {
3161 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3162 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
3163
3164 __DSB();
3165 __ISB();
3166 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3167 __DSB();
3168 __ISB();
3169 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
3170 __DSB();
3171 __ISB();
3172 #endif
3173 }
3174
3175
3176 /**
3177 \brief Disable I-Cache
3178 \details Turns off I-Cache
3179 */
SCB_DisableICache(void)3180 __STATIC_FORCEINLINE void SCB_DisableICache (void)
3181 {
3182 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3183 __DSB();
3184 __ISB();
3185 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
3186 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3187 __DSB();
3188 __ISB();
3189 #endif
3190 }
3191
3192
3193 /**
3194 \brief Invalidate I-Cache
3195 \details Invalidates I-Cache
3196 */
SCB_InvalidateICache(void)3197 __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
3198 {
3199 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3200 __DSB();
3201 __ISB();
3202 SCB->ICIALLU = 0UL;
3203 __DSB();
3204 __ISB();
3205 #endif
3206 }
3207
3208
3209 /**
3210 \brief I-Cache Invalidate by address
3211 \details Invalidates I-Cache for the given address.
3212 I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3213 I-Cache memory blocks which are part of given address + given size are invalidated.
3214 \param[in] addr address
3215 \param[in] isize size of memory block (in number of bytes)
3216 */
SCB_InvalidateICache_by_Addr(void * addr,int32_t isize)3217 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
3218 {
3219 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3220 if ( isize > 0 ) {
3221 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
3222 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
3223
3224 __DSB();
3225
3226 do {
3227 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3228 op_addr += __SCB_ICACHE_LINE_SIZE;
3229 op_size -= __SCB_ICACHE_LINE_SIZE;
3230 } while ( op_size > 0 );
3231
3232 __DSB();
3233 __ISB();
3234 }
3235 #endif
3236 }
3237
3238
3239 /**
3240 \brief Enable D-Cache
3241 \details Turns on D-Cache
3242 */
SCB_EnableDCache(void)3243 __STATIC_FORCEINLINE void SCB_EnableDCache (void)
3244 {
3245 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3246 uint32_t ccsidr;
3247 uint32_t sets;
3248 uint32_t ways;
3249
3250 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
3251
3252 SCB->CSSELR = 0U; /* select Level 1 data cache */
3253 __DSB();
3254
3255 ccsidr = SCB->CCSIDR;
3256
3257 /* invalidate D-Cache */
3258 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3259 do {
3260 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3261 do {
3262 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3263 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3264 #if defined ( __CC_ARM )
3265 __schedule_barrier();
3266 #endif
3267 } while (ways-- != 0U);
3268 } while(sets-- != 0U);
3269 __DSB();
3270
3271 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
3272
3273 __DSB();
3274 __ISB();
3275 #endif
3276 }
3277
3278
3279 /**
3280 \brief Disable D-Cache
3281 \details Turns off D-Cache
3282 */
SCB_DisableDCache(void)3283 __STATIC_FORCEINLINE void SCB_DisableDCache (void)
3284 {
3285 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3286 uint32_t ccsidr;
3287 uint32_t sets;
3288 uint32_t ways;
3289
3290 SCB->CSSELR = 0U; /* select Level 1 data cache */
3291 __DSB();
3292
3293 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
3294 __DSB();
3295
3296 ccsidr = SCB->CCSIDR;
3297
3298 /* clean & invalidate D-Cache */
3299 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3300 do {
3301 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3302 do {
3303 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3304 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3305 #if defined ( __CC_ARM )
3306 __schedule_barrier();
3307 #endif
3308 } while (ways-- != 0U);
3309 } while(sets-- != 0U);
3310
3311 __DSB();
3312 __ISB();
3313 #endif
3314 }
3315
3316
3317 /**
3318 \brief Invalidate D-Cache
3319 \details Invalidates D-Cache
3320 */
SCB_InvalidateDCache(void)3321 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
3322 {
3323 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3324 uint32_t ccsidr;
3325 uint32_t sets;
3326 uint32_t ways;
3327
3328 SCB->CSSELR = 0U; /* select Level 1 data cache */
3329 __DSB();
3330
3331 ccsidr = SCB->CCSIDR;
3332
3333 /* invalidate D-Cache */
3334 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3335 do {
3336 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3337 do {
3338 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3339 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3340 #if defined ( __CC_ARM )
3341 __schedule_barrier();
3342 #endif
3343 } while (ways-- != 0U);
3344 } while(sets-- != 0U);
3345
3346 __DSB();
3347 __ISB();
3348 #endif
3349 }
3350
3351
3352 /**
3353 \brief Clean D-Cache
3354 \details Cleans D-Cache
3355 */
SCB_CleanDCache(void)3356 __STATIC_FORCEINLINE void SCB_CleanDCache (void)
3357 {
3358 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3359 uint32_t ccsidr;
3360 uint32_t sets;
3361 uint32_t ways;
3362
3363 SCB->CSSELR = 0U; /* select Level 1 data cache */
3364 __DSB();
3365
3366 ccsidr = SCB->CCSIDR;
3367
3368 /* clean D-Cache */
3369 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3370 do {
3371 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3372 do {
3373 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
3374 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
3375 #if defined ( __CC_ARM )
3376 __schedule_barrier();
3377 #endif
3378 } while (ways-- != 0U);
3379 } while(sets-- != 0U);
3380
3381 __DSB();
3382 __ISB();
3383 #endif
3384 }
3385
3386
3387 /**
3388 \brief Clean & Invalidate D-Cache
3389 \details Cleans and Invalidates D-Cache
3390 */
SCB_CleanInvalidateDCache(void)3391 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
3392 {
3393 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3394 uint32_t ccsidr;
3395 uint32_t sets;
3396 uint32_t ways;
3397
3398 SCB->CSSELR = 0U; /* select Level 1 data cache */
3399 __DSB();
3400
3401 ccsidr = SCB->CCSIDR;
3402
3403 /* clean & invalidate D-Cache */
3404 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3405 do {
3406 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3407 do {
3408 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3409 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3410 #if defined ( __CC_ARM )
3411 __schedule_barrier();
3412 #endif
3413 } while (ways-- != 0U);
3414 } while(sets-- != 0U);
3415
3416 __DSB();
3417 __ISB();
3418 #endif
3419 }
3420
3421
3422 /**
3423 \brief D-Cache Invalidate by address
3424 \details Invalidates D-Cache for the given address.
3425 D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3426 D-Cache memory blocks which are part of given address + given size are invalidated.
3427 \param[in] addr address
3428 \param[in] dsize size of memory block (in number of bytes)
3429 */
SCB_InvalidateDCache_by_Addr(void * addr,int32_t dsize)3430 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
3431 {
3432 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3433 if ( dsize > 0 ) {
3434 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3435 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3436
3437 __DSB();
3438
3439 do {
3440 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3441 op_addr += __SCB_DCACHE_LINE_SIZE;
3442 op_size -= __SCB_DCACHE_LINE_SIZE;
3443 } while ( op_size > 0 );
3444
3445 __DSB();
3446 __ISB();
3447 }
3448 #endif
3449 }
3450
3451
3452 /**
3453 \brief D-Cache Clean by address
3454 \details Cleans D-Cache for the given address
3455 D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
3456 D-Cache memory blocks which are part of given address + given size are cleaned.
3457 \param[in] addr address
3458 \param[in] dsize size of memory block (in number of bytes)
3459 */
SCB_CleanDCache_by_Addr(uint32_t * addr,int32_t dsize)3460 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
3461 {
3462 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3463 if ( dsize > 0 ) {
3464 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3465 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3466
3467 __DSB();
3468
3469 do {
3470 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3471 op_addr += __SCB_DCACHE_LINE_SIZE;
3472 op_size -= __SCB_DCACHE_LINE_SIZE;
3473 } while ( op_size > 0 );
3474
3475 __DSB();
3476 __ISB();
3477 }
3478 #endif
3479 }
3480
3481
3482 /**
3483 \brief D-Cache Clean and Invalidate by address
3484 \details Cleans and invalidates D_Cache for the given address
3485 D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
3486 D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
3487 \param[in] addr address (aligned to 32-byte boundary)
3488 \param[in] dsize size of memory block (in number of bytes)
3489 */
SCB_CleanInvalidateDCache_by_Addr(uint32_t * addr,int32_t dsize)3490 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
3491 {
3492 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3493 if ( dsize > 0 ) {
3494 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3495 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3496
3497 __DSB();
3498
3499 do {
3500 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3501 op_addr += __SCB_DCACHE_LINE_SIZE;
3502 op_size -= __SCB_DCACHE_LINE_SIZE;
3503 } while ( op_size > 0 );
3504
3505 __DSB();
3506 __ISB();
3507 }
3508 #endif
3509 }
3510
3511 /*@} end of CMSIS_Core_CacheFunctions */
3512 #endif
3513
3514
3515 /* ################################## SysTick function ############################################ */
3516 /**
3517 \ingroup CMSIS_Core_FunctionInterface
3518 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
3519 \brief Functions that configure the System.
3520 @{
3521 */
3522
3523 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3524
3525 /**
3526 \brief System Tick Configuration
3527 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
3528 Counter is in free running mode to generate periodic interrupts.
3529 \param [in] ticks Number of ticks between two interrupts.
3530 \return 0 Function succeeded.
3531 \return 1 Function failed.
3532 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3533 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
3534 must contain a vendor-specific implementation of this function.
3535 */
SysTick_Config(uint32_t ticks)3536 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3537 {
3538 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3539 {
3540 return (1UL); /* Reload value impossible */
3541 }
3542
3543 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3544 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3545 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3546 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3547 SysTick_CTRL_TICKINT_Msk |
3548 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3549 return (0UL); /* Function successful */
3550 }
3551
3552 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3553 /**
3554 \brief System Tick Configuration (non-secure)
3555 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
3556 Counter is in free running mode to generate periodic interrupts.
3557 \param [in] ticks Number of ticks between two interrupts.
3558 \return 0 Function succeeded.
3559 \return 1 Function failed.
3560 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3561 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3562 must contain a vendor-specific implementation of this function.
3563
3564 */
TZ_SysTick_Config_NS(uint32_t ticks)3565 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3566 {
3567 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3568 {
3569 return (1UL); /* Reload value impossible */
3570 }
3571
3572 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3573 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3574 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3575 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3576 SysTick_CTRL_TICKINT_Msk |
3577 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3578 return (0UL); /* Function successful */
3579 }
3580 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3581
3582 #endif
3583
3584 /*@} end of CMSIS_Core_SysTickFunctions */
3585
3586
3587
3588 /* ##################################### Debug In/Output function ########################################### */
3589 /**
3590 \ingroup CMSIS_Core_FunctionInterface
3591 \defgroup CMSIS_core_DebugFunctions ITM Functions
3592 \brief Functions that access the ITM debug interface.
3593 @{
3594 */
3595
3596 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3597 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3598
3599
3600 /**
3601 \brief ITM Send Character
3602 \details Transmits a character via the ITM channel 0, and
3603 \li Just returns when no debugger is connected that has booked the output.
3604 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3605 \param [in] ch Character to transmit.
3606 \returns Character to transmit.
3607 */
ITM_SendChar(uint32_t ch)3608 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3609 {
3610 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3611 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3612 {
3613 while (ITM->PORT[0U].u32 == 0UL)
3614 {
3615 __NOP();
3616 }
3617 ITM->PORT[0U].u8 = (uint8_t)ch;
3618 }
3619 return (ch);
3620 }
3621
3622
3623 /**
3624 \brief ITM Receive Character
3625 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3626 \return Received character.
3627 \return -1 No character pending.
3628 */
ITM_ReceiveChar(void)3629 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3630 {
3631 int32_t ch = -1; /* no character available */
3632
3633 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3634 {
3635 ch = ITM_RxBuffer;
3636 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3637 }
3638
3639 return (ch);
3640 }
3641
3642
3643 /**
3644 \brief ITM Check Character
3645 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3646 \return 0 No character available.
3647 \return 1 Character available.
3648 */
ITM_CheckChar(void)3649 __STATIC_INLINE int32_t ITM_CheckChar (void)
3650 {
3651
3652 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3653 {
3654 return (0); /* no character available */
3655 }
3656 else
3657 {
3658 return (1); /* character available */
3659 }
3660 }
3661
3662 /*@} end of CMSIS_core_DebugFunctions */
3663
3664
3665
3666
3667 #ifdef __cplusplus
3668 }
3669 #endif
3670
3671 #endif /* __CORE_STAR_H_DEPENDANT */
3672
3673 #endif /* __CMSIS_GENERIC */
3674
