1 /**************************************************************************//**
2 * @file core_starmc1.h
3 * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File
4 * @version V1.0.2
5 * @date 07. April 2022
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 Arm Limited.
9 * Copyright (c) 2018-2022 Arm China.
10 * All rights reserved.
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #if defined ( __ICCARM__ )
27 #pragma system_include /* treat file as system include file for MISRA check */
28 #elif defined (__clang__)
29 #pragma clang system_header /* treat file as system include file */
30 #elif defined ( __GNUC__ )
31 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
32 #endif
33
34 #ifndef __CORE_STAR_H_GENERIC
35 #define __CORE_STAR_H_GENERIC
36
37 #include <stdint.h>
38
39 #ifdef __cplusplus
40 extern "C" {
41 #endif
42
43 /**
44 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
45 CMSIS violates the following MISRA-C:2004 rules:
46
47 \li Required Rule 8.5, object/function definition in header file.<br>
48 Function definitions in header files are used to allow 'inlining'.
49
50 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
51 Unions are used for effective representation of core registers.
52
53 \li Advisory Rule 19.7, Function-like macro defined.<br>
54 Function-like macros are used to allow more efficient code.
55 */
56
57
58 /*******************************************************************************
59 * CMSIS definitions
60 ******************************************************************************/
61 /**
62 \ingroup STAR-MC1
63 @{
64 */
65
66 #include "cmsis_version.h"
67
68 /* Macro Define for STAR-MC1 */
69 #define __STAR_MC (1U) /*!< STAR-MC Core */
70
71 /** __FPU_USED indicates whether an FPU is used or not.
72 For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
73 */
74 #if defined ( __CC_ARM )
75 #if defined (__TARGET_FPU_VFP)
76 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
77 #define __FPU_USED 1U
78 #else
79 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
80 #define __FPU_USED 0U
81 #endif
82 #else
83 #define __FPU_USED 0U
84 #endif
85
86 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
87 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
88 #define __DSP_USED 1U
89 #else
90 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
91 #define __DSP_USED 0U
92 #endif
93 #else
94 #define __DSP_USED 0U
95 #endif
96
97 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
98 #if defined (__ARM_FP)
99 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
100 #define __FPU_USED 1U
101 #else
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #define __FPU_USED 0U
104 #endif
105 #else
106 #define __FPU_USED 0U
107 #endif
108
109 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
110 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
111 #define __DSP_USED 1U
112 #else
113 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
114 #define __DSP_USED 0U
115 #endif
116 #else
117 #define __DSP_USED 0U
118 #endif
119
120 #elif defined ( __GNUC__ )
121 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
122 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
123 #define __FPU_USED 1U
124 #else
125 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
126 #define __FPU_USED 0U
127 #endif
128 #else
129 #define __FPU_USED 0U
130 #endif
131
132 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
133 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
134 #define __DSP_USED 1U
135 #else
136 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
137 #define __DSP_USED 0U
138 #endif
139 #else
140 #define __DSP_USED 0U
141 #endif
142
143 #elif defined ( __ICCARM__ )
144 #if defined (__ARMVFP__)
145 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
146 #define __FPU_USED 1U
147 #else
148 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
149 #define __FPU_USED 0U
150 #endif
151 #else
152 #define __FPU_USED 0U
153 #endif
154
155 #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U)
156 #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U)
157 #define __DSP_USED 1U
158 #else
159 #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)"
160 #define __DSP_USED 0U
161 #endif
162 #else
163 #define __DSP_USED 0U
164 #endif
165
166 #elif defined ( __TI_ARM__ )
167 #if defined (__TI_VFP_SUPPORT__)
168 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
169 #define __FPU_USED 1U
170 #else
171 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
172 #define __FPU_USED 0U
173 #endif
174 #else
175 #define __FPU_USED 0U
176 #endif
177
178 #elif defined ( __TASKING__ )
179 #if defined (__FPU_VFP__)
180 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
181 #define __FPU_USED 1U
182 #else
183 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
184 #define __FPU_USED 0U
185 #endif
186 #else
187 #define __FPU_USED 0U
188 #endif
189
190 #elif defined ( __CSMC__ )
191 #if ( __CSMC__ & 0x400U)
192 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
193 #define __FPU_USED 1U
194 #else
195 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
196 #define __FPU_USED 0U
197 #endif
198 #else
199 #define __FPU_USED 0U
200 #endif
201
202 #endif
203
204 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
205
206
207 #ifdef __cplusplus
208 }
209 #endif
210
211 #endif /* __CORE_STAR_H_GENERIC */
212
213 #ifndef __CMSIS_GENERIC
214
215 #ifndef __CORE_STAR_H_DEPENDANT
216 #define __CORE_STAR_H_DEPENDANT
217
218 #ifdef __cplusplus
219 extern "C" {
220 #endif
221
222 /* check device defines and use defaults */
223 #if defined __CHECK_DEVICE_DEFINES
224 #ifndef __STAR_REV
225 #define __STAR_REV 0x0000U
226 #warning "__STAR_REV not defined in device header file; using default!"
227 #endif
228
229 #ifndef __FPU_PRESENT
230 #define __FPU_PRESENT 0U
231 #warning "__FPU_PRESENT not defined in device header file; using default!"
232 #endif
233
234 #ifndef __MPU_PRESENT
235 #define __MPU_PRESENT 0U
236 #warning "__MPU_PRESENT not defined in device header file; using default!"
237 #endif
238
239 #ifndef __SAUREGION_PRESENT
240 #define __SAUREGION_PRESENT 0U
241 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
242 #endif
243
244 #ifndef __DSP_PRESENT
245 #define __DSP_PRESENT 0U
246 #warning "__DSP_PRESENT not defined in device header file; using default!"
247 #endif
248
249 #ifndef __ICACHE_PRESENT
250 #define __ICACHE_PRESENT 0U
251 #warning "__ICACHE_PRESENT not defined in device header file; using default!"
252 #endif
253
254 #ifndef __DCACHE_PRESENT
255 #define __DCACHE_PRESENT 0U
256 #warning "__DCACHE_PRESENT not defined in device header file; using default!"
257 #endif
258
259 #ifndef __DTCM_PRESENT
260 #define __DTCM_PRESENT 0U
261 #warning "__DTCM_PRESENT not defined in device header file; using default!"
262 #endif
263
264 #ifndef __NVIC_PRIO_BITS
265 #define __NVIC_PRIO_BITS 3U
266 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
267 #endif
268
269 #ifndef __Vendor_SysTickConfig
270 #define __Vendor_SysTickConfig 0U
271 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
272 #endif
273 #endif
274
275 /* IO definitions (access restrictions to peripheral registers) */
276 /**
277 \defgroup CMSIS_glob_defs CMSIS Global Defines
278
279 <strong>IO Type Qualifiers</strong> are used
280 \li to specify the access to peripheral variables.
281 \li for automatic generation of peripheral register debug information.
282 */
283 #ifdef __cplusplus
284 #define __I volatile /*!< Defines 'read only' permissions */
285 #else
286 #define __I volatile const /*!< Defines 'read only' permissions */
287 #endif
288 #define __O volatile /*!< Defines 'write only' permissions */
289 #define __IO volatile /*!< Defines 'read / write' permissions */
290
291 /* following defines should be used for structure members */
292 #define __IM volatile const /*! Defines 'read only' structure member permissions */
293 #define __OM volatile /*! Defines 'write only' structure member permissions */
294 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
295
296 /*@} end of group STAR-MC1 */
297
298
299
300 /*******************************************************************************
301 * Register Abstraction
302 Core Register contain:
303 - Core Register
304 - Core NVIC Register
305 - Core SCB Register
306 - Core SysTick Register
307 - Core Debug Register
308 - Core MPU Register
309 - Core SAU Register
310 - Core FPU Register
311 ******************************************************************************/
312 /**
313 \defgroup CMSIS_core_register Defines and Type Definitions
314 \brief Type definitions and defines for STAR-MC1 processor based devices.
315 */
316
317 /**
318 \ingroup CMSIS_core_register
319 \defgroup CMSIS_CORE Status and Control Registers
320 \brief Core Register type definitions.
321 @{
322 */
323
324 /**
325 \brief Union type to access the Application Program Status Register (APSR).
326 */
327 typedef union
328 {
329 struct
330 {
331 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
332 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
333 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
334 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
335 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
336 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
337 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
338 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
339 } b; /*!< Structure used for bit access */
340 uint32_t w; /*!< Type used for word access */
341 } APSR_Type;
342
343 /* APSR Register Definitions */
344 #define APSR_N_Pos 31U /*!< APSR: N Position */
345 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
346
347 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
348 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
349
350 #define APSR_C_Pos 29U /*!< APSR: C Position */
351 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
352
353 #define APSR_V_Pos 28U /*!< APSR: V Position */
354 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
355
356 #define APSR_Q_Pos 27U /*!< APSR: Q Position */
357 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
358
359 #define APSR_GE_Pos 16U /*!< APSR: GE Position */
360 #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */
361
362
363 /**
364 \brief Union type to access the Interrupt Program Status Register (IPSR).
365 */
366 typedef union
367 {
368 struct
369 {
370 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
371 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
372 } b; /*!< Structure used for bit access */
373 uint32_t w; /*!< Type used for word access */
374 } IPSR_Type;
375
376 /* IPSR Register Definitions */
377 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
378 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
379
380
381 /**
382 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
383 */
384 typedef union
385 {
386 struct
387 {
388 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
389 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
390 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
391 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
392 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
393 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
394 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
395 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
396 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
397 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
398 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
399 } b; /*!< Structure used for bit access */
400 uint32_t w; /*!< Type used for word access */
401 } xPSR_Type;
402
403 /* xPSR Register Definitions */
404 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
405 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
406
407 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
408 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
409
410 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
411 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
412
413 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
414 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
415
416 #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */
417 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
418
419 #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */
420 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
421
422 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
423 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
424
425 #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */
426 #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */
427
428 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
429 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
430
431
432 /**
433 \brief Union type to access the Control Registers (CONTROL).
434 */
435 typedef union
436 {
437 struct
438 {
439 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
440 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
441 uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */
442 uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */
443 uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */
444 } b; /*!< Structure used for bit access */
445 uint32_t w; /*!< Type used for word access */
446 } CONTROL_Type;
447
448 /* CONTROL Register Definitions */
449 #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */
450 #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */
451
452 #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */
453 #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */
454
455 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
456 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
457
458 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
459 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
460
461 /*@} end of group CMSIS_CORE */
462
463
464 /**
465 \ingroup CMSIS_core_register
466 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
467 \brief Type definitions for the NVIC Registers
468 @{
469 */
470
471 /**
472 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
473 */
474 typedef struct
475 {
476 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
477 uint32_t RESERVED0[16U];
478 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
479 uint32_t RSERVED1[16U];
480 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
481 uint32_t RESERVED2[16U];
482 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
483 uint32_t RESERVED3[16U];
484 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
485 uint32_t RESERVED4[16U];
486 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
487 uint32_t RESERVED5[16U];
488 __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
489 uint32_t RESERVED6[580U];
490 __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
491 } NVIC_Type;
492
493 /* Software Triggered Interrupt Register Definitions */
494 #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */
495 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
496
497 /*@} end of group CMSIS_NVIC */
498
499
500 /**
501 \ingroup CMSIS_core_register
502 \defgroup CMSIS_SCB System Control Block (SCB)
503 \brief Type definitions for the System Control Block Registers
504 @{
505 */
506
507 /**
508 \brief Structure type to access the System Control Block (SCB).
509 */
510 typedef struct
511 {
512 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
513 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
514 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
515 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
516 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
517 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
518 __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
519 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
520 __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
521 __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
522 __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
523 __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
524 __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
525 __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
526 __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
527 __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
528 __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
529 __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
530 __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
531 uint32_t RESERVED0[1U];
532 __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
533 __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */
534 __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */
535 __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
536 __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
537 __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */
538 uint32_t RESERVED_ADD1[21U];
539 __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */
540 __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */
541 uint32_t RESERVED3[69U];
542 __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */
543 uint32_t RESERVED4[15U];
544 __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */
545 __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */
546 __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */
547 uint32_t RESERVED5[1U];
548 __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */
549 uint32_t RESERVED6[1U];
550 __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */
551 __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */
552 __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */
553 __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */
554 __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */
555 __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */
556 __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */
557 __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */
558 } SCB_Type;
559
560 typedef struct
561 {
562 __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */
563 __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */
564 __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */
565 }EMSS_Type;
566
567 /* SCB CPUID Register Definitions */
568 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
569 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
570
571 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
572 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
573
574 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
575 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
576
577 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
578 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
579
580 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
581 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
582
583 /* SCB Interrupt Control State Register Definitions */
584 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
585 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
586
587 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
588 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
589
590 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
591 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
592
593 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
594 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
595
596 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
597 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
598
599 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
600 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
601
602 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
603 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
604
605 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
606 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
607
608 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
609 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
610
611 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
612 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
613
614 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
615 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
616
617 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
618 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
619
620 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
621 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
622
623 /* SCB Vector Table Offset Register Definitions */
624 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
625 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
626
627 /* SCB Application Interrupt and Reset Control Register Definitions */
628 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
629 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
630
631 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
632 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
633
634 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
635 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
636
637 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
638 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
639
640 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
641 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
642
643 #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */
644 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
645
646 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
647 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
648
649 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
650 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
651
652 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
653 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
654
655 /* SCB System Control Register Definitions */
656 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
657 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
658
659 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
660 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
661
662 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
663 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
664
665 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
666 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
667
668 /* SCB Configuration Control Register Definitions */
669 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
670 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
671
672 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
673 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
674
675 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
676 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
677
678 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
679 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
680
681 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
682 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
683
684 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
685 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
686
687 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
688 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
689
690 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
691 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
692
693 /* SCB System Handler Control and State Register Definitions */
694 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
695 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
696
697 #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */
698 #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */
699
700 #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */
701 #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */
702
703 #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */
704 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
705
706 #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */
707 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
708
709 #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */
710 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
711
712 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
713 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
714
715 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */
716 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
717
718 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */
719 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
720
721 #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */
722 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
723
724 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
725 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
726
727 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
728 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
729
730 #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */
731 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
732
733 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
734 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
735
736 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
737 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
738
739 #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */
740 #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */
741
742 #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */
743 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
744
745 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
746 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
747
748 #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */
749 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
750
751 #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */
752 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
753
754 /* SCB Configurable Fault Status Register Definitions */
755 #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */
756 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
757
758 #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */
759 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
760
761 #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */
762 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
763
764 /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */
765 #define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */
766 #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */
767
768 #define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */
769 #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */
770
771 #define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */
772 #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */
773
774 #define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */
775 #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */
776
777 #define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */
778 #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */
779
780 #define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */
781 #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */
782
783 /* BusFault Status Register (part of SCB Configurable Fault Status Register) */
784 #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */
785 #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */
786
787 #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */
788 #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */
789
790 #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */
791 #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */
792
793 #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */
794 #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */
795
796 #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */
797 #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */
798
799 #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */
800 #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */
801
802 #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */
803 #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */
804
805 /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */
806 #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */
807 #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */
808
809 #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */
810 #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */
811
812 #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */
813 #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */
814
815 #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */
816 #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */
817
818 #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */
819 #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */
820
821 #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */
822 #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */
823
824 #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */
825 #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */
826
827 /* SCB Hard Fault Status Register Definitions */
828 #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */
829 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
830
831 #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */
832 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
833
834 #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */
835 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
836
837 /* SCB Debug Fault Status Register Definitions */
838 #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */
839 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
840
841 #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */
842 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
843
844 #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */
845 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
846
847 #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */
848 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
849
850 #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */
851 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
852
853 /* SCB Non-Secure Access Control Register Definitions */
854 #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */
855 #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */
856
857 #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */
858 #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */
859
860 #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */
861 #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */
862
863 /* SCB Cache Level ID Register Definitions */
864 #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */
865 #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */
866
867 #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */
868 #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */
869
870 #define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */
871 #define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */
872
873 #define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */
874 #define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */
875
876
877
878 /* SCB Cache Type Register Definitions */
879 #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */
880 #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */
881
882 #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */
883 #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */
884
885 #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */
886 #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */
887
888 #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */
889 #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */
890
891 #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */
892 #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */
893
894 /* SCB Cache Size ID Register Definitions */
895 #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */
896 #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */
897
898 #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */
899 #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */
900
901 #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */
902 #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */
903
904 #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */
905 #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */
906
907 #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */
908 #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */
909
910 #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */
911 #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */
912
913 #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */
914 #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */
915
916 /* SCB Cache Size Selection Register Definitions */
917 #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */
918 #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */
919
920 #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */
921 #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */
922
923 /* SCB Software Triggered Interrupt Register Definitions */
924 #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */
925 #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */
926
927 /* SCB D-Cache line Invalidate by Set-way Register Definitions */
928 #define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */
929 #define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */
930
931 #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */
932 #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */
933
934 #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */
935 #define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */
936
937 /* SCB D-Cache Clean line by Set-way Register Definitions */
938 #define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */
939 #define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */
940
941 #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */
942 #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */
943
944 #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */
945 #define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */
946
947 /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */
948 #define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */
949 #define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */
950
951 #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */
952 #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */
953
954 #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */
955 #define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */
956
957 /* ArmChina: Implementation Defined */
958 /* Instruction Tightly-Coupled Memory Control Register Definitions */
959 #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */
960 #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */
961
962 #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */
963 #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */
964
965 /* Data Tightly-Coupled Memory Control Register Definitions */
966 #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */
967 #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */
968
969 #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */
970 #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */
971
972 /* L1 Cache Control Register Definitions */
973 #define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */
974 #define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */
975
976 #define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */
977 #define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */
978
979 #define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */
980 #define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */
981
982 #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */
983 #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */
984
985 /*@} end of group CMSIS_SCB */
986
987
988 /**
989 \ingroup CMSIS_core_register
990 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
991 \brief Type definitions for the System Control and ID Register not in the SCB
992 @{
993 */
994
995 /**
996 \brief Structure type to access the System Control and ID Register not in the SCB.
997 */
998 typedef struct
999 {
1000 uint32_t RESERVED0[1U];
1001 __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
1002 __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
1003 __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
1004 } SCnSCB_Type;
1005
1006 /* Interrupt Controller Type Register Definitions */
1007 #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */
1008 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
1009
1010 /*@} end of group CMSIS_SCnotSCB */
1011
1012
1013 /**
1014 \ingroup CMSIS_core_register
1015 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
1016 \brief Type definitions for the System Timer Registers.
1017 @{
1018 */
1019
1020 /**
1021 \brief Structure type to access the System Timer (SysTick).
1022 */
1023 typedef struct
1024 {
1025 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
1026 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
1027 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
1028 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
1029 } SysTick_Type;
1030
1031 /* SysTick Control / Status Register Definitions */
1032 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
1033 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
1034
1035 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
1036 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
1037
1038 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
1039 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
1040
1041 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
1042 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
1043
1044 /* SysTick Reload Register Definitions */
1045 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
1046 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
1047
1048 /* SysTick Current Register Definitions */
1049 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
1050 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
1051
1052 /* SysTick Calibration Register Definitions */
1053 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
1054 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
1055
1056 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
1057 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
1058
1059 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
1060 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
1061
1062 /*@} end of group CMSIS_SysTick */
1063
1064
1065 /**
1066 \ingroup CMSIS_core_register
1067 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
1068 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
1069 @{
1070 */
1071
1072 /**
1073 \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
1074 */
1075 typedef struct
1076 {
1077 __OM union
1078 {
1079 __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
1080 __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
1081 __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
1082 } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
1083 uint32_t RESERVED0[864U];
1084 __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
1085 uint32_t RESERVED1[15U];
1086 __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
1087 uint32_t RESERVED2[15U];
1088 __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
1089 uint32_t RESERVED3[32U];
1090 uint32_t RESERVED4[43U];
1091 __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
1092 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
1093 uint32_t RESERVED5[1U];
1094 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */
1095 uint32_t RESERVED6[4U];
1096 __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
1097 __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
1098 __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
1099 __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
1100 __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
1101 __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
1102 __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
1103 __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
1104 __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
1105 __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
1106 __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
1107 __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
1108 } ITM_Type;
1109
1110 /* ITM Stimulus Port Register Definitions */
1111 #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */
1112 #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */
1113
1114 #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */
1115 #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */
1116
1117 /* ITM Trace Privilege Register Definitions */
1118 #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */
1119 #define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
1120
1121 /* ITM Trace Control Register Definitions */
1122 #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */
1123 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
1124
1125 #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */
1126 #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */
1127
1128 #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */
1129 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
1130
1131 #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */
1132 #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */
1133
1134 #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */
1135 #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */
1136
1137 #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */
1138 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
1139
1140 #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */
1141 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
1142
1143 #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */
1144 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
1145
1146 #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */
1147 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
1148
1149 #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */
1150 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
1151
1152 /* ITM Lock Status Register Definitions */
1153 #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */
1154 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
1155
1156 #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */
1157 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
1158
1159 #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */
1160 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
1161
1162 /*@}*/ /* end of group CMSIS_ITM */
1163
1164
1165 /**
1166 \ingroup CMSIS_core_register
1167 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
1168 \brief Type definitions for the Data Watchpoint and Trace (DWT)
1169 @{
1170 */
1171
1172 /**
1173 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
1174 */
1175 typedef struct
1176 {
1177 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
1178 __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
1179 __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
1180 __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
1181 __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
1182 __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
1183 __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
1184 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
1185 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
1186 uint32_t RESERVED1[1U];
1187 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
1188 uint32_t RESERVED2[1U];
1189 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
1190 uint32_t RESERVED3[1U];
1191 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
1192 uint32_t RESERVED4[1U];
1193 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
1194 uint32_t RESERVED5[1U];
1195 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
1196 uint32_t RESERVED6[1U];
1197 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
1198 uint32_t RESERVED7[1U];
1199 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
1200 uint32_t RESERVED8[1U];
1201 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
1202 uint32_t RESERVED9[1U];
1203 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
1204 uint32_t RESERVED10[1U];
1205 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
1206 uint32_t RESERVED11[1U];
1207 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
1208 uint32_t RESERVED12[1U];
1209 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
1210 uint32_t RESERVED13[1U];
1211 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
1212 uint32_t RESERVED14[1U];
1213 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
1214 uint32_t RESERVED15[1U];
1215 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
1216 uint32_t RESERVED16[1U];
1217 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
1218 uint32_t RESERVED17[1U];
1219 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
1220 uint32_t RESERVED18[1U];
1221 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
1222 uint32_t RESERVED19[1U];
1223 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
1224 uint32_t RESERVED20[1U];
1225 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
1226 uint32_t RESERVED21[1U];
1227 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
1228 uint32_t RESERVED22[1U];
1229 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
1230 uint32_t RESERVED23[1U];
1231 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
1232 uint32_t RESERVED24[1U];
1233 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
1234 uint32_t RESERVED25[1U];
1235 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
1236 uint32_t RESERVED26[1U];
1237 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
1238 uint32_t RESERVED27[1U];
1239 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
1240 uint32_t RESERVED28[1U];
1241 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
1242 uint32_t RESERVED29[1U];
1243 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
1244 uint32_t RESERVED30[1U];
1245 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
1246 uint32_t RESERVED31[1U];
1247 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
1248 uint32_t RESERVED32[934U];
1249 __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */
1250 uint32_t RESERVED33[1U];
1251 __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */
1252 } DWT_Type;
1253
1254 /* DWT Control Register Definitions */
1255 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
1256 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
1257
1258 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
1259 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
1260
1261 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
1262 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
1263
1264 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
1265 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
1266
1267 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
1268 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
1269
1270 #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */
1271 #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */
1272
1273 #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */
1274 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
1275
1276 #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */
1277 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
1278
1279 #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */
1280 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
1281
1282 #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */
1283 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
1284
1285 #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */
1286 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
1287
1288 #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */
1289 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
1290
1291 #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */
1292 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
1293
1294 #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */
1295 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
1296
1297 #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */
1298 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
1299
1300 #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */
1301 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
1302
1303 #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */
1304 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
1305
1306 #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */
1307 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
1308
1309 #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */
1310 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
1311
1312 /* DWT CPI Count Register Definitions */
1313 #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */
1314 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
1315
1316 /* DWT Exception Overhead Count Register Definitions */
1317 #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */
1318 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
1319
1320 /* DWT Sleep Count Register Definitions */
1321 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */
1322 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
1323
1324 /* DWT LSU Count Register Definitions */
1325 #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */
1326 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
1327
1328 /* DWT Folded-instruction Count Register Definitions */
1329 #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */
1330 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
1331
1332 /* DWT Comparator Function Register Definitions */
1333 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
1334 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
1335
1336 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
1337 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
1338
1339 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
1340 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
1341
1342 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
1343 #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
1344
1345 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
1346 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
1347
1348 /*@}*/ /* end of group CMSIS_DWT */
1349
1350
1351 /**
1352 \ingroup CMSIS_core_register
1353 \defgroup CMSIS_TPI Trace Port Interface (TPI)
1354 \brief Type definitions for the Trace Port Interface (TPI)
1355 @{
1356 */
1357
1358 /**
1359 \brief Structure type to access the Trace Port Interface Register (TPI).
1360 */
1361 typedef struct
1362 {
1363 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
1364 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
1365 uint32_t RESERVED0[2U];
1366 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
1367 uint32_t RESERVED1[55U];
1368 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
1369 uint32_t RESERVED2[131U];
1370 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
1371 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
1372 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
1373 uint32_t RESERVED3[759U];
1374 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
1375 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
1376 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
1377 uint32_t RESERVED4[1U];
1378 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
1379 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
1380 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
1381 uint32_t RESERVED5[39U];
1382 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
1383 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
1384 uint32_t RESERVED7[8U];
1385 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
1386 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
1387 } TPI_Type;
1388
1389 /* TPI Asynchronous Clock Prescaler Register Definitions */
1390 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
1391 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
1392
1393 /* TPI Selected Pin Protocol Register Definitions */
1394 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
1395 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
1396
1397 /* TPI Formatter and Flush Status Register Definitions */
1398 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
1399 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
1400
1401 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
1402 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
1403
1404 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
1405 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
1406
1407 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
1408 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
1409
1410 /* TPI Formatter and Flush Control Register Definitions */
1411 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
1412 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
1413
1414 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
1415 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
1416
1417 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
1418 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
1419
1420 /* TPI TRIGGER Register Definitions */
1421 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
1422 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
1423
1424 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
1425 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
1426 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
1427
1428 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
1429 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
1430
1431 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
1432 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
1433
1434 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
1435 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
1436
1437 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
1438 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
1439
1440 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
1441 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
1442
1443 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
1444 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
1445
1446 /* TPI Integration Test ATB Control Register 2 Register Definitions */
1447 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
1448 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
1449
1450 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
1451 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
1452
1453 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
1454 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
1455
1456 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
1457 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
1458
1459 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
1460 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
1461 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
1462
1463 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
1464 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
1465
1466 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
1467 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
1468
1469 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
1470 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
1471
1472 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
1473 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
1474
1475 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
1476 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
1477
1478 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
1479 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
1480
1481 /* TPI Integration Test ATB Control Register 0 Definitions */
1482 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
1483 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
1484
1485 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
1486 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
1487
1488 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
1489 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
1490
1491 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
1492 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
1493
1494 /* TPI Integration Mode Control Register Definitions */
1495 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
1496 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
1497
1498 /* TPI DEVID Register Definitions */
1499 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
1500 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
1501
1502 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
1503 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
1504
1505 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
1506 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
1507
1508 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
1509 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
1510
1511 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
1512 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
1513
1514 /* TPI DEVTYPE Register Definitions */
1515 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
1516 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
1517
1518 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
1519 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
1520
1521 /*@}*/ /* end of group CMSIS_TPI */
1522
1523
1524 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1525 /**
1526 \ingroup CMSIS_core_register
1527 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
1528 \brief Type definitions for the Memory Protection Unit (MPU)
1529 @{
1530 */
1531
1532 /**
1533 \brief Structure type to access the Memory Protection Unit (MPU).
1534 */
1535 typedef struct
1536 {
1537 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
1538 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
1539 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
1540 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
1541 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
1542 __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */
1543 __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */
1544 __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */
1545 __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */
1546 __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */
1547 __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */
1548 uint32_t RESERVED0[1];
1549 union {
1550 __IOM uint32_t MAIR[2];
1551 struct {
1552 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
1553 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
1554 };
1555 };
1556 } MPU_Type;
1557
1558 #define MPU_TYPE_RALIASES 4U
1559
1560 /* MPU Type Register Definitions */
1561 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
1562 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
1563
1564 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
1565 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
1566
1567 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
1568 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
1569
1570 /* MPU Control Register Definitions */
1571 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
1572 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
1573
1574 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
1575 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
1576
1577 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
1578 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
1579
1580 /* MPU Region Number Register Definitions */
1581 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
1582 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
1583
1584 /* MPU Region Base Address Register Definitions */
1585 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
1586 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
1587
1588 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
1589 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
1590
1591 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
1592 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
1593
1594 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
1595 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
1596
1597 /* MPU Region Limit Address Register Definitions */
1598 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
1599 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
1600
1601 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
1602 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
1603
1604 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */
1605 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */
1606
1607 /* MPU Memory Attribute Indirection Register 0 Definitions */
1608 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
1609 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
1610
1611 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
1612 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
1613
1614 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
1615 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
1616
1617 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
1618 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
1619
1620 /* MPU Memory Attribute Indirection Register 1 Definitions */
1621 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
1622 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
1623
1624 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
1625 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
1626
1627 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
1628 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
1629
1630 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
1631 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
1632
1633 /*@} end of group CMSIS_MPU */
1634 #endif
1635
1636
1637 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1638 /**
1639 \ingroup CMSIS_core_register
1640 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1641 \brief Type definitions for the Security Attribution Unit (SAU)
1642 @{
1643 */
1644
1645 /**
1646 \brief Structure type to access the Security Attribution Unit (SAU).
1647 */
1648 typedef struct
1649 {
1650 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1651 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1652 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1653 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1654 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1655 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1656 #else
1657 uint32_t RESERVED0[3];
1658 #endif
1659 __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */
1660 __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */
1661 } SAU_Type;
1662
1663 /* SAU Control Register Definitions */
1664 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1665 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1666
1667 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1668 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1669
1670 /* SAU Type Register Definitions */
1671 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1672 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1673
1674 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1675 /* SAU Region Number Register Definitions */
1676 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1677 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1678
1679 /* SAU Region Base Address Register Definitions */
1680 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1681 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1682
1683 /* SAU Region Limit Address Register Definitions */
1684 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1685 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1686
1687 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1688 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1689
1690 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1691 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1692
1693 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1694
1695 /* Secure Fault Status Register Definitions */
1696 #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */
1697 #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */
1698
1699 #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */
1700 #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */
1701
1702 #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */
1703 #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */
1704
1705 #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */
1706 #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */
1707
1708 #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */
1709 #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */
1710
1711 #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */
1712 #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */
1713
1714 #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */
1715 #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */
1716
1717 #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */
1718 #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */
1719
1720 /*@} end of group CMSIS_SAU */
1721 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1722
1723
1724 /**
1725 \ingroup CMSIS_core_register
1726 \defgroup CMSIS_FPU Floating Point Unit (FPU)
1727 \brief Type definitions for the Floating Point Unit (FPU)
1728 @{
1729 */
1730
1731 /**
1732 \brief Structure type to access the Floating Point Unit (FPU).
1733 */
1734 typedef struct
1735 {
1736 uint32_t RESERVED0[1U];
1737 __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
1738 __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
1739 __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
1740 __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */
1741 __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */
1742 __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */
1743 } FPU_Type;
1744
1745 /* Floating-Point Context Control Register Definitions */
1746 #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */
1747 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
1748
1749 #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */
1750 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
1751
1752 #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */
1753 #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */
1754
1755 #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */
1756 #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */
1757
1758 #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */
1759 #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */
1760
1761 #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */
1762 #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */
1763
1764 #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */
1765 #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */
1766
1767 #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */
1768 #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */
1769
1770 #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */
1771 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
1772
1773 #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */
1774 #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */
1775
1776 #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */
1777 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
1778
1779 #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */
1780 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
1781
1782 #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */
1783 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
1784
1785 #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */
1786 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
1787
1788 #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */
1789 #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */
1790
1791 #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */
1792 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
1793
1794 #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */
1795 #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */
1796
1797 /* Floating-Point Context Address Register Definitions */
1798 #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */
1799 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
1800
1801 /* Floating-Point Default Status Control Register Definitions */
1802 #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */
1803 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
1804
1805 #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */
1806 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
1807
1808 #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */
1809 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
1810
1811 #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */
1812 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
1813
1814 /* Media and VFP Feature Register 0 Definitions */
1815 #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */
1816 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
1817
1818 #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */
1819 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
1820
1821 #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */
1822 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
1823
1824 #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */
1825 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
1826
1827 #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */
1828 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
1829
1830 #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */
1831 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
1832
1833 #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */
1834 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
1835
1836 #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */
1837 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */
1838
1839 /* Media and VFP Feature Register 1 Definitions */
1840 #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */
1841 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
1842
1843 #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */
1844 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
1845
1846 #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */
1847 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
1848
1849 #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */
1850 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */
1851
1852 /* Media and VFP Feature Register 2 Definitions */
1853 #define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */
1854 #define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */
1855
1856 /*@} end of group CMSIS_FPU */
1857
1858
1859
1860
1861
1862 /**
1863 \ingroup CMSIS_core_register
1864 \defgroup CMSIS_DCB Debug Control Block
1865 \brief Type definitions for the Debug Control Block Registers
1866 @{
1867 */
1868
1869 /**
1870 \brief Structure type to access the Debug Control Block Registers (DCB).
1871 */
1872 typedef struct
1873 {
1874 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1875 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1876 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1877 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1878 uint32_t RESERVED0[1U];
1879 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1880 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1881 } DCB_Type;
1882
1883 /* DHCSR, Debug Halting Control and Status Register Definitions */
1884 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1885 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1886
1887 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1888 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1889
1890 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1891 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1892
1893 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1894 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1895
1896 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1897 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1898
1899 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1900 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1901
1902 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1903 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1904
1905 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1906 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1907
1908 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1909 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1910
1911 #define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */
1912 #define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */
1913
1914 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1915 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1916
1917 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1918 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1919
1920 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1921 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1922
1923 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1924 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1925
1926 /* DCRSR, Debug Core Register Select Register Definitions */
1927 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1928 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1929
1930 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1931 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1932
1933 /* DCRDR, Debug Core Register Data Register Definitions */
1934 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1935 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1936
1937 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1938 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1939 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1940
1941 #define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */
1942 #define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */
1943
1944 #define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */
1945 #define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */
1946
1947 #define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */
1948 #define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */
1949
1950 #define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */
1951 #define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */
1952
1953 #define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */
1954 #define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */
1955
1956 #define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */
1957 #define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */
1958
1959 #define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */
1960 #define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */
1961
1962 #define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */
1963 #define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */
1964
1965 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1966 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1967
1968 #define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */
1969 #define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */
1970
1971 #define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */
1972 #define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */
1973
1974 #define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */
1975 #define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */
1976
1977 #define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */
1978 #define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */
1979
1980 #define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */
1981 #define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */
1982
1983 #define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */
1984 #define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */
1985
1986 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1987 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1988
1989 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1990 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1991 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
1992
1993 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
1994 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
1995
1996 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
1997 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
1998
1999 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
2000 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
2001
2002 /* DSCSR, Debug Security Control and Status Register Definitions */
2003 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
2004 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
2005
2006 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
2007 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
2008
2009 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
2010 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
2011
2012 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
2013 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
2014
2015 /*@} end of group CMSIS_DCB */
2016
2017
2018
2019 /**
2020 \ingroup CMSIS_core_register
2021 \defgroup CMSIS_DIB Debug Identification Block
2022 \brief Type definitions for the Debug Identification Block Registers
2023 @{
2024 */
2025
2026 /**
2027 \brief Structure type to access the Debug Identification Block Registers (DIB).
2028 */
2029 typedef struct
2030 {
2031 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
2032 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
2033 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
2034 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
2035 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
2036 } DIB_Type;
2037
2038 /* DLAR, SCS Software Lock Access Register Definitions */
2039 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
2040 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
2041
2042 /* DLSR, SCS Software Lock Status Register Definitions */
2043 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
2044 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
2045
2046 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
2047 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
2048
2049 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
2050 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
2051
2052 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
2053 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
2054 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
2055
2056 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
2057 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
2058
2059 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
2060 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
2061
2062 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
2063 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
2064
2065 /* DDEVARCH, SCS Device Architecture Register Definitions */
2066 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
2067 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
2068
2069 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
2070 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
2071
2072 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
2073 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
2074
2075 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
2076 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
2077
2078 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
2079 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
2080
2081 /* DDEVTYPE, SCS Device Type Register Definitions */
2082 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
2083 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
2084
2085 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
2086 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
2087
2088
2089 /*@} end of group CMSIS_DIB */
2090
2091
2092 /**
2093 \ingroup CMSIS_core_register
2094 \defgroup CMSIS_core_bitfield Core register bit field macros
2095 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
2096 @{
2097 */
2098
2099 /**
2100 \brief Mask and shift a bit field value for use in a register bit range.
2101 \param[in] field Name of the register bit field.
2102 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
2103 \return Masked and shifted value.
2104 */
2105 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
2106
2107 /**
2108 \brief Mask and shift a register value to extract a bit filed value.
2109 \param[in] field Name of the register bit field.
2110 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
2111 \return Masked and shifted bit field value.
2112 */
2113 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
2114
2115 /*@} end of group CMSIS_core_bitfield */
2116
2117
2118 /**
2119 \ingroup CMSIS_core_register
2120 \defgroup CMSIS_core_base Core Definitions
2121 \brief Definitions for base addresses, unions, and structures.
2122 @{
2123 */
2124
2125 /* Memory mapping of Core Hardware */
2126 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
2127 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
2128 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
2129 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
2130 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
2131 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
2132 #define EMSS_BASE (0xE001E000UL) /*!<Enhanced Memory SubSystem Base Address */
2133
2134 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
2135 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
2136 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
2137
2138 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
2139 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
2140 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
2141 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
2142 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
2143 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
2144 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
2145 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
2146 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
2147 #define EMSS ((EMSS_Type *) EMSS_BASE ) /*!<Ehanced MSS Registers struct */
2148
2149 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2150 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
2151 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
2152 #endif
2153
2154 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2155 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
2156 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
2157 #endif
2158
2159 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
2160 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
2161
2162 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2163 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
2164
2165 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
2166 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
2167 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
2168 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
2169 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
2170
2171 #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */
2172 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
2173 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
2174 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
2175 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
2176 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
2177
2178 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2179 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
2180 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
2181 #endif
2182
2183 #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */
2184 #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */
2185
2186 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2187 /*@} */
2188
2189
2190
2191 /*******************************************************************************
2192 * Hardware Abstraction Layer
2193 Core Function Interface contains:
2194 - Core NVIC Functions
2195 - Core SysTick Functions
2196 - Core Debug Functions
2197 - Core Register Access Functions
2198 ******************************************************************************/
2199 /**
2200 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
2201 */
2202
2203
2204
2205 /* ########################## NVIC functions #################################### */
2206 /**
2207 \ingroup CMSIS_Core_FunctionInterface
2208 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
2209 \brief Functions that manage interrupts and exceptions via the NVIC.
2210 @{
2211 */
2212
2213 #ifdef CMSIS_NVIC_VIRTUAL
2214 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
2215 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
2216 #endif
2217 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
2218 #else
2219 #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
2220 #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
2221 #define NVIC_EnableIRQ __NVIC_EnableIRQ
2222 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
2223 #define NVIC_DisableIRQ __NVIC_DisableIRQ
2224 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
2225 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
2226 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
2227 #define NVIC_GetActive __NVIC_GetActive
2228 #define NVIC_SetPriority __NVIC_SetPriority
2229 #define NVIC_GetPriority __NVIC_GetPriority
2230 #define NVIC_SystemReset __NVIC_SystemReset
2231 #define SW_SystemReset __SW_SystemReset
2232 #endif /* CMSIS_NVIC_VIRTUAL */
2233
2234 #ifdef CMSIS_VECTAB_VIRTUAL
2235 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2236 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
2237 #endif
2238 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
2239 #else
2240 #define NVIC_SetVector __NVIC_SetVector
2241 #define NVIC_GetVector __NVIC_GetVector
2242 #endif /* (CMSIS_VECTAB_VIRTUAL) */
2243
2244 #define NVIC_USER_IRQ_OFFSET 16
2245
2246
2247 /* Special LR values for Secure/Non-Secure call handling and exception handling */
2248
2249 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
2250 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
2251
2252 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
2253 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
2254 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
2255 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
2256 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
2257 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
2258 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
2259 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
2260
2261 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
2262 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
2263 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
2264 #else
2265 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
2266 #endif
2267
2268
2269 /**
2270 \brief Set Priority Grouping
2271 \details Sets the priority grouping field using the required unlock sequence.
2272 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2273 Only values from 0..7 are used.
2274 In case of a conflict between priority grouping and available
2275 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2276 \param [in] PriorityGroup Priority grouping field.
2277 */
__NVIC_SetPriorityGrouping(uint32_t PriorityGroup)2278 __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
2279 {
2280 uint32_t reg_value;
2281 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2282
2283 reg_value = SCB->AIRCR; /* read old register configuration */
2284 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2285 reg_value = (reg_value |
2286 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2287 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2288 SCB->AIRCR = reg_value;
2289 }
2290
2291
2292 /**
2293 \brief Get Priority Grouping
2294 \details Reads the priority grouping field from the NVIC Interrupt Controller.
2295 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2296 */
__NVIC_GetPriorityGrouping(void)2297 __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
2298 {
2299 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2300 }
2301
2302
2303 /**
2304 \brief Enable Interrupt
2305 \details Enables a device specific interrupt in the NVIC interrupt controller.
2306 \param [in] IRQn Device specific interrupt number.
2307 \note IRQn must not be negative.
2308 */
__NVIC_EnableIRQ(IRQn_Type IRQn)2309 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
2310 {
2311 if ((int32_t)(IRQn) >= 0)
2312 {
2313 __COMPILER_BARRIER();
2314 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2315 __COMPILER_BARRIER();
2316 }
2317 }
2318
2319
2320 /**
2321 \brief Get Interrupt Enable status
2322 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
2323 \param [in] IRQn Device specific interrupt number.
2324 \return 0 Interrupt is not enabled.
2325 \return 1 Interrupt is enabled.
2326 \note IRQn must not be negative.
2327 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)2328 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
2329 {
2330 if ((int32_t)(IRQn) >= 0)
2331 {
2332 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2333 }
2334 else
2335 {
2336 return(0U);
2337 }
2338 }
2339
2340
2341 /**
2342 \brief Disable Interrupt
2343 \details Disables a device specific interrupt in the NVIC interrupt controller.
2344 \param [in] IRQn Device specific interrupt number.
2345 \note IRQn must not be negative.
2346 */
__NVIC_DisableIRQ(IRQn_Type IRQn)2347 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
2348 {
2349 if ((int32_t)(IRQn) >= 0)
2350 {
2351 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2352 __DSB();
2353 __ISB();
2354 }
2355 }
2356
2357
2358 /**
2359 \brief Get Pending Interrupt
2360 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
2361 \param [in] IRQn Device specific interrupt number.
2362 \return 0 Interrupt status is not pending.
2363 \return 1 Interrupt status is pending.
2364 \note IRQn must not be negative.
2365 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)2366 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
2367 {
2368 if ((int32_t)(IRQn) >= 0)
2369 {
2370 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2371 }
2372 else
2373 {
2374 return(0U);
2375 }
2376 }
2377
2378
2379 /**
2380 \brief Set Pending Interrupt
2381 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
2382 \param [in] IRQn Device specific interrupt number.
2383 \note IRQn must not be negative.
2384 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)2385 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
2386 {
2387 if ((int32_t)(IRQn) >= 0)
2388 {
2389 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2390 }
2391 }
2392
2393
2394 /**
2395 \brief Clear Pending Interrupt
2396 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
2397 \param [in] IRQn Device specific interrupt number.
2398 \note IRQn must not be negative.
2399 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)2400 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
2401 {
2402 if ((int32_t)(IRQn) >= 0)
2403 {
2404 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2405 }
2406 }
2407
2408
2409 /**
2410 \brief Get Active Interrupt
2411 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
2412 \param [in] IRQn Device specific interrupt number.
2413 \return 0 Interrupt status is not active.
2414 \return 1 Interrupt status is active.
2415 \note IRQn must not be negative.
2416 */
__NVIC_GetActive(IRQn_Type IRQn)2417 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
2418 {
2419 if ((int32_t)(IRQn) >= 0)
2420 {
2421 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2422 }
2423 else
2424 {
2425 return(0U);
2426 }
2427 }
2428
2429
2430 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2431 /**
2432 \brief Get Interrupt Target State
2433 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2434 \param [in] IRQn Device specific interrupt number.
2435 \return 0 if interrupt is assigned to Secure
2436 \return 1 if interrupt is assigned to Non Secure
2437 \note IRQn must not be negative.
2438 */
NVIC_GetTargetState(IRQn_Type IRQn)2439 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
2440 {
2441 if ((int32_t)(IRQn) >= 0)
2442 {
2443 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2444 }
2445 else
2446 {
2447 return(0U);
2448 }
2449 }
2450
2451
2452 /**
2453 \brief Set Interrupt Target State
2454 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2455 \param [in] IRQn Device specific interrupt number.
2456 \return 0 if interrupt is assigned to Secure
2457 1 if interrupt is assigned to Non Secure
2458 \note IRQn must not be negative.
2459 */
NVIC_SetTargetState(IRQn_Type IRQn)2460 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
2461 {
2462 if ((int32_t)(IRQn) >= 0)
2463 {
2464 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2465 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2466 }
2467 else
2468 {
2469 return(0U);
2470 }
2471 }
2472
2473
2474 /**
2475 \brief Clear Interrupt Target State
2476 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
2477 \param [in] IRQn Device specific interrupt number.
2478 \return 0 if interrupt is assigned to Secure
2479 1 if interrupt is assigned to Non Secure
2480 \note IRQn must not be negative.
2481 */
NVIC_ClearTargetState(IRQn_Type IRQn)2482 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
2483 {
2484 if ((int32_t)(IRQn) >= 0)
2485 {
2486 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
2487 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2488 }
2489 else
2490 {
2491 return(0U);
2492 }
2493 }
2494 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2495
2496
2497 /**
2498 \brief Set Interrupt Priority
2499 \details Sets the priority of a device specific interrupt or a processor exception.
2500 The interrupt number can be positive to specify a device specific interrupt,
2501 or negative to specify a processor exception.
2502 \param [in] IRQn Interrupt number.
2503 \param [in] priority Priority to set.
2504 \note The priority cannot be set for every processor exception.
2505 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)2506 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
2507 {
2508 if ((int32_t)(IRQn) >= 0)
2509 {
2510 NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2511 }
2512 else
2513 {
2514 SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2515 }
2516 }
2517
2518
2519 /**
2520 \brief Get Interrupt Priority
2521 \details Reads the priority of a device specific interrupt or a processor exception.
2522 The interrupt number can be positive to specify a device specific interrupt,
2523 or negative to specify a processor exception.
2524 \param [in] IRQn Interrupt number.
2525 \return Interrupt Priority.
2526 Value is aligned automatically to the implemented priority bits of the microcontroller.
2527 */
__NVIC_GetPriority(IRQn_Type IRQn)2528 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
2529 {
2530
2531 if ((int32_t)(IRQn) >= 0)
2532 {
2533 return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2534 }
2535 else
2536 {
2537 return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2538 }
2539 }
2540
2541
2542 /**
2543 \brief Encode Priority
2544 \details Encodes the priority for an interrupt with the given priority group,
2545 preemptive priority value, and subpriority value.
2546 In case of a conflict between priority grouping and available
2547 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2548 \param [in] PriorityGroup Used priority group.
2549 \param [in] PreemptPriority Preemptive priority value (starting from 0).
2550 \param [in] SubPriority Subpriority value (starting from 0).
2551 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
2552 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)2553 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
2554 {
2555 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2556 uint32_t PreemptPriorityBits;
2557 uint32_t SubPriorityBits;
2558
2559 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2560 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2561
2562 return (
2563 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
2564 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
2565 );
2566 }
2567
2568
2569 /**
2570 \brief Decode Priority
2571 \details Decodes an interrupt priority value with a given priority group to
2572 preemptive priority value and subpriority value.
2573 In case of a conflict between priority grouping and available
2574 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
2575 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
2576 \param [in] PriorityGroup Used priority group.
2577 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
2578 \param [out] pSubPriority Subpriority value (starting from 0).
2579 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)2580 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
2581 {
2582 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2583 uint32_t PreemptPriorityBits;
2584 uint32_t SubPriorityBits;
2585
2586 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
2587 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
2588
2589 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
2590 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
2591 }
2592
2593
2594 /**
2595 \brief Set Interrupt Vector
2596 \details Sets an interrupt vector in SRAM based interrupt vector table.
2597 The interrupt number can be positive to specify a device specific interrupt,
2598 or negative to specify a processor exception.
2599 VTOR must been relocated to SRAM before.
2600 \param [in] IRQn Interrupt number
2601 \param [in] vector Address of interrupt handler function
2602 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)2603 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
2604 {
2605 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2606 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
2607 __DSB();
2608 }
2609
2610
2611 /**
2612 \brief Get Interrupt Vector
2613 \details Reads an interrupt vector from interrupt vector table.
2614 The interrupt number can be positive to specify a device specific interrupt,
2615 or negative to specify a processor exception.
2616 \param [in] IRQn Interrupt number.
2617 \return Address of interrupt handler function
2618 */
__NVIC_GetVector(IRQn_Type IRQn)2619 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
2620 {
2621 uint32_t *vectors = (uint32_t *)SCB->VTOR;
2622 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
2623 }
2624
2625
2626 /**
2627 \brief System Reset
2628 \details Initiates a system reset request to reset the MCU.
2629 */
__NVIC_SystemReset(void)2630 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
2631 {
2632 __DSB(); /* Ensure all outstanding memory accesses including
2633 buffered write are completed before reset */
2634 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2635 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
2636 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
2637 __DSB(); /* Ensure completion of memory access */
2638
2639 for(;;) /* wait until reset */
2640 {
2641 __NOP();
2642 }
2643 }
2644
2645 /**
2646 \brief Software Reset
2647 \details Initiates a system reset request to reset the CPU.
2648 */
__SW_SystemReset(void)2649 __NO_RETURN __STATIC_INLINE void __SW_SystemReset(void)
2650 {
2651 __DSB(); /* Ensure all outstanding memory accesses including
2652 buffered write are completed before reset */
2653 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2654 (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */
2655 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */
2656 SCB_AIRCR_SYSRESETREQ_Msk );
2657 __DSB(); /* Ensure completion of memory access */
2658
2659 for(;;) /* wait until reset */
2660 {
2661 __NOP();
2662 }
2663 }
2664
2665
2666 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2667 /**
2668 \brief Set Priority Grouping (non-secure)
2669 \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
2670 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
2671 Only values from 0..7 are used.
2672 In case of a conflict between priority grouping and available
2673 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
2674 \param [in] PriorityGroup Priority grouping field.
2675 */
TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)2676 __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup)
2677 {
2678 uint32_t reg_value;
2679 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
2680
2681 reg_value = SCB_NS->AIRCR; /* read old register configuration */
2682 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
2683 reg_value = (reg_value |
2684 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
2685 (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
2686 SCB_NS->AIRCR = reg_value;
2687 }
2688
2689
2690 /**
2691 \brief Get Priority Grouping (non-secure)
2692 \details Reads the priority grouping field from the non-secure NVIC when in secure state.
2693 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
2694 */
TZ_NVIC_GetPriorityGrouping_NS(void)2695 __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void)
2696 {
2697 return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
2698 }
2699
2700
2701 /**
2702 \brief Enable Interrupt (non-secure)
2703 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2704 \param [in] IRQn Device specific interrupt number.
2705 \note IRQn must not be negative.
2706 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)2707 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
2708 {
2709 if ((int32_t)(IRQn) >= 0)
2710 {
2711 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2712 }
2713 }
2714
2715
2716 /**
2717 \brief Get Interrupt Enable status (non-secure)
2718 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
2719 \param [in] IRQn Device specific interrupt number.
2720 \return 0 Interrupt is not enabled.
2721 \return 1 Interrupt is enabled.
2722 \note IRQn must not be negative.
2723 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)2724 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
2725 {
2726 if ((int32_t)(IRQn) >= 0)
2727 {
2728 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2729 }
2730 else
2731 {
2732 return(0U);
2733 }
2734 }
2735
2736
2737 /**
2738 \brief Disable Interrupt (non-secure)
2739 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
2740 \param [in] IRQn Device specific interrupt number.
2741 \note IRQn must not be negative.
2742 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)2743 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
2744 {
2745 if ((int32_t)(IRQn) >= 0)
2746 {
2747 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2748 }
2749 }
2750
2751
2752 /**
2753 \brief Get Pending Interrupt (non-secure)
2754 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
2755 \param [in] IRQn Device specific interrupt number.
2756 \return 0 Interrupt status is not pending.
2757 \return 1 Interrupt status is pending.
2758 \note IRQn must not be negative.
2759 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)2760 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
2761 {
2762 if ((int32_t)(IRQn) >= 0)
2763 {
2764 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2765 }
2766 else
2767 {
2768 return(0U);
2769 }
2770 }
2771
2772
2773 /**
2774 \brief Set Pending Interrupt (non-secure)
2775 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2776 \param [in] IRQn Device specific interrupt number.
2777 \note IRQn must not be negative.
2778 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)2779 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
2780 {
2781 if ((int32_t)(IRQn) >= 0)
2782 {
2783 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2784 }
2785 }
2786
2787
2788 /**
2789 \brief Clear Pending Interrupt (non-secure)
2790 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
2791 \param [in] IRQn Device specific interrupt number.
2792 \note IRQn must not be negative.
2793 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)2794 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
2795 {
2796 if ((int32_t)(IRQn) >= 0)
2797 {
2798 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
2799 }
2800 }
2801
2802
2803 /**
2804 \brief Get Active Interrupt (non-secure)
2805 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
2806 \param [in] IRQn Device specific interrupt number.
2807 \return 0 Interrupt status is not active.
2808 \return 1 Interrupt status is active.
2809 \note IRQn must not be negative.
2810 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)2811 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
2812 {
2813 if ((int32_t)(IRQn) >= 0)
2814 {
2815 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
2816 }
2817 else
2818 {
2819 return(0U);
2820 }
2821 }
2822
2823
2824 /**
2825 \brief Set Interrupt Priority (non-secure)
2826 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2827 The interrupt number can be positive to specify a device specific interrupt,
2828 or negative to specify a processor exception.
2829 \param [in] IRQn Interrupt number.
2830 \param [in] priority Priority to set.
2831 \note The priority cannot be set for every non-secure processor exception.
2832 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2833 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2834 {
2835 if ((int32_t)(IRQn) >= 0)
2836 {
2837 NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2838 }
2839 else
2840 {
2841 SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
2842 }
2843 }
2844
2845
2846 /**
2847 \brief Get Interrupt Priority (non-secure)
2848 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2849 The interrupt number can be positive to specify a device specific interrupt,
2850 or negative to specify a processor exception.
2851 \param [in] IRQn Interrupt number.
2852 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2853 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2854 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2855 {
2856
2857 if ((int32_t)(IRQn) >= 0)
2858 {
2859 return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS)));
2860 }
2861 else
2862 {
2863 return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS)));
2864 }
2865 }
2866 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2867
2868 /*@} end of CMSIS_Core_NVICFunctions */
2869
2870 /* ########################## MPU functions #################################### */
2871
2872 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2873
2874 #include "mpu_armv8.h"
2875
2876 #endif
2877
2878 /* ########################## FPU functions #################################### */
2879 /**
2880 \ingroup CMSIS_Core_FunctionInterface
2881 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2882 \brief Function that provides FPU type.
2883 @{
2884 */
2885
2886 /**
2887 \brief get FPU type
2888 \details returns the FPU type
2889 \returns
2890 - \b 0: No FPU
2891 - \b 1: Single precision FPU
2892 - \b 2: Double + Single precision FPU
2893 */
SCB_GetFPUType(void)2894 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2895 {
2896 uint32_t mvfr0;
2897
2898 mvfr0 = FPU->MVFR0;
2899 if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U)
2900 {
2901 return 2U; /* Double + Single precision FPU */
2902 }
2903 else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U)
2904 {
2905 return 1U; /* Single precision FPU */
2906 }
2907 else
2908 {
2909 return 0U; /* No FPU */
2910 }
2911 }
2912
2913
2914 /*@} end of CMSIS_Core_FpuFunctions */
2915
2916
2917
2918 /* ########################## SAU functions #################################### */
2919 /**
2920 \ingroup CMSIS_Core_FunctionInterface
2921 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2922 \brief Functions that configure the SAU.
2923 @{
2924 */
2925
2926 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2927
2928 /**
2929 \brief Enable SAU
2930 \details Enables the Security Attribution Unit (SAU).
2931 */
TZ_SAU_Enable(void)2932 __STATIC_INLINE void TZ_SAU_Enable(void)
2933 {
2934 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2935 }
2936
2937
2938
2939 /**
2940 \brief Disable SAU
2941 \details Disables the Security Attribution Unit (SAU).
2942 */
TZ_SAU_Disable(void)2943 __STATIC_INLINE void TZ_SAU_Disable(void)
2944 {
2945 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2946 }
2947
2948 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2949
2950 /*@} end of CMSIS_Core_SAUFunctions */
2951
2952
2953
2954 /* ################################## Debug Control function ############################################ */
2955 /**
2956 \ingroup CMSIS_Core_FunctionInterface
2957 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2958 \brief Functions that access the Debug Control Block.
2959 @{
2960 */
2961
2962
2963 /**
2964 \brief Set Debug Authentication Control Register
2965 \details writes to Debug Authentication Control register.
2966 \param [in] value value to be writen.
2967 */
DCB_SetAuthCtrl(uint32_t value)2968 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2969 {
2970 __DSB();
2971 __ISB();
2972 DCB->DAUTHCTRL = value;
2973 __DSB();
2974 __ISB();
2975 }
2976
2977
2978 /**
2979 \brief Get Debug Authentication Control Register
2980 \details Reads Debug Authentication Control register.
2981 \return Debug Authentication Control Register.
2982 */
DCB_GetAuthCtrl(void)2983 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2984 {
2985 return (DCB->DAUTHCTRL);
2986 }
2987
2988
2989 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2990 /**
2991 \brief Set Debug Authentication Control Register (non-secure)
2992 \details writes to non-secure Debug Authentication Control register when in secure state.
2993 \param [in] value value to be writen
2994 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)2995 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2996 {
2997 __DSB();
2998 __ISB();
2999 DCB_NS->DAUTHCTRL = value;
3000 __DSB();
3001 __ISB();
3002 }
3003
3004
3005 /**
3006 \brief Get Debug Authentication Control Register (non-secure)
3007 \details Reads non-secure Debug Authentication Control register when in secure state.
3008 \return Debug Authentication Control Register.
3009 */
TZ_DCB_GetAuthCtrl_NS(void)3010 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
3011 {
3012 return (DCB_NS->DAUTHCTRL);
3013 }
3014 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3015
3016 /*@} end of CMSIS_Core_DCBFunctions */
3017
3018
3019
3020
3021 /* ################################## Debug Identification function ############################################ */
3022 /**
3023 \ingroup CMSIS_Core_FunctionInterface
3024 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
3025 \brief Functions that access the Debug Identification Block.
3026 @{
3027 */
3028
3029
3030 /**
3031 \brief Get Debug Authentication Status Register
3032 \details Reads Debug Authentication Status register.
3033 \return Debug Authentication Status Register.
3034 */
DIB_GetAuthStatus(void)3035 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
3036 {
3037 return (DIB->DAUTHSTATUS);
3038 }
3039
3040
3041 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3042 /**
3043 \brief Get Debug Authentication Status Register (non-secure)
3044 \details Reads non-secure Debug Authentication Status register when in secure state.
3045 \return Debug Authentication Status Register.
3046 */
TZ_DIB_GetAuthStatus_NS(void)3047 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
3048 {
3049 return (DIB_NS->DAUTHSTATUS);
3050 }
3051 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3052
3053 /*@} end of CMSIS_Core_DCBFunctions */
3054
3055
3056 #if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \
3057 (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)))
3058
3059 /* ########################## Cache functions #################################### */
3060 /**
3061 \ingroup CMSIS_Core_FunctionInterface
3062 \defgroup CMSIS_Core_CacheFunctions Cache Functions
3063 \brief Functions that configure Instruction and Data cache.
3064 @{
3065 */
3066
3067 /* Cache Size ID Register Macros */
3068 #define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
3069 #define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
3070
3071 #define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3072 #define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
3073
3074 /**
3075 \brief Enable I-Cache
3076 \details Turns on I-Cache
3077 */
SCB_EnableICache(void)3078 __STATIC_FORCEINLINE void SCB_EnableICache (void)
3079 {
3080 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3081 if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
3082
3083 __DSB();
3084 __ISB();
3085 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3086 __DSB();
3087 __ISB();
3088 SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
3089 __DSB();
3090 __ISB();
3091 #endif
3092 }
3093
3094
3095 /**
3096 \brief Disable I-Cache
3097 \details Turns off I-Cache
3098 */
SCB_DisableICache(void)3099 __STATIC_FORCEINLINE void SCB_DisableICache (void)
3100 {
3101 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3102 __DSB();
3103 __ISB();
3104 SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
3105 SCB->ICIALLU = 0UL; /* invalidate I-Cache */
3106 __DSB();
3107 __ISB();
3108 #endif
3109 }
3110
3111
3112 /**
3113 \brief Invalidate I-Cache
3114 \details Invalidates I-Cache
3115 */
SCB_InvalidateICache(void)3116 __STATIC_FORCEINLINE void SCB_InvalidateICache (void)
3117 {
3118 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3119 __DSB();
3120 __ISB();
3121 SCB->ICIALLU = 0UL;
3122 __DSB();
3123 __ISB();
3124 #endif
3125 }
3126
3127
3128 /**
3129 \brief I-Cache Invalidate by address
3130 \details Invalidates I-Cache for the given address.
3131 I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3132 I-Cache memory blocks which are part of given address + given size are invalidated.
3133 \param[in] addr address
3134 \param[in] isize size of memory block (in number of bytes)
3135 */
SCB_InvalidateICache_by_Addr(void * addr,int32_t isize)3136 __STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
3137 {
3138 #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
3139 if ( isize > 0 ) {
3140 int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
3141 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
3142
3143 __DSB();
3144
3145 do {
3146 SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3147 op_addr += __SCB_ICACHE_LINE_SIZE;
3148 op_size -= __SCB_ICACHE_LINE_SIZE;
3149 } while ( op_size > 0 );
3150
3151 __DSB();
3152 __ISB();
3153 }
3154 #endif
3155 }
3156
3157
3158 /**
3159 \brief Enable D-Cache
3160 \details Turns on D-Cache
3161 */
SCB_EnableDCache(void)3162 __STATIC_FORCEINLINE void SCB_EnableDCache (void)
3163 {
3164 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3165 uint32_t ccsidr;
3166 uint32_t sets;
3167 uint32_t ways;
3168
3169 if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
3170
3171 SCB->CSSELR = 0U; /* select Level 1 data cache */
3172 __DSB();
3173
3174 ccsidr = SCB->CCSIDR;
3175
3176 /* invalidate D-Cache */
3177 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3178 do {
3179 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3180 do {
3181 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3182 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3183 #if defined ( __CC_ARM )
3184 __schedule_barrier();
3185 #endif
3186 } while (ways-- != 0U);
3187 } while(sets-- != 0U);
3188 __DSB();
3189
3190 SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
3191
3192 __DSB();
3193 __ISB();
3194 #endif
3195 }
3196
3197
3198 /**
3199 \brief Disable D-Cache
3200 \details Turns off D-Cache
3201 */
SCB_DisableDCache(void)3202 __STATIC_FORCEINLINE void SCB_DisableDCache (void)
3203 {
3204 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3205 uint32_t ccsidr;
3206 uint32_t sets;
3207 uint32_t ways;
3208
3209 SCB->CSSELR = 0U; /* select Level 1 data cache */
3210 __DSB();
3211
3212 SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
3213 __DSB();
3214
3215 ccsidr = SCB->CCSIDR;
3216
3217 /* clean & invalidate D-Cache */
3218 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3219 do {
3220 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3221 do {
3222 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3223 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3224 #if defined ( __CC_ARM )
3225 __schedule_barrier();
3226 #endif
3227 } while (ways-- != 0U);
3228 } while(sets-- != 0U);
3229
3230 __DSB();
3231 __ISB();
3232 #endif
3233 }
3234
3235
3236 /**
3237 \brief Invalidate D-Cache
3238 \details Invalidates D-Cache
3239 */
SCB_InvalidateDCache(void)3240 __STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
3241 {
3242 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3243 uint32_t ccsidr;
3244 uint32_t sets;
3245 uint32_t ways;
3246
3247 SCB->CSSELR = 0U; /* select Level 1 data cache */
3248 __DSB();
3249
3250 ccsidr = SCB->CCSIDR;
3251
3252 /* invalidate D-Cache */
3253 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3254 do {
3255 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3256 do {
3257 SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
3258 ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
3259 #if defined ( __CC_ARM )
3260 __schedule_barrier();
3261 #endif
3262 } while (ways-- != 0U);
3263 } while(sets-- != 0U);
3264
3265 __DSB();
3266 __ISB();
3267 #endif
3268 }
3269
3270
3271 /**
3272 \brief Clean D-Cache
3273 \details Cleans D-Cache
3274 */
SCB_CleanDCache(void)3275 __STATIC_FORCEINLINE void SCB_CleanDCache (void)
3276 {
3277 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3278 uint32_t ccsidr;
3279 uint32_t sets;
3280 uint32_t ways;
3281
3282 SCB->CSSELR = 0U; /* select Level 1 data cache */
3283 __DSB();
3284
3285 ccsidr = SCB->CCSIDR;
3286
3287 /* clean D-Cache */
3288 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3289 do {
3290 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3291 do {
3292 SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
3293 ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
3294 #if defined ( __CC_ARM )
3295 __schedule_barrier();
3296 #endif
3297 } while (ways-- != 0U);
3298 } while(sets-- != 0U);
3299
3300 __DSB();
3301 __ISB();
3302 #endif
3303 }
3304
3305
3306 /**
3307 \brief Clean & Invalidate D-Cache
3308 \details Cleans and Invalidates D-Cache
3309 */
SCB_CleanInvalidateDCache(void)3310 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
3311 {
3312 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3313 uint32_t ccsidr;
3314 uint32_t sets;
3315 uint32_t ways;
3316
3317 SCB->CSSELR = 0U; /* select Level 1 data cache */
3318 __DSB();
3319
3320 ccsidr = SCB->CCSIDR;
3321
3322 /* clean & invalidate D-Cache */
3323 sets = (uint32_t)(CCSIDR_SETS(ccsidr));
3324 do {
3325 ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
3326 do {
3327 SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
3328 ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
3329 #if defined ( __CC_ARM )
3330 __schedule_barrier();
3331 #endif
3332 } while (ways-- != 0U);
3333 } while(sets-- != 0U);
3334
3335 __DSB();
3336 __ISB();
3337 #endif
3338 }
3339
3340
3341 /**
3342 \brief D-Cache Invalidate by address
3343 \details Invalidates D-Cache for the given address.
3344 D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
3345 D-Cache memory blocks which are part of given address + given size are invalidated.
3346 \param[in] addr address
3347 \param[in] dsize size of memory block (in number of bytes)
3348 */
SCB_InvalidateDCache_by_Addr(void * addr,int32_t dsize)3349 __STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
3350 {
3351 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3352 if ( dsize > 0 ) {
3353 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3354 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3355
3356 __DSB();
3357
3358 do {
3359 SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3360 op_addr += __SCB_DCACHE_LINE_SIZE;
3361 op_size -= __SCB_DCACHE_LINE_SIZE;
3362 } while ( op_size > 0 );
3363
3364 __DSB();
3365 __ISB();
3366 }
3367 #endif
3368 }
3369
3370
3371 /**
3372 \brief D-Cache Clean by address
3373 \details Cleans D-Cache for the given address
3374 D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
3375 D-Cache memory blocks which are part of given address + given size are cleaned.
3376 \param[in] addr address
3377 \param[in] dsize size of memory block (in number of bytes)
3378 */
SCB_CleanDCache_by_Addr(uint32_t * addr,int32_t dsize)3379 __STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
3380 {
3381 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3382 if ( dsize > 0 ) {
3383 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3384 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3385
3386 __DSB();
3387
3388 do {
3389 SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3390 op_addr += __SCB_DCACHE_LINE_SIZE;
3391 op_size -= __SCB_DCACHE_LINE_SIZE;
3392 } while ( op_size > 0 );
3393
3394 __DSB();
3395 __ISB();
3396 }
3397 #endif
3398 }
3399
3400
3401 /**
3402 \brief D-Cache Clean and Invalidate by address
3403 \details Cleans and invalidates D_Cache for the given address
3404 D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
3405 D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
3406 \param[in] addr address (aligned to 32-byte boundary)
3407 \param[in] dsize size of memory block (in number of bytes)
3408 */
SCB_CleanInvalidateDCache_by_Addr(uint32_t * addr,int32_t dsize)3409 __STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
3410 {
3411 #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
3412 if ( dsize > 0 ) {
3413 int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
3414 uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
3415
3416 __DSB();
3417
3418 do {
3419 SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
3420 op_addr += __SCB_DCACHE_LINE_SIZE;
3421 op_size -= __SCB_DCACHE_LINE_SIZE;
3422 } while ( op_size > 0 );
3423
3424 __DSB();
3425 __ISB();
3426 }
3427 #endif
3428 }
3429
3430 /*@} end of CMSIS_Core_CacheFunctions */
3431 #endif
3432
3433
3434 /* ################################## SysTick function ############################################ */
3435 /**
3436 \ingroup CMSIS_Core_FunctionInterface
3437 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
3438 \brief Functions that configure the System.
3439 @{
3440 */
3441
3442 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
3443
3444 /**
3445 \brief System Tick Configuration
3446 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
3447 Counter is in free running mode to generate periodic interrupts.
3448 \param [in] ticks Number of ticks between two interrupts.
3449 \return 0 Function succeeded.
3450 \return 1 Function failed.
3451 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3452 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
3453 must contain a vendor-specific implementation of this function.
3454 */
SysTick_Config(uint32_t ticks)3455 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
3456 {
3457 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3458 {
3459 return (1UL); /* Reload value impossible */
3460 }
3461
3462 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3463 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3464 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
3465 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3466 SysTick_CTRL_TICKINT_Msk |
3467 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3468 return (0UL); /* Function successful */
3469 }
3470
3471 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
3472 /**
3473 \brief System Tick Configuration (non-secure)
3474 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
3475 Counter is in free running mode to generate periodic interrupts.
3476 \param [in] ticks Number of ticks between two interrupts.
3477 \return 0 Function succeeded.
3478 \return 1 Function failed.
3479 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
3480 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
3481 must contain a vendor-specific implementation of this function.
3482
3483 */
TZ_SysTick_Config_NS(uint32_t ticks)3484 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
3485 {
3486 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
3487 {
3488 return (1UL); /* Reload value impossible */
3489 }
3490
3491 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
3492 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
3493 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
3494 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
3495 SysTick_CTRL_TICKINT_Msk |
3496 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
3497 return (0UL); /* Function successful */
3498 }
3499 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
3500
3501 #endif
3502
3503 /*@} end of CMSIS_Core_SysTickFunctions */
3504
3505
3506
3507 /* ##################################### Debug In/Output function ########################################### */
3508 /**
3509 \ingroup CMSIS_Core_FunctionInterface
3510 \defgroup CMSIS_core_DebugFunctions ITM Functions
3511 \brief Functions that access the ITM debug interface.
3512 @{
3513 */
3514
3515 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
3516 #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
3517
3518
3519 /**
3520 \brief ITM Send Character
3521 \details Transmits a character via the ITM channel 0, and
3522 \li Just returns when no debugger is connected that has booked the output.
3523 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
3524 \param [in] ch Character to transmit.
3525 \returns Character to transmit.
3526 */
ITM_SendChar(uint32_t ch)3527 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
3528 {
3529 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
3530 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
3531 {
3532 while (ITM->PORT[0U].u32 == 0UL)
3533 {
3534 __NOP();
3535 }
3536 ITM->PORT[0U].u8 = (uint8_t)ch;
3537 }
3538 return (ch);
3539 }
3540
3541
3542 /**
3543 \brief ITM Receive Character
3544 \details Inputs a character via the external variable \ref ITM_RxBuffer.
3545 \return Received character.
3546 \return -1 No character pending.
3547 */
ITM_ReceiveChar(void)3548 __STATIC_INLINE int32_t ITM_ReceiveChar (void)
3549 {
3550 int32_t ch = -1; /* no character available */
3551
3552 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY)
3553 {
3554 ch = ITM_RxBuffer;
3555 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
3556 }
3557
3558 return (ch);
3559 }
3560
3561
3562 /**
3563 \brief ITM Check Character
3564 \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
3565 \return 0 No character available.
3566 \return 1 Character available.
3567 */
ITM_CheckChar(void)3568 __STATIC_INLINE int32_t ITM_CheckChar (void)
3569 {
3570
3571 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY)
3572 {
3573 return (0); /* no character available */
3574 }
3575 else
3576 {
3577 return (1); /* character available */
3578 }
3579 }
3580
3581 /*@} end of CMSIS_core_DebugFunctions */
3582
3583
3584
3585
3586 #ifdef __cplusplus
3587 }
3588 #endif
3589
3590 #endif /* __CORE_STAR_H_DEPENDANT */
3591
3592 #endif /* __CMSIS_GENERIC */
3593
