1 /**************************************************************************//**
2 * @file core_cr.h
3 * @brief CMSIS Cortex-R Core Peripheral Access Layer Header File
4 * @version V1.0.0
5 * @date 17. October 2019
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
9 * Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
10 *
11 * SPDX-License-Identifier: Apache-2.0
12 *
13 * Licensed under the Apache License, Version 2.0 (the License); you may
14 * not use this file except in compliance with the License.
15 * You may obtain a copy of the License at
16 *
17 * www.apache.org/licenses/LICENSE-2.0
18 *
19 * Unless required by applicable law or agreed to in writing, software
20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 * See the License for the specific language governing permissions and
23 * limitations under the License.
24 */
25
26 #if defined ( __ICCARM__ )
27 #pragma system_include /* treat file as system include file for MISRA check */
28 #elif defined (__clang__)
29 #pragma clang system_header /* treat file as system include file */
30 #endif
31
32 #ifndef __CORE_CR_H_GENERIC
33 #define __CORE_CR_H_GENERIC
34
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38
39 /*******************************************************************************
40 * CMSIS definitions
41 ******************************************************************************/
42
43 /* CMSIS CR definitions */
44 #define __CR_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(R) main version */
45 #define __CR_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS-Core(R) sub version */
46 #define __CR_CMSIS_VERSION ((__CR_CMSIS_VERSION_MAIN << 16U) | \
47 __CR_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(R) version number */
48
49 #if defined ( __CC_ARM )
50 #if defined __TARGET_FPU_VFP
51 #if (__FPU_PRESENT == 1)
52 #define __FPU_USED 1U
53 #else
54 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
55 #define __FPU_USED 0U
56 #endif
57 #else
58 #define __FPU_USED 0U
59 #endif
60
61 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
62 #if defined __ARM_FP
63 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)
64 #define __FPU_USED 1U
65 #else
66 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
67 #define __FPU_USED 0U
68 #endif
69 #else
70 #define __FPU_USED 0U
71 #endif
72
73 #elif defined ( __ICCARM__ )
74 #if defined __ARMVFP__
75 #if (__FPU_PRESENT == 1)
76 #define __FPU_USED 1U
77 #else
78 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
79 #define __FPU_USED 0U
80 #endif
81 #else
82 #define __FPU_USED 0U
83 #endif
84
85 #elif defined ( __TMS470__ )
86 #if defined __TI_VFP_SUPPORT__
87 #if (__FPU_PRESENT == 1)
88 #define __FPU_USED 1U
89 #else
90 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
91 #define __FPU_USED 0U
92 #endif
93 #else
94 #define __FPU_USED 0U
95 #endif
96
97 #elif defined ( __GNUC__ )
98 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
99 #if (__FPU_PRESENT == 1)
100 #define __FPU_USED 1U
101 #else
102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #define __FPU_USED 0U
104 #endif
105 #else
106 #define __FPU_USED 0U
107 #endif
108
109 #elif defined ( __TASKING__ )
110 #if defined __FPU_VFP__
111 #if (__FPU_PRESENT == 1)
112 #define __FPU_USED 1U
113 #else
114 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
115 #define __FPU_USED 0U
116 #endif
117 #else
118 #define __FPU_USED 0U
119 #endif
120 #endif
121
122 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
123
124 #ifdef __cplusplus
125 }
126 #endif
127
128 #endif /* __CORE_CR_H_GENERIC */
129
130 #ifndef __CMSIS_GENERIC
131
132 #ifndef __CORE_CR_H_DEPENDANT
133 #define __CORE_CR_H_DEPENDANT
134
135 #ifdef __cplusplus
136 extern "C" {
137 #endif
138
139 /* check device defines and use defaults */
140 #if defined __CHECK_DEVICE_DEFINES
141 #ifndef __CR_REV
142 #define __CR_REV 0x0000U
143 #warning "__CR_REV not defined in device header file; using default!"
144 #endif
145
146 #ifndef __FPU_PRESENT
147 #define __FPU_PRESENT 0U
148 #warning "__FPU_PRESENT not defined in device header file; using default!"
149 #endif
150
151 #ifndef __GIC_PRESENT
152 #define __GIC_PRESENT 1U
153 #warning "__GIC_PRESENT not defined in device header file; using default!"
154 #endif
155
156 #ifndef __TIM_PRESENT
157 #define __TIM_PRESENT 1U
158 #warning "__TIM_PRESENT not defined in device header file; using default!"
159 #endif
160
161 #ifndef __MPU_PRESENT
162 #define __MPU_PRESENT 1U
163 #warning "__MPU_PRESENT not defined in device header file; using default!"
164 #endif
165 #endif
166
167 /* IO definitions (access restrictions to peripheral registers) */
168 #ifdef __cplusplus
169 #define __I volatile /*!< \brief Defines 'read only' permissions */
170 #else
171 #define __I volatile const /*!< \brief Defines 'read only' permissions */
172 #endif
173 #define __O volatile /*!< \brief Defines 'write only' permissions */
174 #define __IO volatile /*!< \brief Defines 'read / write' permissions */
175
176 /* following defines should be used for structure members */
177 #define __IM volatile const /*!< \brief Defines 'read only' structure member permissions */
178 #define __OM volatile /*!< \brief Defines 'write only' structure member permissions */
179 #define __IOM volatile /*!< \brief Defines 'read / write' structure member permissions */
180 #define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas
181
182 /*******************************************************************************
183 * Register Abstraction
184 Core Register contain:
185 - CPSR
186 - CP15 Registers
187 - Generic Interrupt Controller Distributor
188 - Generic Interrupt Controller Interface
189 ******************************************************************************/
190
191 /* Core Register CPSR */
192 typedef union
193 {
194 struct
195 {
196 uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */
197 uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */
198 uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */
199 uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */
200 uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */
201 uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */
202 uint32_t IT1:6; /*!< \brief bit: 10..15 If-Then execution state bits 2-7 */
203 uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */
204 RESERVED(0:4, uint32_t)
205 uint32_t J:1; /*!< \brief bit: 24 Jazelle bit */
206 uint32_t IT0:2; /*!< \brief bit: 25..26 If-Then execution state bits 0-1 */
207 uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */
208 uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */
209 uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */
210 uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */
211 uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */
212 } b; /*!< \brief Structure used for bit access */
213 uint32_t w; /*!< \brief Type used for word access */
214 } CPSR_Type;
215
216
217
218 /* CPSR Register Definitions */
219 #define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */
220 #define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */
221
222 #define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */
223 #define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */
224
225 #define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */
226 #define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */
227
228 #define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */
229 #define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */
230
231 #define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */
232 #define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */
233
234 #define CPSR_IT0_Pos 25U /*!< \brief CPSR: IT0 Position */
235 #define CPSR_IT0_Msk (3UL << CPSR_IT0_Pos) /*!< \brief CPSR: IT0 Mask */
236
237 #define CPSR_J_Pos 24U /*!< \brief CPSR: J Position */
238 #define CPSR_J_Msk (1UL << CPSR_J_Pos) /*!< \brief CPSR: J Mask */
239
240 #define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */
241 #define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */
242
243 #define CPSR_IT1_Pos 10U /*!< \brief CPSR: IT1 Position */
244 #define CPSR_IT1_Msk (0x3FUL << CPSR_IT1_Pos) /*!< \brief CPSR: IT1 Mask */
245
246 #define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */
247 #define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */
248
249 #define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */
250 #define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */
251
252 #define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */
253 #define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */
254
255 #define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */
256 #define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */
257
258 #define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */
259 #define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */
260
261 #define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */
262 #define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */
263
264 #define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */
265 #define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */
266 #define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */
267 #define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */
268 #define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */
269 #define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */
270 #define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */
271 #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */
272 #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */
273
274 /* CP15 Register SCTLR */
275 typedef union
276 {
277 #if __CORTEX_R == 4 || __CORTEX_R == 5 || defined(DOXYGEN)
278 struct
279 {
280 uint32_t M:1; /*!< \brief bit: 0 MPU enable */
281 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
282 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
283 RESERVED(0:7, uint32_t)
284 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
285 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
286 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
287 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
288 uint32_t RR:1; /*!< \brief bit: 14 Round Robin select */
289 RESERVED(1:2, uint32_t)
290 uint32_t BR:1; /*!< \brief bit: 17 Background region access */
291 RESERVED(2:1, uint32_t)
292 uint32_t DZ:1; /*!< \brief bit: 19 Divide-by-zero fault enable */
293 RESERVED(3:1, uint32_t)
294 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
295 RESERVED(4:2, uint32_t)
296 uint32_t VE:1; /*!< \brief bit: 24 Interrupt Vectors Enable */
297 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
298 RESERVED(5:1, uint32_t)
299 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
300 uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */
301 uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */
302 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
303 uint32_t IE:1; /*!< \brief bit: 31 Instruction endianness */
304 } b; /*!< \brief Structure used for bit access */
305 #endif
306 #if __CORTEX_R == 7 || __CORTEX_R == 8 || defined(DOXYGEN)
307 struct
308 {
309 uint32_t M:1; /*!< \brief bit: 0 MPU enable */
310 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
311 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
312 RESERVED(0:7, uint32_t)
313 uint32_t SW:1; /*!< \brief bit: 10 SWP and SWPB enable */
314 uint32_t Z:1; /*!< \brief bit: 11 Branch prediction enable */
315 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
316 uint32_t V:1; /*!< \brief bit: 13 Vectors bit */
317 RESERVED(1:3, uint32_t)
318 uint32_t BR:1; /*!< \brief bit: 17 Background region access */
319 RESERVED(2:1, uint32_t)
320 uint32_t DZ:1; /*!< \brief bit: 19 Divide-by-zero fault enable */
321 RESERVED(3:1, uint32_t)
322 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
323 RESERVED(4:3, uint32_t)
324 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
325 RESERVED(5:1, uint32_t)
326 uint32_t NMFI:1; /*!< \brief bit: 27 Non-maskable FIQ (NMFI) support */
327 RESERVED(6:2, uint32_t)
328 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
329 RESERVED(7:1, uint32_t)
330 } b; /*!< \brief Structure used for bit access */
331 #endif
332 #if __CORTEX_R == 52 || defined(DOXYGEN)
333 struct
334 {
335 uint32_t M:1; /*!< \brief bit: 0 MPU enable */
336 uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */
337 uint32_t C:1; /*!< \brief bit: 2 Cache enable */
338 RESERVED(0:2, uint32_t)
339 uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */
340 RESERVED(1:1, uint32_t)
341 uint32_t ITD:1; /*!< \brief bit: 7 If-Then disable */
342 uint32_t SED:1; /*!< \brief bit: 8 SETEND disable */
343 RESERVED(2:3, uint32_t)
344 uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */
345 RESERVED(3:3, uint32_t)
346 uint32_t NTWI:1; /*!< \brief bit: 16 Do not trap WFI */
347 uint32_t BR:1; /*!< \brief bit: 17 Background region access */
348 uint32_t NTWE:1; /*!< \brief bit: 18 Do not trap WFE */
349 uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */
350 uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */
351 uint32_t FI:1; /*!< \brief bit: 21 Fast interrupts configuration enable */
352 RESERVED(4:3, uint32_t)
353 uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */
354 RESERVED(5:4, uint32_t)
355 uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */
356 RESERVED(6:1, uint32_t)
357 } b; /*!< \brief Structure used for bit access */
358 #endif
359 uint32_t w; /*!< \brief Type used for word access */
360 } SCTLR_Type;
361
362 #define SCTLR_IE_Pos 31U /*!< \brief SCTLR: IE Position */
363 #define SCTLR_IE_Msk (1UL << SCTLR_IE_Pos) /*!< \brief SCTLR: IE Mask */
364
365 #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */
366 #define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */
367
368 #define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */
369 #define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */
370
371 #define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */
372 #define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */
373
374 #define SCTLR_NMFI_Pos 27U /*!< \brief SCTLR: NMFI Position */
375 #define SCTLR_NMFI_Msk (1UL << SCTLR_NMFI_Pos) /*!< \brief SCTLR: NMFI Mask */
376
377 #define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */
378 #define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */
379
380 #define SCTLR_VE_Pos 24U /*!< \brief SCTLR: VE Position */
381 #define SCTLR_VE_Msk (1UL << SCTLR_VE_Pos) /*!< \brief SCTLR: VE Mask */
382
383 #define SCTLR_FI_Pos 21U /*!< \brief SCTLR: FI Position */
384 #define SCTLR_FI_Msk (1UL << SCTLR_FI_Pos) /*!< \brief SCTLR: FI Mask */
385
386 #define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */
387 #define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */
388
389 #define SCTLR_DZ_Pos 19U /*!< \brief SCTLR: DZ Position */
390 #define SCTLR_DZ_Msk (1UL << SCTLR_DZ_Pos) /*!< \brief SCTLR: DZ Mask */
391
392 #define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */
393 #define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */
394
395 #define SCTLR_NTWE_Pos 18U /*!< \brief SCTLR: NTWE Position */
396 #define SCTLR_NTWE_Msk (1UL << SCTLR_NTWE_Pos) /*!< \brief SCTLR: NTWE Mask */
397
398 #define SCTLR_BR_Pos 17U /*!< \brief SCTLR: BR Position */
399 #define SCTLR_BR_Msk (1UL << SCTLR_BR_Pos) /*!< \brief SCTLR: BR Mask */
400
401 #define SCTLR_NTWI_Pos 16U /*!< \brief SCTLR: NTWI Position */
402 #define SCTLR_NTWI_Msk (1UL << SCTLR_NTWI_Pos) /*!< \brief SCTLR: NTWI Mask */
403
404 #define SCTLR_RR_Pos 14U /*!< \brief SCTLR: RR Position */
405 #define SCTLR_RR_Msk (1UL << SCTLR_RR_Pos) /*!< \brief SCTLR: RR Mask */
406
407 #define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */
408 #define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */
409
410 #define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */
411 #define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */
412
413 #define SCTLR_Z_Pos 11U /*!< \brief SCTLR: Z Position */
414 #define SCTLR_Z_Msk (1UL << SCTLR_Z_Pos) /*!< \brief SCTLR: Z Mask */
415
416 #define SCTLR_SW_Pos 10U /*!< \brief SCTLR: SW Position */
417 #define SCTLR_SW_Msk (1UL << SCTLR_SW_Pos) /*!< \brief SCTLR: SW Mask */
418
419 #define SCTLR_SED_Pos 8U /*!< \brief SCTLR: SED Position */
420 #define SCTLR_SED_Msk (1UL << SCTLR_SED_Pos) /*!< \brief SCTLR: SED Mask */
421
422 #define SCTLR_ITD_Pos 7U /*!< \brief SCTLR: ITD Position */
423 #define SCTLR_ITD_Msk (1UL << SCTLR_ITD_Pos) /*!< \brief SCTLR: ITD Mask */
424
425 #define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */
426 #define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */
427
428 #define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */
429 #define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */
430
431 #define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */
432 #define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */
433
434 #define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */
435 #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */
436
437 /* CP15 Register ACTLR */
438 typedef union
439 {
440 #if __CORTEX_R == 4 || __CORTEX_R == 5 || defined(DOXYGEN)
441 struct
442 {
443 uint32_t ATCMECEN:1; /*!< \brief bit: 0 ATCM external error enable */
444 uint32_t B0TCMECEN:1; /*!< \brief bit: 1 B0TCM external error enable */
445 uint32_t B1TCMECEN:1; /*!< \brief bit: 2 B1TCM external error enable */
446 uint32_t CEC:3; /*!< \brief bit: 3.. 5 Cache error control */
447 uint32_t DILS:1; /*!< \brief bit: 6 Low interrupt latency disable */
448 uint32_t SMOV:1; /*!< \brief bit: 7 SMOV out-of-order disable */
449 uint32_t FDSNS:1; /*!< \brief bit: 8 Force D-side not shared when MPU is off */
450 uint32_t FWT:1; /*!< \brief bit: 9 Force write-through for write-back regions */
451 uint32_t FORA:1; /*!< \brief bit: 10 Force out-read-allocate for out-write-allocate regions */
452 uint32_t DNCH:1; /*!< \brief bit: 11 Data forwarding for non-cachable access disable */
453 uint32_t ERPEG:1; /*!< \brief bit: 12 Random parity error generation enable */
454 uint32_t DLFO:1; /*!< \brief bit: 13 Linefill optimization disable */
455 uint32_t DBWR:1; /*!< \brief bit: 14 Write burst disable */
456 uint32_t BP:2; /*!< \brief bit:15..16 Branch prediction policy */
457 uint32_t RSDIS:1; /*!< \brief bit: 17 Return stack disable */
458 RESERVED(0:1, uint32_t)
459 uint32_t FRCDIS:1; /*!< \brief bit: 19 Fetch rate control disable */
460 uint32_t DBHE:1; /*!< \brief bit: 20 Branch history extension disable */
461 uint32_t DEOLP:1; /*!< \brief bit: 21 End-of-loop prediction disable */
462 uint32_t DILSM:1; /*!< \brief bit: 22 Low interrupt latency on load/store multiples disable */
463 uint32_t AXISCUEN:1; /*!< \brief bit: 23 AXI slave cache RAM non-privileged access enable */
464 uint32_t AXISCEN:1; /*!< \brief bit: 24 AXI slave cache RAM access enable */
465 uint32_t ATCMPCEN:1; /*!< \brief bit: 25 ATCM ECC check enable */
466 uint32_t B0TCMPCEN:1; /*!< \brief bit: 26 B0TCM ECC check enable */
467 uint32_t B1TCMPCEN:1; /*!< \brief bit: 27 B1TCM ECC check enable */
468 uint32_t DIADI:1; /*!< \brief bit: 28 Case A dual issue disable */
469 uint32_t DIB1DI:1; /*!< \brief bit: 29 Case B1 dual issue disable */
470 uint32_t DIB2DI:1; /*!< \brief bit: 30 Case B2 dual issue disable */
471 uint32_t DICDI:1; /*!< \brief bit: 31 Case C dual issue disable */
472 } b;
473 #endif
474 #if __CORTEX_R == 7 || __CORTEX_R == 8 || defined(DOXYGEN)
475 struct
476 {
477 uint32_t FW:1; /*!< \brief bit: 0 Cache and TLB maintenance broadcast */
478 RESERVED(0:2, uint32_t)
479 uint32_t MRPEN:1; /*!< \brief bit: 3 MRP enable */
480 RESERVED(1:2, uint32_t)
481 uint32_t SMP:1; /*!< \brief bit: 6 Processor coherency enable */
482 RESERVED(2:1, uint32_t)
483 uint32_t AOW:1; /*!< \brief bit: 8 One way cache allocation enable */
484 uint32_t DTCMECEN:1; /*!< \brief bit: 9 Cache and DTCM ECC support */
485 uint32_t ITCMECEN:1; /*!< \brief bit: 10 ITCM ECC support */
486 uint32_t QOSEN:1; /*!< \brief bit: 11 Quality-of-service enable */
487 RESERVED(3:20, uint32_t)
488 } b;
489 #endif
490 #if __CORTEX_R == 52 || defined(DOXYGEN)
491 struct
492 {
493 RESERVED(0:32, uint32_t)
494 } b;
495 #endif
496 uint32_t w; /*!< \brief Type used for word access */
497 } ACTLR_Type;
498
499 #define ACTLR_DICDI_Pos 31U /*!< \brief ACTLR: DICDI Position */
500 #define ACTLR_DICDI_Msk (1UL << ACTLR_DICDI_Pos) /*!< \brief ACTLR: DICDI Mask */
501
502 #define ACTLR_DIB2DI_Pos 30U /*!< \brief ACTLR: DIB2DI Position */
503 #define ACTLR_DIB2DI_Msk (1UL << ACTLR_DIB2DI_Pos) /*!< \brief ACTLR: DIB2DI Mask */
504
505 #define ACTLR_DIB1DI_Pos 29U /*!< \brief ACTLR: DIB1DI Position */
506 #define ACTLR_DIB1DI_Msk (1UL << ACTLR_DIB1DI_Pos) /*!< \brief ACTLR: DIB1DI Mask */
507
508 #define ACTLR_DIADI_Pos 28U /*!< \brief ACTLR: DIADI Position */
509 #define ACTLR_DIADI_Msk (1UL << ACTLR_DIADI_Pos) /*!< \brief ACTLR: DIADI Mask */
510
511 #define ACTLR_B1TCMPCEN_Pos 27U /*!< \brief ACTLR: B1TCMPCEN Position */
512 #define ACTLR_B1TCMPCEN_Msk (1UL << ACTLR_B1TCMPCEN_Pos) /*!< \brief ACTLR: B1TCMPCEN Mask */
513
514 #define ACTLR_B0TCMPCEN_Pos 26U /*!< \brief ACTLR: B0TCMPCEN Position */
515 #define ACTLR_B0TCMPCEN_Msk (1UL << ACTLR_B0TCMPCEN_Pos) /*!< \brief ACTLR: B0TCMPCEN Mask */
516
517 #define ACTLR_ATCMPCEN_Pos 25U /*!< \brief ACTLR: ATCMPCEN Position */
518 #define ACTLR_ATCMPCEN_Msk (1UL << ACTLR_ATCMPCEN_Pos) /*!< \brief ACTLR: ATCMPCEN Mask */
519
520 #define ACTLR_AXISCEN_Pos 24U /*!< \brief ACTLR: AXISCEN Position */
521 #define ACTLR_AXISCEN_Msk (1UL << ACTLR_AXISCEN_Pos) /*!< \brief ACTLR: AXISCEN Mask */
522
523 #define ACTLR_AXISCUEN_Pos 23U /*!< \brief ACTLR: AXISCUEN Position */
524 #define ACTLR_AXISCUEN_Msk (1UL << ACTLR_AXISCUEN_Pos) /*!< \brief ACTLR: AXISCUEN Mask */
525
526 #define ACTLR_DILSM_Pos 22U /*!< \brief ACTLR: DILSM Position */
527 #define ACTLR_DILSM_Msk (1UL << ACTLR_DILSM_Pos) /*!< \brief ACTLR: DILSM Mask */
528
529 #define ACTLR_DEOLP_Pos 21U /*!< \brief ACTLR: DEOLP Position */
530 #define ACTLR_DEOLP_Msk (1UL << ACTLR_DEOLP_Pos) /*!< \brief ACTLR: DEOLP Mask */
531
532 #define ACTLR_DBHE_Pos 20U /*!< \brief ACTLR: DBHE Position */
533 #define ACTLR_DBHE_Msk (1UL << ACTLR_DBHE_Pos) /*!< \brief ACTLR: DBHE Mask */
534
535 #define ACTLR_FRCDIS_Pos 19U /*!< \brief ACTLR: FRCDIS Position */
536 #define ACTLR_FRCDIS_Msk (1UL << ACTLR_FRCDIS_Pos) /*!< \brief ACTLR: FRCDIS Mask */
537
538 #define ACTLR_RSDIS_Pos 17U /*!< \brief ACTLR: RSDIS Position */
539 #define ACTLR_RSDIS_Msk (1UL << ACTLR_RSDIS_Pos) /*!< \brief ACTLR: RSDIS Mask */
540
541 #define ACTLR_BP_Pos 15U /*!< \brief ACTLR: BP Position */
542 #define ACTLR_BP_Msk (3UL << ACTLR_BP_Pos) /*!< \brief ACTLR: BP Mask */
543
544 #define ACTLR_DBWR_Pos 14U /*!< \brief ACTLR: DBWR Position */
545 #define ACTLR_DBWR_Msk (1UL << ACTLR_DBWR_Pos) /*!< \brief ACTLR: DBWR Mask */
546
547 #define ACTLR_DLFO_Pos 13U /*!< \brief ACTLR: DLFO Position */
548 #define ACTLR_DLFO_Msk (1UL << ACTLR_DLFO_Pos) /*!< \brief ACTLR: DLFO Mask */
549
550 #define ACTLR_ERPEG_Pos 12U /*!< \brief ACTLR: ERPEG Position */
551 #define ACTLR_ERPEG_Msk (1UL << ACTLR_ERPEG_Pos) /*!< \brief ACTLR: ERPEG Mask */
552
553 #define ACTLR_DNCH_Pos 11U /*!< \brief ACTLR: DNCH Position */
554 #define ACTLR_DNCH_Msk (1UL << ACTLR_DNCH_Pos) /*!< \brief ACTLR: DNCH Mask */
555
556 #define ACTLR_QOSEN_Pos 11U /*!< \brief ACTLR: QOSEN Position */
557 #define ACTLR_QOSEN_Msk (1UL << ACTLR_QOSEN_Pos) /*!< \brief ACTLR: QOSEN Mask */
558
559 #define ACTLR_FORA_Pos 10U /*!< \brief ACTLR: FORA Position */
560 #define ACTLR_FORA_Msk (1UL << ACTLR_FORA_Pos) /*!< \brief ACTLR: FORA Mask */
561
562 #define ACTLR_ITCMECEN_Pos 10U /*!< \brief ACTLR: ITCMECEN Position */
563 #define ACTLR_ITCMECEN_Msk (1UL << ACTLR_ITCMECEN_Pos) /*!< \brief ACTLR: ITCMECEN Mask */
564
565 #define ACTLR_FWT_Pos 9U /*!< \brief ACTLR: FWT Position */
566 #define ACTLR_FWT_Msk (1UL << ACTLR_FWT_Pos) /*!< \brief ACTLR: FWT Mask */
567
568 #define ACTLR_DTCMECEN_Pos 9U /*!< \brief ACTLR: DTCMECEN Position */
569 #define ACTLR_DTCMECEN_Msk (1UL << ACTLR_DTCMECEN_Pos) /*!< \brief ACTLR: DTCMECEN Mask */
570
571 #define ACTLR_FDSNS_Pos 8U /*!< \brief ACTLR: FDSNS Position */
572 #define ACTLR_FDSNS_Msk (1UL << ACTLR_FDSNS_Pos) /*!< \brief ACTLR: FDSNS Mask */
573
574 #define ACTLR_AOW_Pos 8U /*!< \brief ACTLR: AOW Position */
575 #define ACTLR_AOW_Msk (1UL << ACTLR_AOW_Pos) /*!< \brief ACTLR: AOW Mask */
576
577 #define ACTLR_SMOV_Pos 7U /*!< \brief ACTLR: SMOV Position */
578 #define ACTLR_SMOV_Msk (1UL << ACTLR_SMOV_Pos) /*!< \brief ACTLR: SMOV Mask */
579
580 #define ACTLR_DILS_Pos 6U /*!< \brief ACTLR: DILS Position */
581 #define ACTLR_DILS_Msk (1UL << ACTLR_DILS_Pos) /*!< \brief ACTLR: DILS Mask */
582
583 #define ACTLR_SMP_Pos 6U /*!< \brief ACTLR: SMP Position */
584 #define ACTLR_SMP_Msk (1UL << ACTLR_SMP_Pos) /*!< \brief ACTLR: SMP Mask */
585
586 #define ACTLR_CEC_Pos 3U /*!< \brief ACTLR: CEC Position */
587 #define ACTLR_CEC_Msk (7UL << ACTLR_CEC_Pos) /*!< \brief ACTLR: CEC Mask */
588
589 #define ACTLR_MRPEN_Pos 3U /*!< \brief ACTLR: MRPEN Position */
590 #define ACTLR_MRPEN_Msk (1UL << ACTLR_MRPEN_Pos) /*!< \brief ACTLR: MRPEN Mask */
591
592 #define ACTLR_B1TCMECEN_Pos 2U /*!< \brief ACTLR: B1TCMECEN Position */
593 #define ACTLR_B1TCMECEN_Msk (1UL << ACTLR_B1TCMECEN_Pos) /*!< \brief ACTLR: B1TCMECEN Mask */
594
595 #define ACTLR_B0TCMECEN_Pos 1U /*!< \brief ACTLR: B0TCMECEN Position */
596 #define ACTLR_B0TCMECEN_Msk (1UL << ACTLR_B0TCMECEN_Pos) /*!< \brief ACTLR: B0TCMECEN Mask */
597
598 #define ACTLR_ATCMECEN_Pos 0U /*!< \brief ACTLR: ATCMECEN Position */
599 #define ACTLR_ATCMECEN_Msk (1UL << ACTLR_ATCMECEN_Pos) /*!< \brief ACTLR: ATCMECEN Mask */
600
601 #define ACTLR_FW_Pos 0U /*!< \brief ACTLR: FW Position */
602 #define ACTLR_FW_Msk (1UL << ACTLR_FW_Pos) /*!< \brief ACTLR: FW Mask */
603
604 /* CP15 Register CPACR */
605 typedef union
606 {
607 struct
608 {
609 uint32_t CP0:2; /*!< \brief bit: 0..1 Access rights for coprocessor 0 */
610 uint32_t CP1:2; /*!< \brief bit: 2..3 Access rights for coprocessor 1 */
611 uint32_t CP2:2; /*!< \brief bit: 4..5 Access rights for coprocessor 2 */
612 uint32_t CP3:2; /*!< \brief bit: 6..7 Access rights for coprocessor 3 */
613 uint32_t CP4:2; /*!< \brief bit: 8..9 Access rights for coprocessor 4 */
614 uint32_t CP5:2; /*!< \brief bit:10..11 Access rights for coprocessor 5 */
615 uint32_t CP6:2; /*!< \brief bit:12..13 Access rights for coprocessor 6 */
616 uint32_t CP7:2; /*!< \brief bit:14..15 Access rights for coprocessor 7 */
617 uint32_t CP8:2; /*!< \brief bit:16..17 Access rights for coprocessor 8 */
618 uint32_t CP9:2; /*!< \brief bit:18..19 Access rights for coprocessor 9 */
619 uint32_t CP10:2; /*!< \brief bit:20..21 Access rights for coprocessor 10 */
620 uint32_t CP11:2; /*!< \brief bit:22..23 Access rights for coprocessor 11 */
621 uint32_t CP12:2; /*!< \brief bit:24..25 Access rights for coprocessor 11 */
622 uint32_t CP13:2; /*!< \brief bit:26..27 Access rights for coprocessor 11 */
623 uint32_t TRCDIS:1; /*!< \brief bit: 28 Disable CP14 access to trace registers */
624 RESERVED(0:1, uint32_t)
625 uint32_t D32DIS:1; /*!< \brief bit: 30 Disable use of registers D16-D31 of the VFP register file */
626 uint32_t ASEDIS:1; /*!< \brief bit: 31 Disable Advanced SIMD Functionality */
627 } b; /*!< \brief Structure used for bit access */
628 uint32_t w; /*!< \brief Type used for word access */
629 } CPACR_Type;
630
631 #define CPACR_ASEDIS_Pos 31U /*!< \brief CPACR: ASEDIS Position */
632 #define CPACR_ASEDIS_Msk (1UL << CPACR_ASEDIS_Pos) /*!< \brief CPACR: ASEDIS Mask */
633
634 #define CPACR_D32DIS_Pos 30U /*!< \brief CPACR: D32DIS Position */
635 #define CPACR_D32DIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
636
637 #define CPACR_TRCDIS_Pos 28U /*!< \brief CPACR: D32DIS Position */
638 #define CPACR_TRCDIS_Msk (1UL << CPACR_D32DIS_Pos) /*!< \brief CPACR: D32DIS Mask */
639
640 #define CPACR_CP_Pos_(n) (n*2U) /*!< \brief CPACR: CPn Position */
641 #define CPACR_CP_Msk_(n) (3UL << CPACR_CP_Pos_(n)) /*!< \brief CPACR: CPn Mask */
642
643 #define CPACR_CP_NA 0U /*!< \brief CPACR CPn field: Access denied. */
644 #define CPACR_CP_PL1 1U /*!< \brief CPACR CPn field: Accessible from PL1 only. */
645 #define CPACR_CP_FA 3U /*!< \brief CPACR CPn field: Full access. */
646
647 /* CP15 Register DFSR */
648 typedef union
649 {
650 struct
651 {
652 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
653 uint32_t Domain:4; /*!< \brief bit: 4.. 7 Fault on which domain */
654 RESERVED(0:1, uint32_t)
655 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
656 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
657 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
658 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
659 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
660 RESERVED(1:2, uint32_t)
661 uint32_t FnV:1; /*!< \brief bit: 16 FAR not valid */
662 RESERVED(2:15, uint32_t)
663 } s; /*!< \brief Structure used for bit access in short format */
664 struct
665 {
666 uint32_t STATUS:5; /*!< \brief bit: 0.. 5 Fault Status bits */
667 RESERVED(0:3, uint32_t)
668 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
669 RESERVED(1:1, uint32_t)
670 uint32_t WnR:1; /*!< \brief bit: 11 Write not Read bit */
671 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
672 uint32_t CM:1; /*!< \brief bit: 13 Cache maintenance fault */
673 RESERVED(2:2, uint32_t)
674 uint32_t FnV:1; /*!< \brief bit: 16 FAR not valid */
675 RESERVED(3:15, uint32_t)
676 } l; /*!< \brief Structure used for bit access in long format */
677 uint32_t w; /*!< \brief Type used for word access */
678 } DFSR_Type;
679
680 #define DFSR_FnV_Pos 16U /*!< \brief DFSR: FnV Position */
681 #define DFSR_FnV_Msk (1UL << DFSR_FnV_Pos) /*!< \brief DFSR: FnV Mask */
682
683 #define DFSR_CM_Pos 13U /*!< \brief DFSR: CM Position */
684 #define DFSR_CM_Msk (1UL << DFSR_CM_Pos) /*!< \brief DFSR: CM Mask */
685
686 #define DFSR_Ext_Pos 12U /*!< \brief DFSR: Ext Position */
687 #define DFSR_Ext_Msk (1UL << DFSR_Ext_Pos) /*!< \brief DFSR: Ext Mask */
688
689 #define DFSR_WnR_Pos 11U /*!< \brief DFSR: WnR Position */
690 #define DFSR_WnR_Msk (1UL << DFSR_WnR_Pos) /*!< \brief DFSR: WnR Mask */
691
692 #define DFSR_FS1_Pos 10U /*!< \brief DFSR: FS1 Position */
693 #define DFSR_FS1_Msk (1UL << DFSR_FS1_Pos) /*!< \brief DFSR: FS1 Mask */
694
695 #define DFSR_LPAE_Pos 9U /*!< \brief DFSR: LPAE Position */
696 #define DFSR_LPAE_Msk (1UL << DFSR_LPAE_Pos) /*!< \brief DFSR: LPAE Mask */
697
698 #define DFSR_Domain_Pos 4U /*!< \brief DFSR: Domain Position */
699 #define DFSR_Domain_Msk (0xFUL << DFSR_Domain_Pos) /*!< \brief DFSR: Domain Mask */
700
701 #define DFSR_FS0_Pos 0U /*!< \brief DFSR: FS0 Position */
702 #define DFSR_FS0_Msk (0xFUL << DFSR_FS0_Pos) /*!< \brief DFSR: FS0 Mask */
703
704 #define DFSR_STATUS_Pos 0U /*!< \brief DFSR: STATUS Position */
705 #define DFSR_STATUS_Msk (0x3FUL << DFSR_STATUS_Pos) /*!< \brief DFSR: STATUS Mask */
706
707 /* CP15 Register IFSR */
708 typedef union
709 {
710 struct
711 {
712 uint32_t FS0:4; /*!< \brief bit: 0.. 3 Fault Status bits bit 0-3 */
713 RESERVED(0:5, uint32_t)
714 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
715 uint32_t FS1:1; /*!< \brief bit: 10 Fault Status bits bit 4 */
716 RESERVED(1:1, uint32_t)
717 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
718 RESERVED(2:19, uint32_t)
719 } s; /*!< \brief Structure used for bit access in short format */
720 struct
721 {
722 uint32_t STATUS:6; /*!< \brief bit: 0.. 5 Fault Status bits */
723 RESERVED(0:3, uint32_t)
724 uint32_t LPAE:1; /*!< \brief bit: 9 Large Physical Address Extension */
725 RESERVED(1:2, uint32_t)
726 uint32_t ExT:1; /*!< \brief bit: 12 External abort type */
727 RESERVED(2:3, uint32_t)
728 uint32_t FnV:1; /*!< \brief bit: 16 FAR not valid */
729 RESERVED(3:15, uint32_t)
730 } l; /*!< \brief Structure used for bit access in long format */
731 uint32_t w; /*!< \brief Type used for word access */
732 } IFSR_Type;
733
734 #define IFSR_FnV_Pos 16U /*!< \brief IFSR: FnV Position */
735 #define IFSR_FnV_Msk (1UL << IFSR_FnV_Pos) /*!< \brief IFSR: FnV Mask */
736
737 #define IFSR_ExT_Pos 12U /*!< \brief IFSR: ExT Position */
738 #define IFSR_ExT_Msk (1UL << IFSR_ExT_Pos) /*!< \brief IFSR: ExT Mask */
739
740 #define IFSR_FS1_Pos 10U /*!< \brief IFSR: FS1 Position */
741 #define IFSR_FS1_Msk (1UL << IFSR_FS1_Pos) /*!< \brief IFSR: FS1 Mask */
742
743 #define IFSR_LPAE_Pos 9U /*!< \brief IFSR: LPAE Position */
744 #define IFSR_LPAE_Msk (0x1UL << IFSR_LPAE_Pos) /*!< \brief IFSR: LPAE Mask */
745
746 #define IFSR_FS0_Pos 0U /*!< \brief IFSR: FS0 Position */
747 #define IFSR_FS0_Msk (0xFUL << IFSR_FS0_Pos) /*!< \brief IFSR: FS0 Mask */
748
749 #define IFSR_STATUS_Pos 0U /*!< \brief IFSR: STATUS Position */
750 #define IFSR_STATUS_Msk (0x3FUL << IFSR_STATUS_Pos) /*!< \brief IFSR: STATUS Mask */
751
752 /* CP15 Register ISR */
753 typedef union
754 {
755 struct
756 {
757 RESERVED(0:6, uint32_t)
758 uint32_t F:1; /*!< \brief bit: 6 FIQ pending bit */
759 uint32_t I:1; /*!< \brief bit: 7 IRQ pending bit */
760 uint32_t A:1; /*!< \brief bit: 8 External abort pending bit */
761 RESERVED(1:23, uint32_t)
762 } b; /*!< \brief Structure used for bit access */
763 uint32_t w; /*!< \brief Type used for word access */
764 } ISR_Type;
765
766 #define ISR_A_Pos 13U /*!< \brief ISR: A Position */
767 #define ISR_A_Msk (1UL << ISR_A_Pos) /*!< \brief ISR: A Mask */
768
769 #define ISR_I_Pos 12U /*!< \brief ISR: I Position */
770 #define ISR_I_Msk (1UL << ISR_I_Pos) /*!< \brief ISR: I Mask */
771
772 #define ISR_F_Pos 11U /*!< \brief ISR: F Position */
773 #define ISR_F_Msk (1UL << ISR_F_Pos) /*!< \brief ISR: F Mask */
774
775 /* DACR Register */
776 #define DACR_D_Pos_(n) (2U*n) /*!< \brief DACR: Dn Position */
777 #define DACR_D_Msk_(n) (3UL << DACR_D_Pos_(n)) /*!< \brief DACR: Dn Mask */
778 #define DACR_Dn_NOACCESS 0U /*!< \brief DACR Dn field: No access */
779 #define DACR_Dn_CLIENT 1U /*!< \brief DACR Dn field: Client */
780 #define DACR_Dn_MANAGER 3U /*!< \brief DACR Dn field: Manager */
781
782 /**
783 \brief Mask and shift a bit field value for use in a register bit range.
784 \param [in] field Name of the register bit field.
785 \param [in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
786 \return Masked and shifted value.
787 */
788 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
789
790 /**
791 \brief Mask and shift a register value to extract a bit filed value.
792 \param [in] field Name of the register bit field.
793 \param [in] value Value of register. This parameter is interpreted as an uint32_t type.
794 \return Masked and shifted bit field value.
795 */
796 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
797
798 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
799
800 /** \brief Structure type to access the Generic Interrupt Controller Distributor (GICD)
801 */
802 typedef struct
803 {
804 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) Distributor Control Register */
805 __IM uint32_t TYPER; /*!< \brief Offset: 0x004 (R/ ) Interrupt Controller Type Register */
806 __IM uint32_t IIDR; /*!< \brief Offset: 0x008 (R/ ) Distributor Implementer Identification Register */
807 RESERVED(0, uint32_t)
808 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x010 (R/W) Error Reporting Status Register, optional */
809 RESERVED(1[11], uint32_t)
810 __OM uint32_t SETSPI_NSR; /*!< \brief Offset: 0x040 ( /W) Set SPI Register */
811 RESERVED(2, uint32_t)
812 __OM uint32_t CLRSPI_NSR; /*!< \brief Offset: 0x048 ( /W) Clear SPI Register */
813 RESERVED(3, uint32_t)
814 __OM uint32_t SETSPI_SR; /*!< \brief Offset: 0x050 ( /W) Set SPI, Secure Register */
815 RESERVED(4, uint32_t)
816 __OM uint32_t CLRSPI_SR; /*!< \brief Offset: 0x058 ( /W) Clear SPI, Secure Register */
817 RESERVED(5[9], uint32_t)
818 __IOM uint32_t IGROUPR[32]; /*!< \brief Offset: 0x080 (R/W) Interrupt Group Registers */
819 __IOM uint32_t ISENABLER[32]; /*!< \brief Offset: 0x100 (R/W) Interrupt Set-Enable Registers */
820 __IOM uint32_t ICENABLER[32]; /*!< \brief Offset: 0x180 (R/W) Interrupt Clear-Enable Registers */
821 __IOM uint32_t ISPENDR[32]; /*!< \brief Offset: 0x200 (R/W) Interrupt Set-Pending Registers */
822 __IOM uint32_t ICPENDR[32]; /*!< \brief Offset: 0x280 (R/W) Interrupt Clear-Pending Registers */
823 __IOM uint32_t ISACTIVER[32]; /*!< \brief Offset: 0x300 (R/W) Interrupt Set-Active Registers */
824 __IOM uint32_t ICACTIVER[32]; /*!< \brief Offset: 0x380 (R/W) Interrupt Clear-Active Registers */
825 __IOM uint32_t IPRIORITYR[255]; /*!< \brief Offset: 0x400 (R/W) Interrupt Priority Registers */
826 RESERVED(6, uint32_t)
827 __IOM uint32_t ITARGETSR[255]; /*!< \brief Offset: 0x800 (R/W) Interrupt Targets Registers */
828 RESERVED(7, uint32_t)
829 __IOM uint32_t ICFGR[64]; /*!< \brief Offset: 0xC00 (R/W) Interrupt Configuration Registers */
830 __IOM uint32_t IGRPMODR[32]; /*!< \brief Offset: 0xD00 (R/W) Interrupt Group Modifier Registers */
831 RESERVED(8[32], uint32_t)
832 __IOM uint32_t NSACR[64]; /*!< \brief Offset: 0xE00 (R/W) Non-secure Access Control Registers */
833 __OM uint32_t SGIR; /*!< \brief Offset: 0xF00 ( /W) Software Generated Interrupt Register */
834 RESERVED(9[3], uint32_t)
835 __IOM uint32_t CPENDSGIR[4]; /*!< \brief Offset: 0xF10 (R/W) SGI Clear-Pending Registers */
836 __IOM uint32_t SPENDSGIR[4]; /*!< \brief Offset: 0xF20 (R/W) SGI Set-Pending Registers */
837 RESERVED(10[5236], uint32_t)
838 __IOM uint64_t IROUTER[988]; /*!< \brief Offset: 0x6100(R/W) Interrupt Routing Registers */
839 } GICDistributor_Type;
840
841 #define GICDistributor ((GICDistributor_Type *) GIC_DISTRIBUTOR_BASE ) /*!< \brief GIC Distributor register set access pointer */
842
843 /** \brief Structure type to access the Generic Interrupt Controller Interface (GICC)
844 */
845 typedef struct
846 {
847 __IOM uint32_t CTLR; /*!< \brief Offset: 0x000 (R/W) CPU Interface Control Register */
848 __IOM uint32_t PMR; /*!< \brief Offset: 0x004 (R/W) Interrupt Priority Mask Register */
849 __IOM uint32_t BPR; /*!< \brief Offset: 0x008 (R/W) Binary Point Register */
850 __IM uint32_t IAR; /*!< \brief Offset: 0x00C (R/ ) Interrupt Acknowledge Register */
851 __OM uint32_t EOIR; /*!< \brief Offset: 0x010 ( /W) End Of Interrupt Register */
852 __IM uint32_t RPR; /*!< \brief Offset: 0x014 (R/ ) Running Priority Register */
853 __IM uint32_t HPPIR; /*!< \brief Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register */
854 __IOM uint32_t ABPR; /*!< \brief Offset: 0x01C (R/W) Aliased Binary Point Register */
855 __IM uint32_t AIAR; /*!< \brief Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register */
856 __OM uint32_t AEOIR; /*!< \brief Offset: 0x024 ( /W) Aliased End Of Interrupt Register */
857 __IM uint32_t AHPPIR; /*!< \brief Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register */
858 __IOM uint32_t STATUSR; /*!< \brief Offset: 0x02C (R/W) Error Reporting Status Register, optional */
859 RESERVED(1[40], uint32_t)
860 __IOM uint32_t APR[4]; /*!< \brief Offset: 0x0D0 (R/W) Active Priority Register */
861 __IOM uint32_t NSAPR[4]; /*!< \brief Offset: 0x0E0 (R/W) Non-secure Active Priority Register */
862 RESERVED(2[3], uint32_t)
863 __IM uint32_t IIDR; /*!< \brief Offset: 0x0FC (R/ ) CPU Interface Identification Register */
864 RESERVED(3[960], uint32_t)
865 __OM uint32_t DIR; /*!< \brief Offset: 0x1000( /W) Deactivate Interrupt Register */
866 } GICInterface_Type;
867
868 #define GICInterface ((GICInterface_Type *) GIC_INTERFACE_BASE ) /*!< \brief GIC Interface register set access pointer */
869 #endif
870
871 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
872 #if ((__CORTEX_R == 7U) || (__CORTEX_R == 8U)) || defined(DOXYGEN)
873 /** \brief Structure type to access the Private Timer
874 */
875 typedef struct
876 {
877 __IOM uint32_t LOAD; //!< \brief Offset: 0x000 (R/W) Private Timer Load Register
878 __IOM uint32_t COUNTER; //!< \brief Offset: 0x004 (R/W) Private Timer Counter Register
879 __IOM uint32_t CONTROL; //!< \brief Offset: 0x008 (R/W) Private Timer Control Register
880 __IOM uint32_t ISR; //!< \brief Offset: 0x00C (R/W) Private Timer Interrupt Status Register
881 RESERVED(0[4], uint32_t)
882 __IOM uint32_t WLOAD; //!< \brief Offset: 0x020 (R/W) Watchdog Load Register
883 __IOM uint32_t WCOUNTER; //!< \brief Offset: 0x024 (R/W) Watchdog Counter Register
884 __IOM uint32_t WCONTROL; //!< \brief Offset: 0x028 (R/W) Watchdog Control Register
885 __IOM uint32_t WISR; //!< \brief Offset: 0x02C (R/W) Watchdog Interrupt Status Register
886 __IOM uint32_t WRESET; //!< \brief Offset: 0x030 (R/W) Watchdog Reset Status Register
887 __OM uint32_t WDISABLE; //!< \brief Offset: 0x034 ( /W) Watchdog Disable Register
888 } Timer_Type;
889 #define PTIM ((Timer_Type *) TIMER_BASE ) /*!< \brief Timer register struct */
890 #endif
891 #endif
892
893 /*******************************************************************************
894 * Hardware Abstraction Layer
895 Core Function Interface contains:
896 - L1 Cache Functions
897 - PL1 Timer Functions
898 - GIC Functions
899 - MMU Functions
900 ******************************************************************************/
901
902 /* ########################## L1 Cache functions ################################# */
903
904 /** \brief Enable Caches by setting I and C bits in SCTLR register.
905 */
L1C_EnableCaches(void)906 __STATIC_FORCEINLINE void L1C_EnableCaches(void) {
907 __set_SCTLR( __get_SCTLR() | SCTLR_I_Msk | SCTLR_C_Msk);
908 __ISB();
909 }
910
911 /** \brief Disable Caches by clearing I and C bits in SCTLR register.
912 */
L1C_DisableCaches(void)913 __STATIC_FORCEINLINE void L1C_DisableCaches(void) {
914 __set_SCTLR( __get_SCTLR() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk));
915 __ISB();
916 }
917
918 /** \brief Enable Branch Prediction by setting Z bit in SCTLR register.
919 */
L1C_EnableBTAC(void)920 __STATIC_FORCEINLINE void L1C_EnableBTAC(void) {
921 __set_SCTLR( __get_SCTLR() | SCTLR_Z_Msk);
922 __ISB();
923 }
924
925 /** \brief Disable Branch Prediction by clearing Z bit in SCTLR register.
926 */
L1C_DisableBTAC(void)927 __STATIC_FORCEINLINE void L1C_DisableBTAC(void) {
928 __set_SCTLR( __get_SCTLR() & (~SCTLR_Z_Msk));
929 __ISB();
930 }
931
932 /** \brief Invalidate entire branch predictor array
933 */
L1C_InvalidateBTAC(void)934 __STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) {
935 __set_BPIALL(0);
936 __DSB(); //ensure completion of the invalidation
937 __ISB(); //ensure instruction fetch path sees new state
938 }
939
940 /** \brief Invalidate the whole instruction cache
941 */
L1C_InvalidateICacheAll(void)942 __STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) {
943 __set_ICIALLU(0);
944 __DSB(); //ensure completion of the invalidation
945 __ISB(); //ensure instruction fetch path sees new I cache state
946 }
947
948 /** \brief Clean data cache line by address.
949 * \param [in] va Pointer to data to clear the cache for.
950 */
L1C_CleanDCacheMVA(void * va)951 __STATIC_FORCEINLINE void L1C_CleanDCacheMVA(void *va) {
952 __set_DCCMVAC((uint32_t)va);
953 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
954 }
955
956 /** \brief Invalidate data cache line by address.
957 * \param [in] va Pointer to data to invalidate the cache for.
958 */
L1C_InvalidateDCacheMVA(void * va)959 __STATIC_FORCEINLINE void L1C_InvalidateDCacheMVA(void *va) {
960 __set_DCIMVAC((uint32_t)va);
961 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
962 }
963
964 /** \brief Clean and Invalidate data cache by address.
965 * \param [in] va Pointer to data to invalidate the cache for.
966 */
L1C_CleanInvalidateDCacheMVA(void * va)967 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheMVA(void *va) {
968 __set_DCCIMVAC((uint32_t)va);
969 __DMB(); //ensure the ordering of data cache maintenance operations and their effects
970 }
971
972 /** \brief Calculate log2 rounded up
973 * - log(0) => 0
974 * - log(1) => 0
975 * - log(2) => 1
976 * - log(3) => 2
977 * - log(4) => 2
978 * - log(5) => 3
979 * : :
980 * - log(16) => 4
981 * - log(32) => 5
982 * : :
983 * \param [in] n input value parameter
984 * \return log2(n)
985 */
__log2_up(uint32_t n)986 __STATIC_FORCEINLINE uint8_t __log2_up(uint32_t n)
987 {
988 if (n < 2U) {
989 return 0U;
990 }
991 uint8_t log = 0U;
992 uint32_t t = n;
993 while(t > 1U)
994 {
995 log++;
996 t >>= 1U;
997 }
998 if (n & 1U) { log++; }
999 return log;
1000 }
1001
1002 /** \brief Apply cache maintenance to given cache level.
1003 * \param [in] level cache level to be maintained
1004 * \param [in] maint 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1005 */
__L1C_MaintainDCacheSetWay(uint32_t level,uint32_t maint)1006 __STATIC_FORCEINLINE void __L1C_MaintainDCacheSetWay(uint32_t level, uint32_t maint)
1007 {
1008 uint32_t Dummy;
1009 uint32_t ccsidr;
1010 uint32_t num_sets;
1011 uint32_t num_ways;
1012 uint32_t shift_way;
1013 uint32_t log2_linesize;
1014 int32_t log2_num_ways;
1015
1016 Dummy = level << 1U;
1017 /* set csselr, select ccsidr register */
1018 __set_CSSELR(Dummy);
1019 /* get current ccsidr register */
1020 ccsidr = __get_CCSIDR();
1021 num_sets = ((ccsidr & 0x0FFFE000U) >> 13U) + 1U;
1022 num_ways = ((ccsidr & 0x00001FF8U) >> 3U) + 1U;
1023 log2_linesize = (ccsidr & 0x00000007U) + 2U + 2U;
1024 log2_num_ways = __log2_up(num_ways);
1025 if ((log2_num_ways < 0) || (log2_num_ways > 32)) {
1026 return; // FATAL ERROR
1027 }
1028 shift_way = 32U - (uint32_t)log2_num_ways;
1029 for(int32_t way = num_ways-1; way >= 0; way--)
1030 {
1031 for(int32_t set = num_sets-1; set >= 0; set--)
1032 {
1033 Dummy = (level << 1U) | (((uint32_t)set) << log2_linesize) | (((uint32_t)way) << shift_way);
1034 switch (maint)
1035 {
1036 case 0U: __set_DCISW(Dummy); break;
1037 case 1U: __set_DCCSW(Dummy); break;
1038 default: __set_DCCISW(Dummy); break;
1039 }
1040 }
1041 }
1042 __DMB();
1043 }
1044
1045 /** \brief Clean and Invalidate the entire data or unified cache
1046 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
1047 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1048 */
L1C_CleanInvalidateCache(uint32_t op)1049 __STATIC_FORCEINLINE void L1C_CleanInvalidateCache(uint32_t op) {
1050 uint32_t clidr;
1051 uint32_t cache_type;
1052 clidr = __get_CLIDR();
1053 for(uint32_t i = 0U; i<7U; i++)
1054 {
1055 cache_type = (clidr >> i*3U) & 0x7UL;
1056 if ((cache_type >= 2U) && (cache_type <= 4U))
1057 {
1058 __L1C_MaintainDCacheSetWay(i, op);
1059 }
1060 }
1061 }
1062
1063 /** \brief Clean and Invalidate the entire data or unified cache
1064 * Generic mechanism for cleaning/invalidating the entire data or unified cache to the point of coherency
1065 * \param [in] op 0 - invalidate, 1 - clean, otherwise - invalidate and clean
1066 * \deprecated Use generic L1C_CleanInvalidateCache instead.
1067 */
1068 CMSIS_DEPRECATED
__L1C_CleanInvalidateCache(uint32_t op)1069 __STATIC_FORCEINLINE void __L1C_CleanInvalidateCache(uint32_t op) {
1070 L1C_CleanInvalidateCache(op);
1071 }
1072
1073 /** \brief Invalidate the whole data cache.
1074 */
L1C_InvalidateDCacheAll(void)1075 __STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) {
1076 L1C_CleanInvalidateCache(0);
1077 }
1078
1079 /** \brief Clean the whole data cache.
1080 */
L1C_CleanDCacheAll(void)1081 __STATIC_FORCEINLINE void L1C_CleanDCacheAll(void) {
1082 L1C_CleanInvalidateCache(1);
1083 }
1084
1085 /** \brief Clean and invalidate the whole data cache.
1086 */
L1C_CleanInvalidateDCacheAll(void)1087 __STATIC_FORCEINLINE void L1C_CleanInvalidateDCacheAll(void) {
1088 L1C_CleanInvalidateCache(2);
1089 }
1090
1091 /* ########################## GIC functions ###################################### */
1092 #if (__GIC_PRESENT == 1U) || defined(DOXYGEN)
1093
1094 /** \brief Enable the interrupt distributor using the GIC's CTLR register.
1095 */
GIC_EnableDistributor(void)1096 __STATIC_INLINE void GIC_EnableDistributor(void)
1097 {
1098 GICDistributor->CTLR |= 1U;
1099 }
1100
1101 /** \brief Disable the interrupt distributor using the GIC's CTLR register.
1102 */
GIC_DisableDistributor(void)1103 __STATIC_INLINE void GIC_DisableDistributor(void)
1104 {
1105 GICDistributor->CTLR &=~1U;
1106 }
1107
1108 /** \brief Read the GIC's TYPER register.
1109 * \return GICDistributor_Type::TYPER
1110 */
GIC_DistributorInfo(void)1111 __STATIC_INLINE uint32_t GIC_DistributorInfo(void)
1112 {
1113 return (GICDistributor->TYPER);
1114 }
1115
1116 /** \brief Reads the GIC's IIDR register.
1117 * \return GICDistributor_Type::IIDR
1118 */
GIC_DistributorImplementer(void)1119 __STATIC_INLINE uint32_t GIC_DistributorImplementer(void)
1120 {
1121 return (GICDistributor->IIDR);
1122 }
1123
1124 /** \brief Sets the GIC's ITARGETSR register for the given interrupt.
1125 * \param [in] IRQn Interrupt to be configured.
1126 * \param [in] cpu_target CPU interfaces to assign this interrupt to.
1127 */
GIC_SetTarget(IRQn_Type IRQn,uint32_t cpu_target)1128 __STATIC_INLINE void GIC_SetTarget(IRQn_Type IRQn, uint32_t cpu_target)
1129 {
1130 uint32_t mask = GICDistributor->ITARGETSR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
1131 GICDistributor->ITARGETSR[IRQn / 4U] = mask | ((cpu_target & 0xFFUL) << ((IRQn % 4U) * 8U));
1132 }
1133
1134 /** \brief Read the GIC's ITARGETSR register.
1135 * \param [in] IRQn Interrupt to acquire the configuration for.
1136 * \return GICDistributor_Type::ITARGETSR
1137 */
GIC_GetTarget(IRQn_Type IRQn)1138 __STATIC_INLINE uint32_t GIC_GetTarget(IRQn_Type IRQn)
1139 {
1140 return (GICDistributor->ITARGETSR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1141 }
1142
1143 /** \brief Enable the CPU's interrupt interface.
1144 */
GIC_EnableInterface(void)1145 __STATIC_INLINE void GIC_EnableInterface(void)
1146 {
1147 GICInterface->CTLR |= 1U; //enable interface
1148 }
1149
1150 /** \brief Disable the CPU's interrupt interface.
1151 */
GIC_DisableInterface(void)1152 __STATIC_INLINE void GIC_DisableInterface(void)
1153 {
1154 GICInterface->CTLR &=~1U; //disable distributor
1155 }
1156
1157 /** \brief Read the CPU's IAR register.
1158 * \return GICInterface_Type::IAR
1159 */
GIC_AcknowledgePending(void)1160 __STATIC_INLINE IRQn_Type GIC_AcknowledgePending(void)
1161 {
1162 return (IRQn_Type)(GICInterface->IAR);
1163 }
1164
1165 /** \brief Writes the given interrupt number to the CPU's EOIR register.
1166 * \param [in] IRQn The interrupt to be signaled as finished.
1167 */
GIC_EndInterrupt(IRQn_Type IRQn)1168 __STATIC_INLINE void GIC_EndInterrupt(IRQn_Type IRQn)
1169 {
1170 GICInterface->EOIR = IRQn;
1171 }
1172
1173 /** \brief Enables the given interrupt using GIC's ISENABLER register.
1174 * \param [in] IRQn The interrupt to be enabled.
1175 */
GIC_EnableIRQ(IRQn_Type IRQn)1176 __STATIC_INLINE void GIC_EnableIRQ(IRQn_Type IRQn)
1177 {
1178 GICDistributor->ISENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
1179 }
1180
1181 /** \brief Get interrupt enable status using GIC's ISENABLER register.
1182 * \param [in] IRQn The interrupt to be queried.
1183 * \return 0 - interrupt is not enabled, 1 - interrupt is enabled.
1184 */
GIC_GetEnableIRQ(IRQn_Type IRQn)1185 __STATIC_INLINE uint32_t GIC_GetEnableIRQ(IRQn_Type IRQn)
1186 {
1187 return (GICDistributor->ISENABLER[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1188 }
1189
1190 /** \brief Disables the given interrupt using GIC's ICENABLER register.
1191 * \param [in] IRQn The interrupt to be disabled.
1192 */
GIC_DisableIRQ(IRQn_Type IRQn)1193 __STATIC_INLINE void GIC_DisableIRQ(IRQn_Type IRQn)
1194 {
1195 GICDistributor->ICENABLER[IRQn / 32U] = 1U << (IRQn % 32U);
1196 }
1197
1198 /** \brief Get interrupt pending status from GIC's ISPENDR register.
1199 * \param [in] IRQn The interrupt to be queried.
1200 * \return 0 - interrupt is not pending, 1 - interrupt is pendig.
1201 */
GIC_GetPendingIRQ(IRQn_Type IRQn)1202 __STATIC_INLINE uint32_t GIC_GetPendingIRQ(IRQn_Type IRQn)
1203 {
1204 uint32_t pend;
1205
1206 if (IRQn >= 16U) {
1207 pend = (GICDistributor->ISPENDR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1208 } else {
1209 // INTID 0-15 Software Generated Interrupt
1210 pend = (GICDistributor->SPENDSGIR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1211 // No CPU identification offered
1212 if (pend != 0U) {
1213 pend = 1U;
1214 } else {
1215 pend = 0U;
1216 }
1217 }
1218
1219 return (pend);
1220 }
1221
1222 /** \brief Sets the given interrupt as pending using GIC's ISPENDR register.
1223 * \param [in] IRQn The interrupt to be enabled.
1224 */
GIC_SetPendingIRQ(IRQn_Type IRQn)1225 __STATIC_INLINE void GIC_SetPendingIRQ(IRQn_Type IRQn)
1226 {
1227 if (IRQn >= 16U) {
1228 GICDistributor->ISPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
1229 } else {
1230 // INTID 0-15 Software Generated Interrupt
1231 GICDistributor->SPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
1232 }
1233 }
1234
1235 /** \brief Clears the given interrupt from being pending using GIC's ICPENDR register.
1236 * \param [in] IRQn The interrupt to be enabled.
1237 */
GIC_ClearPendingIRQ(IRQn_Type IRQn)1238 __STATIC_INLINE void GIC_ClearPendingIRQ(IRQn_Type IRQn)
1239 {
1240 if (IRQn >= 16U) {
1241 GICDistributor->ICPENDR[IRQn / 32U] = 1U << (IRQn % 32U);
1242 } else {
1243 // INTID 0-15 Software Generated Interrupt
1244 GICDistributor->CPENDSGIR[IRQn / 4U] = 1U << ((IRQn % 4U) * 8U);
1245 }
1246 }
1247
1248 /** \brief Sets the interrupt configuration using GIC's ICFGR register.
1249 * \param [in] IRQn The interrupt to be configured.
1250 * \param [in] int_config Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
1251 * Bit 1: 0 - level sensitive, 1 - edge triggered
1252 */
GIC_SetConfiguration(IRQn_Type IRQn,uint32_t int_config)1253 __STATIC_INLINE void GIC_SetConfiguration(IRQn_Type IRQn, uint32_t int_config)
1254 {
1255 uint32_t icfgr = GICDistributor->ICFGR[IRQn / 16U];
1256 uint32_t shift = (IRQn % 16U) << 1U;
1257
1258 icfgr &= (~(3U << shift));
1259 icfgr |= ( int_config << shift);
1260
1261 GICDistributor->ICFGR[IRQn / 16U] = icfgr;
1262 }
1263
1264 /** \brief Get the interrupt configuration from the GIC's ICFGR register.
1265 * \param [in] IRQn Interrupt to acquire the configuration for.
1266 * \return Int_config field value. Bit 0: Reserved (0 - N-N model, 1 - 1-N model for some GIC before v1)
1267 * Bit 1: 0 - level sensitive, 1 - edge triggered
1268 */
GIC_GetConfiguration(IRQn_Type IRQn)1269 __STATIC_INLINE uint32_t GIC_GetConfiguration(IRQn_Type IRQn)
1270 {
1271 return (GICDistributor->ICFGR[IRQn / 16U] >> ((IRQn % 16U) >> 1U));
1272 }
1273
1274 /** \brief Set the priority for the given interrupt in the GIC's IPRIORITYR register.
1275 * \param [in] IRQn The interrupt to be configured.
1276 * \param [in] priority The priority for the interrupt, lower values denote higher priorities.
1277 */
GIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1278 __STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1279 {
1280 uint32_t mask = GICDistributor->IPRIORITYR[IRQn / 4U] & ~(0xFFUL << ((IRQn % 4U) * 8U));
1281 GICDistributor->IPRIORITYR[IRQn / 4U] = mask | ((priority & 0xFFUL) << ((IRQn % 4U) * 8U));
1282 }
1283
1284 /** \brief Read the current interrupt priority from GIC's IPRIORITYR register.
1285 * \param [in] IRQn The interrupt to be queried.
1286 */
GIC_GetPriority(IRQn_Type IRQn)1287 __STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)
1288 {
1289 return (GICDistributor->IPRIORITYR[IRQn / 4U] >> ((IRQn % 4U) * 8U)) & 0xFFUL;
1290 }
1291
1292 /** \brief Set the interrupt priority mask using CPU's PMR register.
1293 * \param [in] priority Priority mask to be set.
1294 */
GIC_SetInterfacePriorityMask(uint32_t priority)1295 __STATIC_INLINE void GIC_SetInterfacePriorityMask(uint32_t priority)
1296 {
1297 GICInterface->PMR = priority & 0xFFUL; //set priority mask
1298 }
1299
1300 /** \brief Read the current interrupt priority mask from CPU's PMR register.
1301 * \result GICInterface_Type::PMR
1302 */
GIC_GetInterfacePriorityMask(void)1303 __STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask(void)
1304 {
1305 return GICInterface->PMR;
1306 }
1307
1308 /** \brief Configures the group priority and subpriority split point using CPU's BPR register.
1309 * \param [in] binary_point Amount of bits used as subpriority.
1310 */
GIC_SetBinaryPoint(uint32_t binary_point)1311 __STATIC_INLINE void GIC_SetBinaryPoint(uint32_t binary_point)
1312 {
1313 GICInterface->BPR = binary_point & 7U; //set binary point
1314 }
1315
1316 /** \brief Read the current group priority and subpriority split point from CPU's BPR register.
1317 * \return GICInterface_Type::BPR
1318 */
GIC_GetBinaryPoint(void)1319 __STATIC_INLINE uint32_t GIC_GetBinaryPoint(void)
1320 {
1321 return GICInterface->BPR;
1322 }
1323
1324 /** \brief Get the status for a given interrupt.
1325 * \param [in] IRQn The interrupt to get status for.
1326 * \return 0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active
1327 */
GIC_GetIRQStatus(IRQn_Type IRQn)1328 __STATIC_INLINE uint32_t GIC_GetIRQStatus(IRQn_Type IRQn)
1329 {
1330 uint32_t pending, active;
1331
1332 active = ((GICDistributor->ISACTIVER[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
1333 pending = ((GICDistributor->ISPENDR[IRQn / 32U]) >> (IRQn % 32U)) & 1UL;
1334
1335 return ((active<<1U) | pending);
1336 }
1337
1338 /** \brief Generate a software interrupt using GIC's SGIR register.
1339 * \param [in] IRQn Software interrupt to be generated.
1340 * \param [in] target_list List of CPUs the software interrupt should be forwarded to.
1341 * \param [in] filter_list Filter to be applied to determine interrupt receivers.
1342 */
GIC_SendSGI(IRQn_Type IRQn,uint32_t target_list,uint32_t filter_list)1343 __STATIC_INLINE void GIC_SendSGI(IRQn_Type IRQn, uint32_t target_list, uint32_t filter_list)
1344 {
1345 GICDistributor->SGIR = ((filter_list & 3U) << 24U) | ((target_list & 0xFFUL) << 16U) | (IRQn & 0x0FUL);
1346 }
1347
1348 /** \brief Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.
1349 * \return GICInterface_Type::HPPIR
1350 */
GIC_GetHighPendingIRQ(void)1351 __STATIC_INLINE uint32_t GIC_GetHighPendingIRQ(void)
1352 {
1353 return GICInterface->HPPIR;
1354 }
1355
1356 /** \brief Provides information about the implementer and revision of the CPU interface.
1357 * \return GICInterface_Type::IIDR
1358 */
GIC_GetInterfaceId(void)1359 __STATIC_INLINE uint32_t GIC_GetInterfaceId(void)
1360 {
1361 return GICInterface->IIDR;
1362 }
1363
1364 /** \brief Set the interrupt group from the GIC's IGROUPR register.
1365 * \param [in] IRQn The interrupt to be queried.
1366 * \param [in] group Interrupt group number: 0 - Group 0, 1 - Group 1
1367 */
GIC_SetGroup(IRQn_Type IRQn,uint32_t group)1368 __STATIC_INLINE void GIC_SetGroup(IRQn_Type IRQn, uint32_t group)
1369 {
1370 uint32_t igroupr = GICDistributor->IGROUPR[IRQn / 32U];
1371 uint32_t shift = (IRQn % 32U);
1372
1373 igroupr &= (~(1U << shift));
1374 igroupr |= ( (group & 1U) << shift);
1375
1376 GICDistributor->IGROUPR[IRQn / 32U] = igroupr;
1377 }
1378 #define GIC_SetSecurity GIC_SetGroup
1379
1380 /** \brief Get the interrupt group from the GIC's IGROUPR register.
1381 * \param [in] IRQn The interrupt to be queried.
1382 * \return 0 - Group 0, 1 - Group 1
1383 */
GIC_GetGroup(IRQn_Type IRQn)1384 __STATIC_INLINE uint32_t GIC_GetGroup(IRQn_Type IRQn)
1385 {
1386 return (GICDistributor->IGROUPR[IRQn / 32U] >> (IRQn % 32U)) & 1UL;
1387 }
1388 #define GIC_GetSecurity GIC_GetGroup
1389
1390 /** \brief Initialize the interrupt distributor.
1391 */
GIC_DistInit(void)1392 __STATIC_INLINE void GIC_DistInit(void)
1393 {
1394 uint32_t i;
1395 uint32_t num_irq = 0U;
1396 uint32_t priority_field;
1397
1398 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
1399 //configuring all of the interrupts as Secure.
1400
1401 //Disable interrupt forwarding
1402 GIC_DisableDistributor();
1403 //Get the maximum number of interrupts that the GIC supports
1404 num_irq = 32U * ((GIC_DistributorInfo() & 0x1FU) + 1U);
1405
1406 /* Priority level is implementation defined.
1407 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
1408 priority field and read back the value stored.*/
1409 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
1410 priority_field = GIC_GetPriority((IRQn_Type)0U);
1411
1412 for (i = 32U; i < num_irq; i++)
1413 {
1414 //Disable the SPI interrupt
1415 GIC_DisableIRQ((IRQn_Type)i);
1416 //Set level-sensitive (and N-N model)
1417 GIC_SetConfiguration((IRQn_Type)i, 0U);
1418 //Set priority
1419 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
1420 //Set target list to CPU0
1421 GIC_SetTarget((IRQn_Type)i, 1U);
1422 }
1423 //Enable distributor
1424 GIC_EnableDistributor();
1425 }
1426
1427 /** \brief Initialize the CPU's interrupt interface
1428 */
GIC_CPUInterfaceInit(void)1429 __STATIC_INLINE void GIC_CPUInterfaceInit(void)
1430 {
1431 uint32_t i;
1432 uint32_t priority_field;
1433
1434 //A reset sets all bits in the IGROUPRs corresponding to the SPIs to 0,
1435 //configuring all of the interrupts as Secure.
1436
1437 //Disable interrupt forwarding
1438 GIC_DisableInterface();
1439
1440 /* Priority level is implementation defined.
1441 To determine the number of priority bits implemented write 0xFF to an IPRIORITYR
1442 priority field and read back the value stored.*/
1443 GIC_SetPriority((IRQn_Type)0U, 0xFFU);
1444 priority_field = GIC_GetPriority((IRQn_Type)0U);
1445
1446 //SGI and PPI
1447 for (i = 0U; i < 32U; i++)
1448 {
1449 if(i > 15U) {
1450 //Set level-sensitive (and N-N model) for PPI
1451 GIC_SetConfiguration((IRQn_Type)i, 0U);
1452 }
1453 //Disable SGI and PPI interrupts
1454 GIC_DisableIRQ((IRQn_Type)i);
1455 //Set priority
1456 GIC_SetPriority((IRQn_Type)i, priority_field/2U);
1457 }
1458 //Enable interface
1459 GIC_EnableInterface();
1460 //Set binary point to 0
1461 GIC_SetBinaryPoint(0U);
1462 //Set priority mask
1463 GIC_SetInterfacePriorityMask(0xFFU);
1464 }
1465
1466 /** \brief Initialize and enable the GIC
1467 */
GIC_Enable(void)1468 __STATIC_INLINE void GIC_Enable(void)
1469 {
1470 GIC_DistInit();
1471 GIC_CPUInterfaceInit(); //per CPU
1472 }
1473 #endif
1474
1475 /* ########################## Generic Timer functions ############################ */
1476 #if (__TIM_PRESENT == 1U) || defined(DOXYGEN)
1477
1478 /* PL1 Physical Timer */
1479 #if (__CORTEX_R == 52U) || defined(DOXYGEN)
1480
1481 /** \brief Physical Timer Control register */
1482 typedef union
1483 {
1484 struct
1485 {
1486 uint32_t ENABLE:1; /*!< \brief bit: 0 Enables the timer. */
1487 uint32_t IMASK:1; /*!< \brief bit: 1 Timer output signal mask bit. */
1488 uint32_t ISTATUS:1; /*!< \brief bit: 2 The status of the timer. */
1489 RESERVED(0:29, uint32_t)
1490 } b; /*!< \brief Structure used for bit access */
1491 uint32_t w; /*!< \brief Type used for word access */
1492 } CNTP_CTL_Type;
1493
1494 /** \brief Configures the frequency the timer shall run at.
1495 * \param [in] value The timer frequency in Hz.
1496 */
PL1_SetCounterFrequency(uint32_t value)1497 __STATIC_INLINE void PL1_SetCounterFrequency(uint32_t value)
1498 {
1499 __set_CNTFRQ(value);
1500 __ISB();
1501 }
1502
1503 /** \brief Sets the reset value of the timer.
1504 * \param [in] value The value the timer is loaded with.
1505 */
PL1_SetLoadValue(uint32_t value)1506 __STATIC_INLINE void PL1_SetLoadValue(uint32_t value)
1507 {
1508 __set_CNTP_TVAL(value);
1509 __ISB();
1510 }
1511
1512 /** \brief Get the current counter value.
1513 * \return Current counter value.
1514 */
PL1_GetCurrentValue(void)1515 __STATIC_INLINE uint32_t PL1_GetCurrentValue(void)
1516 {
1517 return(__get_CNTP_TVAL());
1518 }
1519
1520 /** \brief Get the current physical counter value.
1521 * \return Current physical counter value.
1522 */
PL1_GetCurrentPhysicalValue(void)1523 __STATIC_INLINE uint64_t PL1_GetCurrentPhysicalValue(void)
1524 {
1525 return(__get_CNTPCT());
1526 }
1527
1528 /** \brief Set the physical compare value.
1529 * \param [in] value New physical timer compare value.
1530 */
PL1_SetPhysicalCompareValue(uint64_t value)1531 __STATIC_INLINE void PL1_SetPhysicalCompareValue(uint64_t value)
1532 {
1533 __set_CNTP_CVAL(value);
1534 __ISB();
1535 }
1536
1537 /** \brief Get the physical compare value.
1538 * \return Physical compare value.
1539 */
PL1_GetPhysicalCompareValue(void)1540 __STATIC_INLINE uint64_t PL1_GetPhysicalCompareValue(void)
1541 {
1542 return(__get_CNTP_CVAL());
1543 }
1544
1545 /** \brief Configure the timer by setting the control value.
1546 * \param [in] value New timer control value.
1547 */
PL1_SetControl(uint32_t value)1548 __STATIC_INLINE void PL1_SetControl(uint32_t value)
1549 {
1550 __set_CNTP_CTL(value);
1551 __ISB();
1552 }
1553
1554 /** \brief Get the control value.
1555 * \return Control value.
1556 */
PL1_GetControl(void)1557 __STATIC_INLINE uint32_t PL1_GetControl(void)
1558 {
1559 return(__get_CNTP_CTL());
1560 }
1561 #endif
1562
1563 /* Private Timer */
1564 #if ((__CORTEX_R == 7U) || (__CORTEX_R == 8U)) || defined(DOXYGEN)
1565 /** \brief Set the load value to timers LOAD register.
1566 * \param [in] value The load value to be set.
1567 */
PTIM_SetLoadValue(uint32_t value)1568 __STATIC_INLINE void PTIM_SetLoadValue(uint32_t value)
1569 {
1570 PTIM->LOAD = value;
1571 }
1572
1573 /** \brief Get the load value from timers LOAD register.
1574 * \return Timer_Type::LOAD
1575 */
PTIM_GetLoadValue(void)1576 __STATIC_INLINE uint32_t PTIM_GetLoadValue(void)
1577 {
1578 return(PTIM->LOAD);
1579 }
1580
1581 /** \brief Set current counter value from its COUNTER register.
1582 */
PTIM_SetCurrentValue(uint32_t value)1583 __STATIC_INLINE void PTIM_SetCurrentValue(uint32_t value)
1584 {
1585 PTIM->COUNTER = value;
1586 }
1587
1588 /** \brief Get current counter value from timers COUNTER register.
1589 * \result Timer_Type::COUNTER
1590 */
PTIM_GetCurrentValue(void)1591 __STATIC_INLINE uint32_t PTIM_GetCurrentValue(void)
1592 {
1593 return(PTIM->COUNTER);
1594 }
1595
1596 /** \brief Configure the timer using its CONTROL register.
1597 * \param [in] value The new configuration value to be set.
1598 */
PTIM_SetControl(uint32_t value)1599 __STATIC_INLINE void PTIM_SetControl(uint32_t value)
1600 {
1601 PTIM->CONTROL = value;
1602 }
1603
1604 /** ref Timer_Type::CONTROL Get the current timer configuration from its CONTROL register.
1605 * \return Timer_Type::CONTROL
1606 */
PTIM_GetControl(void)1607 __STATIC_INLINE uint32_t PTIM_GetControl(void)
1608 {
1609 return(PTIM->CONTROL);
1610 }
1611
1612 /** ref Timer_Type::CONTROL Get the event flag in timers ISR register.
1613 * \return 0 - flag is not set, 1- flag is set
1614 */
PTIM_GetEventFlag(void)1615 __STATIC_INLINE uint32_t PTIM_GetEventFlag(void)
1616 {
1617 return (PTIM->ISR & 1UL);
1618 }
1619
1620 /** ref Timer_Type::CONTROL Clears the event flag in timers ISR register.
1621 */
PTIM_ClearEventFlag(void)1622 __STATIC_INLINE void PTIM_ClearEventFlag(void)
1623 {
1624 PTIM->ISR = 1;
1625 }
1626 #endif
1627 #endif
1628
1629 #ifdef __cplusplus
1630 }
1631 #endif
1632
1633 #endif /* __CORE_CR_H_DEPENDANT */
1634
1635 #endif /* __CMSIS_GENERIC */
1636
