1 /**************************************************************************//**
2 * @file core_cm23.h
3 * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File
4 * @version V5.1.0
5 * @date 11. February 2020
6 ******************************************************************************/
7 /*
8 * Copyright (c) 2009-2020 Arm Limited. All rights reserved.
9 *
10 * SPDX-License-Identifier: Apache-2.0
11 *
12 * Licensed under the Apache License, Version 2.0 (the License); you may
13 * not use this file except in compliance with the License.
14 * You may obtain a copy of the License at
15 *
16 * www.apache.org/licenses/LICENSE-2.0
17 *
18 * Unless required by applicable law or agreed to in writing, software
19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
21 * See the License for the specific language governing permissions and
22 * limitations under the License.
23 */
24
25 #if defined ( __ICCARM__ )
26 #pragma system_include /* treat file as system include file for MISRA check */
27 #elif defined (__clang__)
28 #pragma clang system_header /* treat file as system include file */
29 #elif defined ( __GNUC__ )
30 #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */
31 #endif
32
33 #ifndef __CORE_CM23_H_GENERIC
34 #define __CORE_CM23_H_GENERIC
35
36 #include <stdint.h>
37
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41
42 /**
43 \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
44 CMSIS violates the following MISRA-C:2004 rules:
45
46 \li Required Rule 8.5, object/function definition in header file.<br>
47 Function definitions in header files are used to allow 'inlining'.
48
49 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
50 Unions are used for effective representation of core registers.
51
52 \li Advisory Rule 19.7, Function-like macro defined.<br>
53 Function-like macros are used to allow more efficient code.
54 */
55
56
57 /*******************************************************************************
58 * CMSIS definitions
59 ******************************************************************************/
60 /**
61 \ingroup Cortex_M23
62 @{
63 */
64
65 #include "cmsis_version.h"
66
67 /* CMSIS definitions */
68 #define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
69 #define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
70 #define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \
71 __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
72
73 #define __CORTEX_M (23U) /*!< Cortex-M Core */
74
75 /** __FPU_USED indicates whether an FPU is used or not.
76 This core does not support an FPU at all
77 */
78 #define __FPU_USED 0U
79
80 #if defined ( __CC_ARM )
81 #if defined __TARGET_FPU_VFP
82 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
83 #endif
84
85 #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
86 #if defined __ARM_FP
87 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
88 #endif
89
90 #elif defined ( __GNUC__ )
91 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
92 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
93 #endif
94
95 #elif defined ( __ICCARM__ )
96 #if defined __ARMVFP__
97 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
98 #endif
99
100 #elif defined ( __TI_ARM__ )
101 #if defined __TI_VFP_SUPPORT__
102 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
103 #endif
104
105 #elif defined ( __TASKING__ )
106 #if defined __FPU_VFP__
107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
108 #endif
109
110 #elif defined ( __CSMC__ )
111 #if ( __CSMC__ & 0x400U)
112 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
113 #endif
114
115 #endif
116
117 #include "cmsis_compiler.h" /* CMSIS compiler specific defines */
118
119
120 #ifdef __cplusplus
121 }
122 #endif
123
124 #endif /* __CORE_CM23_H_GENERIC */
125
126 #ifndef __CMSIS_GENERIC
127
128 #ifndef __CORE_CM23_H_DEPENDANT
129 #define __CORE_CM23_H_DEPENDANT
130
131 #ifdef __cplusplus
132 extern "C" {
133 #endif
134
135 /* check device defines and use defaults */
136 #if defined __CHECK_DEVICE_DEFINES
137 #ifndef __CM23_REV
138 #define __CM23_REV 0x0000U
139 #warning "__CM23_REV not defined in device header file; using default!"
140 #endif
141
142 #ifndef __FPU_PRESENT
143 #define __FPU_PRESENT 0U
144 #warning "__FPU_PRESENT not defined in device header file; using default!"
145 #endif
146
147 #ifndef __MPU_PRESENT
148 #define __MPU_PRESENT 0U
149 #warning "__MPU_PRESENT not defined in device header file; using default!"
150 #endif
151
152 #ifndef __SAUREGION_PRESENT
153 #define __SAUREGION_PRESENT 0U
154 #warning "__SAUREGION_PRESENT not defined in device header file; using default!"
155 #endif
156
157 #ifndef __VTOR_PRESENT
158 #define __VTOR_PRESENT 0U
159 #warning "__VTOR_PRESENT not defined in device header file; using default!"
160 #endif
161
162 #ifndef __NVIC_PRIO_BITS
163 #define __NVIC_PRIO_BITS 2U
164 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
165 #endif
166
167 #ifndef __Vendor_SysTickConfig
168 #define __Vendor_SysTickConfig 0U
169 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
170 #endif
171
172 #ifndef __ETM_PRESENT
173 #define __ETM_PRESENT 0U
174 #warning "__ETM_PRESENT not defined in device header file; using default!"
175 #endif
176
177 #ifndef __MTB_PRESENT
178 #define __MTB_PRESENT 0U
179 #warning "__MTB_PRESENT not defined in device header file; using default!"
180 #endif
181
182 #endif
183
184 /* IO definitions (access restrictions to peripheral registers) */
185 /**
186 \defgroup CMSIS_glob_defs CMSIS Global Defines
187
188 <strong>IO Type Qualifiers</strong> are used
189 \li to specify the access to peripheral variables.
190 \li for automatic generation of peripheral register debug information.
191 */
192 #ifdef __cplusplus
193 #define __I volatile /*!< Defines 'read only' permissions */
194 #else
195 #define __I volatile const /*!< Defines 'read only' permissions */
196 #endif
197 #define __O volatile /*!< Defines 'write only' permissions */
198 #define __IO volatile /*!< Defines 'read / write' permissions */
199
200 /* following defines should be used for structure members */
201 #define __IM volatile const /*! Defines 'read only' structure member permissions */
202 #define __OM volatile /*! Defines 'write only' structure member permissions */
203 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
204
205 /*@} end of group Cortex_M23 */
206
207
208
209 /*******************************************************************************
210 * Register Abstraction
211 Core Register contain:
212 - Core Register
213 - Core NVIC Register
214 - Core SCB Register
215 - Core SysTick Register
216 - Core Debug Register
217 - Core MPU Register
218 - Core SAU Register
219 ******************************************************************************/
220 /**
221 \defgroup CMSIS_core_register Defines and Type Definitions
222 \brief Type definitions and defines for Cortex-M processor based devices.
223 */
224
225 /**
226 \ingroup CMSIS_core_register
227 \defgroup CMSIS_CORE Status and Control Registers
228 \brief Core Register type definitions.
229 @{
230 */
231
232 /**
233 \brief Union type to access the Application Program Status Register (APSR).
234 */
235 typedef union
236 {
237 struct
238 {
239 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
240 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
241 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
242 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
243 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
244 } b; /*!< Structure used for bit access */
245 uint32_t w; /*!< Type used for word access */
246 } APSR_Type;
247
248 /* APSR Register Definitions */
249 #define APSR_N_Pos 31U /*!< APSR: N Position */
250 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
251
252 #define APSR_Z_Pos 30U /*!< APSR: Z Position */
253 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
254
255 #define APSR_C_Pos 29U /*!< APSR: C Position */
256 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
257
258 #define APSR_V_Pos 28U /*!< APSR: V Position */
259 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
260
261
262 /**
263 \brief Union type to access the Interrupt Program Status Register (IPSR).
264 */
265 typedef union
266 {
267 struct
268 {
269 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
270 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
271 } b; /*!< Structure used for bit access */
272 uint32_t w; /*!< Type used for word access */
273 } IPSR_Type;
274
275 /* IPSR Register Definitions */
276 #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
277 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
278
279
280 /**
281 \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
282 */
283 typedef union
284 {
285 struct
286 {
287 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
288 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
289 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
290 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
291 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
292 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
293 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
294 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
295 } b; /*!< Structure used for bit access */
296 uint32_t w; /*!< Type used for word access */
297 } xPSR_Type;
298
299 /* xPSR Register Definitions */
300 #define xPSR_N_Pos 31U /*!< xPSR: N Position */
301 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
302
303 #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
304 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
305
306 #define xPSR_C_Pos 29U /*!< xPSR: C Position */
307 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
308
309 #define xPSR_V_Pos 28U /*!< xPSR: V Position */
310 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
311
312 #define xPSR_T_Pos 24U /*!< xPSR: T Position */
313 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
314
315 #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
316 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
317
318
319 /**
320 \brief Union type to access the Control Registers (CONTROL).
321 */
322 typedef union
323 {
324 struct
325 {
326 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
327 uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */
328 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
329 } b; /*!< Structure used for bit access */
330 uint32_t w; /*!< Type used for word access */
331 } CONTROL_Type;
332
333 /* CONTROL Register Definitions */
334 #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
335 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
336
337 #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */
338 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
339
340 /*@} end of group CMSIS_CORE */
341
342
343 /**
344 \ingroup CMSIS_core_register
345 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
346 \brief Type definitions for the NVIC Registers
347 @{
348 */
349
350 /**
351 \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
352 */
353 typedef struct
354 {
355 __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
356 uint32_t RESERVED0[16U];
357 __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
358 uint32_t RSERVED1[16U];
359 __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
360 uint32_t RESERVED2[16U];
361 __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
362 uint32_t RESERVED3[16U];
363 __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
364 uint32_t RESERVED4[16U];
365 __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */
366 uint32_t RESERVED5[16U];
367 __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
368 } NVIC_Type;
369
370 /*@} end of group CMSIS_NVIC */
371
372
373 /**
374 \ingroup CMSIS_core_register
375 \defgroup CMSIS_SCB System Control Block (SCB)
376 \brief Type definitions for the System Control Block Registers
377 @{
378 */
379
380 /**
381 \brief Structure type to access the System Control Block (SCB).
382 */
383 typedef struct
384 {
385 __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
386 __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
387 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
388 __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
389 #else
390 uint32_t RESERVED0;
391 #endif
392 __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
393 __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
394 __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
395 uint32_t RESERVED1;
396 __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
397 __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
398 } SCB_Type;
399
400 /* SCB CPUID Register Definitions */
401 #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
402 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
403
404 #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
405 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
406
407 #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
408 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
409
410 #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
411 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
412
413 #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
414 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
415
416 /* SCB Interrupt Control State Register Definitions */
417 #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */
418 #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */
419
420 #define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */
421 #define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */
422
423 #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */
424 #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */
425
426 #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
427 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
428
429 #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
430 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
431
432 #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
433 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
434
435 #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
436 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
437
438 #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */
439 #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */
440
441 #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
442 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
443
444 #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
445 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
446
447 #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
448 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
449
450 #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */
451 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
452
453 #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
454 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
455
456 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
457 /* SCB Vector Table Offset Register Definitions */
458 #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */
459 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
460 #endif
461
462 /* SCB Application Interrupt and Reset Control Register Definitions */
463 #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
464 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
465
466 #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
467 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
468
469 #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
470 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
471
472 #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */
473 #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */
474
475 #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */
476 #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */
477
478 #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */
479 #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */
480
481 #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
483
484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
486
487 /* SCB System Control Register Definitions */
488 #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
489 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
490
491 #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */
492 #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */
493
494 #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
496
497 #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
499
500 /* SCB Configuration Control Register Definitions */
501 #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */
502 #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */
503
504 #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */
505 #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */
506
507 #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */
508 #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */
509
510 #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */
511 #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */
512
513 #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */
514 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
515
516 #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */
517 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
518
519 #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
520 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
521
522 #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */
523 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
524
525 /* SCB System Handler Control and State Register Definitions */
526 #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */
527 #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */
528
529 #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
531
532 #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */
533 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
534
535 #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */
536 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
537
538 #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */
539 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
540
541 #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */
542 #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */
543
544 #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */
545 #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */
546
547 /*@} end of group CMSIS_SCB */
548
549
550 /**
551 \ingroup CMSIS_core_register
552 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
553 \brief Type definitions for the System Timer Registers.
554 @{
555 */
556
557 /**
558 \brief Structure type to access the System Timer (SysTick).
559 */
560 typedef struct
561 {
562 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
563 __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
564 __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
565 __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
566 } SysTick_Type;
567
568 /* SysTick Control / Status Register Definitions */
569 #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
570 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
571
572 #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
573 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
574
575 #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
576 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
577
578 #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
579 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
580
581 /* SysTick Reload Register Definitions */
582 #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
583 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
584
585 /* SysTick Current Register Definitions */
586 #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
587 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
588
589 /* SysTick Calibration Register Definitions */
590 #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
591 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
592
593 #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
594 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
595
596 #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
597 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
598
599 /*@} end of group CMSIS_SysTick */
600
601
602 /**
603 \ingroup CMSIS_core_register
604 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
605 \brief Type definitions for the Data Watchpoint and Trace (DWT)
606 @{
607 */
608
609 /**
610 \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
611 */
612 typedef struct
613 {
614 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
615 uint32_t RESERVED0[6U];
616 __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
617 __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
618 uint32_t RESERVED1[1U];
619 __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
620 uint32_t RESERVED2[1U];
621 __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
622 uint32_t RESERVED3[1U];
623 __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
624 uint32_t RESERVED4[1U];
625 __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
626 uint32_t RESERVED5[1U];
627 __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
628 uint32_t RESERVED6[1U];
629 __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
630 uint32_t RESERVED7[1U];
631 __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
632 uint32_t RESERVED8[1U];
633 __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */
634 uint32_t RESERVED9[1U];
635 __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */
636 uint32_t RESERVED10[1U];
637 __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */
638 uint32_t RESERVED11[1U];
639 __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */
640 uint32_t RESERVED12[1U];
641 __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */
642 uint32_t RESERVED13[1U];
643 __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */
644 uint32_t RESERVED14[1U];
645 __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */
646 uint32_t RESERVED15[1U];
647 __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */
648 uint32_t RESERVED16[1U];
649 __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */
650 uint32_t RESERVED17[1U];
651 __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */
652 uint32_t RESERVED18[1U];
653 __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */
654 uint32_t RESERVED19[1U];
655 __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */
656 uint32_t RESERVED20[1U];
657 __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */
658 uint32_t RESERVED21[1U];
659 __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */
660 uint32_t RESERVED22[1U];
661 __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */
662 uint32_t RESERVED23[1U];
663 __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */
664 uint32_t RESERVED24[1U];
665 __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */
666 uint32_t RESERVED25[1U];
667 __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */
668 uint32_t RESERVED26[1U];
669 __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */
670 uint32_t RESERVED27[1U];
671 __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */
672 uint32_t RESERVED28[1U];
673 __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */
674 uint32_t RESERVED29[1U];
675 __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */
676 uint32_t RESERVED30[1U];
677 __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */
678 uint32_t RESERVED31[1U];
679 __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */
680 } DWT_Type;
681
682 /* DWT Control Register Definitions */
683 #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */
684 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
685
686 #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */
687 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
688
689 #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */
690 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
691
692 #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */
693 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
694
695 #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */
696 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
697
698 /* DWT Comparator Function Register Definitions */
699 #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */
700 #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */
701
702 #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */
703 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
704
705 #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */
706 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
707
708 #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */
709 #define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */
710
711 #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */
712 #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */
713
714 /*@}*/ /* end of group CMSIS_DWT */
715
716
717 /**
718 \ingroup CMSIS_core_register
719 \defgroup CMSIS_TPI Trace Port Interface (TPI)
720 \brief Type definitions for the Trace Port Interface (TPI)
721 @{
722 */
723
724 /**
725 \brief Structure type to access the Trace Port Interface Register (TPI).
726 */
727 typedef struct
728 {
729 __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
730 __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
731 uint32_t RESERVED0[2U];
732 __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
733 uint32_t RESERVED1[55U];
734 __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
735 uint32_t RESERVED2[131U];
736 __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
737 __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
738 __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */
739 uint32_t RESERVED3[759U];
740 __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */
741 __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */
742 __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */
743 uint32_t RESERVED4[1U];
744 __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */
745 __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */
746 __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
747 uint32_t RESERVED5[39U];
748 __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
749 __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
750 uint32_t RESERVED7[8U];
751 __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */
752 __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */
753 } TPI_Type;
754
755 /* TPI Asynchronous Clock Prescaler Register Definitions */
756 #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */
757 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
758
759 /* TPI Selected Pin Protocol Register Definitions */
760 #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */
761 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
762
763 /* TPI Formatter and Flush Status Register Definitions */
764 #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */
765 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
766
767 #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */
768 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
769
770 #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */
771 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
772
773 #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */
774 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
775
776 /* TPI Formatter and Flush Control Register Definitions */
777 #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */
778 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
779
780 #define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */
781 #define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */
782
783 #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */
784 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
785
786 /* TPI TRIGGER Register Definitions */
787 #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */
788 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
789
790 /* TPI Integration Test FIFO Test Data 0 Register Definitions */
791 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */
792 #define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */
793
794 #define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */
795 #define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */
796
797 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */
798 #define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */
799
800 #define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */
801 #define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */
802
803 #define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */
804 #define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */
805
806 #define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */
807 #define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */
808
809 #define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */
810 #define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */
811
812 /* TPI Integration Test ATB Control Register 2 Register Definitions */
813 #define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */
814 #define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */
815
816 #define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */
817 #define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */
818
819 #define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */
820 #define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */
821
822 #define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */
823 #define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */
824
825 /* TPI Integration Test FIFO Test Data 1 Register Definitions */
826 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */
827 #define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */
828
829 #define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */
830 #define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */
831
832 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */
833 #define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */
834
835 #define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */
836 #define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */
837
838 #define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */
839 #define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */
840
841 #define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */
842 #define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */
843
844 #define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */
845 #define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */
846
847 /* TPI Integration Test ATB Control Register 0 Definitions */
848 #define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */
849 #define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */
850
851 #define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */
852 #define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */
853
854 #define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */
855 #define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */
856
857 #define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */
858 #define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */
859
860 /* TPI Integration Mode Control Register Definitions */
861 #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */
862 #define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
863
864 /* TPI DEVID Register Definitions */
865 #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */
866 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
867
868 #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */
869 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
870
871 #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */
872 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
873
874 #define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */
875 #define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */
876
877 #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */
878 #define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
879
880 /* TPI DEVTYPE Register Definitions */
881 #define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */
882 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
883
884 #define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */
885 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
886
887 /*@}*/ /* end of group CMSIS_TPI */
888
889
890 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
891 /**
892 \ingroup CMSIS_core_register
893 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
894 \brief Type definitions for the Memory Protection Unit (MPU)
895 @{
896 */
897
898 /**
899 \brief Structure type to access the Memory Protection Unit (MPU).
900 */
901 typedef struct
902 {
903 __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
904 __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
905 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */
906 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
907 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */
908 uint32_t RESERVED0[7U];
909 union {
910 __IOM uint32_t MAIR[2];
911 struct {
912 __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */
913 __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */
914 };
915 };
916 } MPU_Type;
917
918 #define MPU_TYPE_RALIASES 1U
919
920 /* MPU Type Register Definitions */
921 #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */
922 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
923
924 #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */
925 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
926
927 #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */
928 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
929
930 /* MPU Control Register Definitions */
931 #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */
932 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
933
934 #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */
935 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
936
937 #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */
938 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
939
940 /* MPU Region Number Register Definitions */
941 #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */
942 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
943
944 /* MPU Region Base Address Register Definitions */
945 #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */
946 #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */
947
948 #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */
949 #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */
950
951 #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */
952 #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */
953
954 #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */
955 #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */
956
957 /* MPU Region Limit Address Register Definitions */
958 #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */
959 #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */
960
961 #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */
962 #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */
963
964 #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */
965 #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */
966
967 /* MPU Memory Attribute Indirection Register 0 Definitions */
968 #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */
969 #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */
970
971 #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */
972 #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */
973
974 #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */
975 #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */
976
977 #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */
978 #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */
979
980 /* MPU Memory Attribute Indirection Register 1 Definitions */
981 #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */
982 #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */
983
984 #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */
985 #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */
986
987 #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */
988 #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */
989
990 #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */
991 #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */
992
993 /*@} end of group CMSIS_MPU */
994 #endif
995
996
997 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
998 /**
999 \ingroup CMSIS_core_register
1000 \defgroup CMSIS_SAU Security Attribution Unit (SAU)
1001 \brief Type definitions for the Security Attribution Unit (SAU)
1002 @{
1003 */
1004
1005 /**
1006 \brief Structure type to access the Security Attribution Unit (SAU).
1007 */
1008 typedef struct
1009 {
1010 __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */
1011 __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */
1012 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1013 __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */
1014 __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */
1015 __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */
1016 #endif
1017 } SAU_Type;
1018
1019 /* SAU Control Register Definitions */
1020 #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */
1021 #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */
1022
1023 #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */
1024 #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */
1025
1026 /* SAU Type Register Definitions */
1027 #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */
1028 #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */
1029
1030 #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
1031 /* SAU Region Number Register Definitions */
1032 #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */
1033 #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */
1034
1035 /* SAU Region Base Address Register Definitions */
1036 #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */
1037 #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */
1038
1039 /* SAU Region Limit Address Register Definitions */
1040 #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */
1041 #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */
1042
1043 #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */
1044 #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */
1045
1046 #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */
1047 #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */
1048
1049 #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
1050
1051 /*@} end of group CMSIS_SAU */
1052 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1053
1054
1055 /* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */
1056 /**
1057 \ingroup CMSIS_core_register
1058 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
1059 \brief Type definitions for the Core Debug Registers
1060 @{
1061 */
1062
1063 /**
1064 \brief \deprecated Structure type to access the Core Debug Register (CoreDebug).
1065 */
1066 typedef struct
1067 {
1068 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1069 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1070 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1071 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1072 uint32_t RESERVED0[1U];
1073 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1074 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1075 } CoreDebug_Type;
1076
1077 /* Debug Halting Control and Status Register Definitions */
1078 #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */
1079 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */
1080
1081 #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */
1082 #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */
1083
1084 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */
1085 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */
1086
1087 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */
1088 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */
1089
1090 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */
1091 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */
1092
1093 #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */
1094 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */
1095
1096 #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */
1097 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */
1098
1099 #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */
1100 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */
1101
1102 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */
1103 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */
1104
1105 #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */
1106 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */
1107
1108 #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */
1109 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */
1110
1111 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */
1112 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */
1113
1114 /* Debug Core Register Selector Register Definitions */
1115 #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */
1116 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */
1117
1118 #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */
1119 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */
1120
1121 /* Debug Exception and Monitor Control Register */
1122 #define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */
1123 #define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */
1124
1125 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */
1126 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */
1127
1128 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */
1129 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */
1130
1131 /* Debug Authentication Control Register Definitions */
1132 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */
1133 #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */
1134
1135 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */
1136 #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */
1137
1138 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */
1139 #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */
1140
1141 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */
1142 #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */
1143
1144 /* Debug Security Control and Status Register Definitions */
1145 #define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */
1146 #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */
1147
1148 #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */
1149 #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */
1150
1151 #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */
1152 #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */
1153
1154 /*@} end of group CMSIS_CoreDebug */
1155
1156
1157 /**
1158 \ingroup CMSIS_core_register
1159 \defgroup CMSIS_DCB Debug Control Block
1160 \brief Type definitions for the Debug Control Block Registers
1161 @{
1162 */
1163
1164 /**
1165 \brief Structure type to access the Debug Control Block Registers (DCB).
1166 */
1167 typedef struct
1168 {
1169 __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
1170 __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
1171 __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
1172 __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
1173 uint32_t RESERVED0[1U];
1174 __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */
1175 __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */
1176 } DCB_Type;
1177
1178 /* DHCSR, Debug Halting Control and Status Register Definitions */
1179 #define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */
1180 #define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */
1181
1182 #define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */
1183 #define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */
1184
1185 #define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */
1186 #define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */
1187
1188 #define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */
1189 #define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */
1190
1191 #define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */
1192 #define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */
1193
1194 #define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */
1195 #define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */
1196
1197 #define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */
1198 #define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */
1199
1200 #define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */
1201 #define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */
1202
1203 #define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */
1204 #define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */
1205
1206 #define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */
1207 #define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */
1208
1209 #define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */
1210 #define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */
1211
1212 #define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */
1213 #define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */
1214
1215 #define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */
1216 #define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */
1217
1218 /* DCRSR, Debug Core Register Select Register Definitions */
1219 #define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */
1220 #define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */
1221
1222 #define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */
1223 #define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */
1224
1225 /* DCRDR, Debug Core Register Data Register Definitions */
1226 #define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */
1227 #define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */
1228
1229 /* DEMCR, Debug Exception and Monitor Control Register Definitions */
1230 #define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */
1231 #define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */
1232
1233 #define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */
1234 #define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */
1235
1236 #define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */
1237 #define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */
1238
1239 /* DAUTHCTRL, Debug Authentication Control Register Definitions */
1240 #define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */
1241 #define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */
1242
1243 #define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */
1244 #define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */
1245
1246 #define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */
1247 #define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */
1248
1249 #define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */
1250 #define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */
1251
1252 /* DSCSR, Debug Security Control and Status Register Definitions */
1253 #define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */
1254 #define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */
1255
1256 #define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */
1257 #define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */
1258
1259 #define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */
1260 #define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */
1261
1262 #define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */
1263 #define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */
1264
1265 /*@} end of group CMSIS_DCB */
1266
1267
1268
1269 /**
1270 \ingroup CMSIS_core_register
1271 \defgroup CMSIS_DIB Debug Identification Block
1272 \brief Type definitions for the Debug Identification Block Registers
1273 @{
1274 */
1275
1276 /**
1277 \brief Structure type to access the Debug Identification Block Registers (DIB).
1278 */
1279 typedef struct
1280 {
1281 __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */
1282 __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */
1283 __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */
1284 __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */
1285 __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */
1286 } DIB_Type;
1287
1288 /* DLAR, SCS Software Lock Access Register Definitions */
1289 #define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */
1290 #define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */
1291
1292 /* DLSR, SCS Software Lock Status Register Definitions */
1293 #define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */
1294 #define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */
1295
1296 #define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */
1297 #define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */
1298
1299 #define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */
1300 #define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */
1301
1302 /* DAUTHSTATUS, Debug Authentication Status Register Definitions */
1303 #define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */
1304 #define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */
1305
1306 #define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */
1307 #define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */
1308
1309 #define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */
1310 #define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */
1311
1312 #define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */
1313 #define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */
1314
1315 /* DDEVARCH, SCS Device Architecture Register Definitions */
1316 #define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */
1317 #define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */
1318
1319 #define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */
1320 #define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */
1321
1322 #define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */
1323 #define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */
1324
1325 #define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */
1326 #define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */
1327
1328 #define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */
1329 #define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */
1330
1331 /* DDEVTYPE, SCS Device Type Register Definitions */
1332 #define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */
1333 #define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */
1334
1335 #define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */
1336 #define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */
1337
1338
1339 /*@} end of group CMSIS_DIB */
1340
1341
1342 /**
1343 \ingroup CMSIS_core_register
1344 \defgroup CMSIS_core_bitfield Core register bit field macros
1345 \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
1346 @{
1347 */
1348
1349 /**
1350 \brief Mask and shift a bit field value for use in a register bit range.
1351 \param[in] field Name of the register bit field.
1352 \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
1353 \return Masked and shifted value.
1354 */
1355 #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
1356
1357 /**
1358 \brief Mask and shift a register value to extract a bit filed value.
1359 \param[in] field Name of the register bit field.
1360 \param[in] value Value of register. This parameter is interpreted as an uint32_t type.
1361 \return Masked and shifted bit field value.
1362 */
1363 #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
1364
1365 /*@} end of group CMSIS_core_bitfield */
1366
1367
1368 /**
1369 \ingroup CMSIS_core_register
1370 \defgroup CMSIS_core_base Core Definitions
1371 \brief Definitions for base addresses, unions, and structures.
1372 @{
1373 */
1374
1375 /* Memory mapping of Core Hardware */
1376 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
1377 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
1378 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
1379 #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */
1380 #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */
1381 #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */
1382 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
1383 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
1384 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
1385
1386
1387 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
1388 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
1389 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
1390 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
1391 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
1392 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */
1393 #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */
1394 #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */
1395
1396 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1397 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
1398 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
1399 #endif
1400
1401 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1402 #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */
1403 #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */
1404 #endif
1405
1406 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1407 #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */
1408 #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */
1409 #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */
1410 #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */
1411 #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */
1412 #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */
1413 #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */
1414
1415 #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */
1416 #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */
1417 #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */
1418 #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */
1419 #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */
1420 #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */
1421
1422 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
1423 #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */
1424 #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */
1425 #endif
1426
1427 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1428 /*@} */
1429
1430
1431
1432 /*******************************************************************************
1433 * Hardware Abstraction Layer
1434 Core Function Interface contains:
1435 - Core NVIC Functions
1436 - Core SysTick Functions
1437 - Core Debug Functions
1438 - Core Register Access Functions
1439 ******************************************************************************/
1440 /**
1441 \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
1442 */
1443
1444
1445
1446 /* ########################## NVIC functions #################################### */
1447 /**
1448 \ingroup CMSIS_Core_FunctionInterface
1449 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
1450 \brief Functions that manage interrupts and exceptions via the NVIC.
1451 @{
1452 */
1453
1454 #ifdef CMSIS_NVIC_VIRTUAL
1455 #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
1456 #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
1457 #endif
1458 #include CMSIS_NVIC_VIRTUAL_HEADER_FILE
1459 #else
1460 /*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */
1461 /*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */
1462 #define NVIC_EnableIRQ __NVIC_EnableIRQ
1463 #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
1464 #define NVIC_DisableIRQ __NVIC_DisableIRQ
1465 #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
1466 #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
1467 #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
1468 #define NVIC_GetActive __NVIC_GetActive
1469 #define NVIC_SetPriority __NVIC_SetPriority
1470 #define NVIC_GetPriority __NVIC_GetPriority
1471 #define NVIC_SystemReset __NVIC_SystemReset
1472 #endif /* CMSIS_NVIC_VIRTUAL */
1473
1474 #ifdef CMSIS_VECTAB_VIRTUAL
1475 #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1476 #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
1477 #endif
1478 #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
1479 #else
1480 #define NVIC_SetVector __NVIC_SetVector
1481 #define NVIC_GetVector __NVIC_GetVector
1482 #endif /* (CMSIS_VECTAB_VIRTUAL) */
1483
1484 #define NVIC_USER_IRQ_OFFSET 16
1485
1486
1487 /* Special LR values for Secure/Non-Secure call handling and exception handling */
1488
1489 /* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */
1490 #define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */
1491
1492 /* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */
1493 #define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */
1494 #define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
1495 #define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */
1496 #define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */
1497 #define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */
1498 #define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */
1499 #define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */
1500
1501 /* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */
1502 #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */
1503 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */
1504 #else
1505 #define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */
1506 #endif
1507
1508
1509 /* Interrupt Priorities are WORD accessible only under Armv6-M */
1510 /* The following MACROS handle generation of the register offset and byte masks */
1511 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
1512 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
1513 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
1514
1515 #define __NVIC_SetPriorityGrouping(X) (void)(X)
1516 #define __NVIC_GetPriorityGrouping() (0U)
1517
1518 /**
1519 \brief Enable Interrupt
1520 \details Enables a device specific interrupt in the NVIC interrupt controller.
1521 \param [in] IRQn Device specific interrupt number.
1522 \note IRQn must not be negative.
1523 */
__NVIC_EnableIRQ(IRQn_Type IRQn)1524 __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
1525 {
1526 if ((int32_t)(IRQn) >= 0)
1527 {
1528 __COMPILER_BARRIER();
1529 NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1530 __COMPILER_BARRIER();
1531 }
1532 }
1533
1534
1535 /**
1536 \brief Get Interrupt Enable status
1537 \details Returns a device specific interrupt enable status from the NVIC interrupt controller.
1538 \param [in] IRQn Device specific interrupt number.
1539 \return 0 Interrupt is not enabled.
1540 \return 1 Interrupt is enabled.
1541 \note IRQn must not be negative.
1542 */
__NVIC_GetEnableIRQ(IRQn_Type IRQn)1543 __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
1544 {
1545 if ((int32_t)(IRQn) >= 0)
1546 {
1547 return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1548 }
1549 else
1550 {
1551 return(0U);
1552 }
1553 }
1554
1555
1556 /**
1557 \brief Disable Interrupt
1558 \details Disables a device specific interrupt in the NVIC interrupt controller.
1559 \param [in] IRQn Device specific interrupt number.
1560 \note IRQn must not be negative.
1561 */
__NVIC_DisableIRQ(IRQn_Type IRQn)1562 __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
1563 {
1564 if ((int32_t)(IRQn) >= 0)
1565 {
1566 NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1567 __DSB();
1568 __ISB();
1569 }
1570 }
1571
1572
1573 /**
1574 \brief Get Pending Interrupt
1575 \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
1576 \param [in] IRQn Device specific interrupt number.
1577 \return 0 Interrupt status is not pending.
1578 \return 1 Interrupt status is pending.
1579 \note IRQn must not be negative.
1580 */
__NVIC_GetPendingIRQ(IRQn_Type IRQn)1581 __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
1582 {
1583 if ((int32_t)(IRQn) >= 0)
1584 {
1585 return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1586 }
1587 else
1588 {
1589 return(0U);
1590 }
1591 }
1592
1593
1594 /**
1595 \brief Set Pending Interrupt
1596 \details Sets the pending bit of a device specific interrupt in the NVIC pending register.
1597 \param [in] IRQn Device specific interrupt number.
1598 \note IRQn must not be negative.
1599 */
__NVIC_SetPendingIRQ(IRQn_Type IRQn)1600 __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
1601 {
1602 if ((int32_t)(IRQn) >= 0)
1603 {
1604 NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1605 }
1606 }
1607
1608
1609 /**
1610 \brief Clear Pending Interrupt
1611 \details Clears the pending bit of a device specific interrupt in the NVIC pending register.
1612 \param [in] IRQn Device specific interrupt number.
1613 \note IRQn must not be negative.
1614 */
__NVIC_ClearPendingIRQ(IRQn_Type IRQn)1615 __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
1616 {
1617 if ((int32_t)(IRQn) >= 0)
1618 {
1619 NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1620 }
1621 }
1622
1623
1624 /**
1625 \brief Get Active Interrupt
1626 \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
1627 \param [in] IRQn Device specific interrupt number.
1628 \return 0 Interrupt status is not active.
1629 \return 1 Interrupt status is active.
1630 \note IRQn must not be negative.
1631 */
__NVIC_GetActive(IRQn_Type IRQn)1632 __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
1633 {
1634 if ((int32_t)(IRQn) >= 0)
1635 {
1636 return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1637 }
1638 else
1639 {
1640 return(0U);
1641 }
1642 }
1643
1644
1645 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1646 /**
1647 \brief Get Interrupt Target State
1648 \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1649 \param [in] IRQn Device specific interrupt number.
1650 \return 0 if interrupt is assigned to Secure
1651 \return 1 if interrupt is assigned to Non Secure
1652 \note IRQn must not be negative.
1653 */
NVIC_GetTargetState(IRQn_Type IRQn)1654 __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
1655 {
1656 if ((int32_t)(IRQn) >= 0)
1657 {
1658 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1659 }
1660 else
1661 {
1662 return(0U);
1663 }
1664 }
1665
1666
1667 /**
1668 \brief Set Interrupt Target State
1669 \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1670 \param [in] IRQn Device specific interrupt number.
1671 \return 0 if interrupt is assigned to Secure
1672 1 if interrupt is assigned to Non Secure
1673 \note IRQn must not be negative.
1674 */
NVIC_SetTargetState(IRQn_Type IRQn)1675 __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
1676 {
1677 if ((int32_t)(IRQn) >= 0)
1678 {
1679 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1680 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1681 }
1682 else
1683 {
1684 return(0U);
1685 }
1686 }
1687
1688
1689 /**
1690 \brief Clear Interrupt Target State
1691 \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
1692 \param [in] IRQn Device specific interrupt number.
1693 \return 0 if interrupt is assigned to Secure
1694 1 if interrupt is assigned to Non Secure
1695 \note IRQn must not be negative.
1696 */
NVIC_ClearTargetState(IRQn_Type IRQn)1697 __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
1698 {
1699 if ((int32_t)(IRQn) >= 0)
1700 {
1701 NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
1702 return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1703 }
1704 else
1705 {
1706 return(0U);
1707 }
1708 }
1709 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
1710
1711
1712 /**
1713 \brief Set Interrupt Priority
1714 \details Sets the priority of a device specific interrupt or a processor exception.
1715 The interrupt number can be positive to specify a device specific interrupt,
1716 or negative to specify a processor exception.
1717 \param [in] IRQn Interrupt number.
1718 \param [in] priority Priority to set.
1719 \note The priority cannot be set for every processor exception.
1720 */
__NVIC_SetPriority(IRQn_Type IRQn,uint32_t priority)1721 __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
1722 {
1723 if ((int32_t)(IRQn) >= 0)
1724 {
1725 NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1726 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1727 }
1728 else
1729 {
1730 SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
1731 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
1732 }
1733 }
1734
1735
1736 /**
1737 \brief Get Interrupt Priority
1738 \details Reads the priority of a device specific interrupt or a processor exception.
1739 The interrupt number can be positive to specify a device specific interrupt,
1740 or negative to specify a processor exception.
1741 \param [in] IRQn Interrupt number.
1742 \return Interrupt Priority.
1743 Value is aligned automatically to the implemented priority bits of the microcontroller.
1744 */
__NVIC_GetPriority(IRQn_Type IRQn)1745 __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
1746 {
1747
1748 if ((int32_t)(IRQn) >= 0)
1749 {
1750 return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1751 }
1752 else
1753 {
1754 return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
1755 }
1756 }
1757
1758
1759 /**
1760 \brief Encode Priority
1761 \details Encodes the priority for an interrupt with the given priority group,
1762 preemptive priority value, and subpriority value.
1763 In case of a conflict between priority grouping and available
1764 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
1765 \param [in] PriorityGroup Used priority group.
1766 \param [in] PreemptPriority Preemptive priority value (starting from 0).
1767 \param [in] SubPriority Subpriority value (starting from 0).
1768 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
1769 */
NVIC_EncodePriority(uint32_t PriorityGroup,uint32_t PreemptPriority,uint32_t SubPriority)1770 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
1771 {
1772 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1773 uint32_t PreemptPriorityBits;
1774 uint32_t SubPriorityBits;
1775
1776 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1777 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1778
1779 return (
1780 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
1781 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
1782 );
1783 }
1784
1785
1786 /**
1787 \brief Decode Priority
1788 \details Decodes an interrupt priority value with a given priority group to
1789 preemptive priority value and subpriority value.
1790 In case of a conflict between priority grouping and available
1791 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
1792 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
1793 \param [in] PriorityGroup Used priority group.
1794 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
1795 \param [out] pSubPriority Subpriority value (starting from 0).
1796 */
NVIC_DecodePriority(uint32_t Priority,uint32_t PriorityGroup,uint32_t * const pPreemptPriority,uint32_t * const pSubPriority)1797 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
1798 {
1799 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
1800 uint32_t PreemptPriorityBits;
1801 uint32_t SubPriorityBits;
1802
1803 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
1804 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
1805
1806 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
1807 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
1808 }
1809
1810
1811 /**
1812 \brief Set Interrupt Vector
1813 \details Sets an interrupt vector in SRAM based interrupt vector table.
1814 The interrupt number can be positive to specify a device specific interrupt,
1815 or negative to specify a processor exception.
1816 VTOR must been relocated to SRAM before.
1817 If VTOR is not present address 0 must be mapped to SRAM.
1818 \param [in] IRQn Interrupt number
1819 \param [in] vector Address of interrupt handler function
1820 */
__NVIC_SetVector(IRQn_Type IRQn,uint32_t vector)1821 __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
1822 {
1823 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1824 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1825 #else
1826 uint32_t *vectors = (uint32_t *)0x0U;
1827 #endif
1828 vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
1829 __DSB();
1830 }
1831
1832
1833 /**
1834 \brief Get Interrupt Vector
1835 \details Reads an interrupt vector from interrupt vector table.
1836 The interrupt number can be positive to specify a device specific interrupt,
1837 or negative to specify a processor exception.
1838 \param [in] IRQn Interrupt number.
1839 \return Address of interrupt handler function
1840 */
__NVIC_GetVector(IRQn_Type IRQn)1841 __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
1842 {
1843 #if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
1844 uint32_t *vectors = (uint32_t *)SCB->VTOR;
1845 #else
1846 uint32_t *vectors = (uint32_t *)0x0U;
1847 #endif
1848 return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
1849 }
1850
1851
1852 /**
1853 \brief System Reset
1854 \details Initiates a system reset request to reset the MCU.
1855 */
__NVIC_SystemReset(void)1856 __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
1857 {
1858 __DSB(); /* Ensure all outstanding memory accesses included
1859 buffered write are completed before reset */
1860 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
1861 SCB_AIRCR_SYSRESETREQ_Msk);
1862 __DSB(); /* Ensure completion of memory access */
1863
1864 for(;;) /* wait until reset */
1865 {
1866 __NOP();
1867 }
1868 }
1869
1870 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
1871 /**
1872 \brief Enable Interrupt (non-secure)
1873 \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1874 \param [in] IRQn Device specific interrupt number.
1875 \note IRQn must not be negative.
1876 */
TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)1877 __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
1878 {
1879 if ((int32_t)(IRQn) >= 0)
1880 {
1881 NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1882 }
1883 }
1884
1885
1886 /**
1887 \brief Get Interrupt Enable status (non-secure)
1888 \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
1889 \param [in] IRQn Device specific interrupt number.
1890 \return 0 Interrupt is not enabled.
1891 \return 1 Interrupt is enabled.
1892 \note IRQn must not be negative.
1893 */
TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)1894 __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
1895 {
1896 if ((int32_t)(IRQn) >= 0)
1897 {
1898 return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1899 }
1900 else
1901 {
1902 return(0U);
1903 }
1904 }
1905
1906
1907 /**
1908 \brief Disable Interrupt (non-secure)
1909 \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
1910 \param [in] IRQn Device specific interrupt number.
1911 \note IRQn must not be negative.
1912 */
TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)1913 __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
1914 {
1915 if ((int32_t)(IRQn) >= 0)
1916 {
1917 NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1918 }
1919 }
1920
1921
1922 /**
1923 \brief Get Pending Interrupt (non-secure)
1924 \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
1925 \param [in] IRQn Device specific interrupt number.
1926 \return 0 Interrupt status is not pending.
1927 \return 1 Interrupt status is pending.
1928 \note IRQn must not be negative.
1929 */
TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)1930 __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
1931 {
1932 if ((int32_t)(IRQn) >= 0)
1933 {
1934 return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1935 }
1936 else
1937 {
1938 return(0U);
1939 }
1940 }
1941
1942
1943 /**
1944 \brief Set Pending Interrupt (non-secure)
1945 \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1946 \param [in] IRQn Device specific interrupt number.
1947 \note IRQn must not be negative.
1948 */
TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)1949 __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
1950 {
1951 if ((int32_t)(IRQn) >= 0)
1952 {
1953 NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1954 }
1955 }
1956
1957
1958 /**
1959 \brief Clear Pending Interrupt (non-secure)
1960 \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
1961 \param [in] IRQn Device specific interrupt number.
1962 \note IRQn must not be negative.
1963 */
TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)1964 __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
1965 {
1966 if ((int32_t)(IRQn) >= 0)
1967 {
1968 NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
1969 }
1970 }
1971
1972
1973 /**
1974 \brief Get Active Interrupt (non-secure)
1975 \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
1976 \param [in] IRQn Device specific interrupt number.
1977 \return 0 Interrupt status is not active.
1978 \return 1 Interrupt status is active.
1979 \note IRQn must not be negative.
1980 */
TZ_NVIC_GetActive_NS(IRQn_Type IRQn)1981 __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
1982 {
1983 if ((int32_t)(IRQn) >= 0)
1984 {
1985 return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
1986 }
1987 else
1988 {
1989 return(0U);
1990 }
1991 }
1992
1993
1994 /**
1995 \brief Set Interrupt Priority (non-secure)
1996 \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
1997 The interrupt number can be positive to specify a device specific interrupt,
1998 or negative to specify a processor exception.
1999 \param [in] IRQn Interrupt number.
2000 \param [in] priority Priority to set.
2001 \note The priority cannot be set for every non-secure processor exception.
2002 */
TZ_NVIC_SetPriority_NS(IRQn_Type IRQn,uint32_t priority)2003 __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
2004 {
2005 if ((int32_t)(IRQn) >= 0)
2006 {
2007 NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
2008 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
2009 }
2010 else
2011 {
2012 SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
2013 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
2014 }
2015 }
2016
2017
2018 /**
2019 \brief Get Interrupt Priority (non-secure)
2020 \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
2021 The interrupt number can be positive to specify a device specific interrupt,
2022 or negative to specify a processor exception.
2023 \param [in] IRQn Interrupt number.
2024 \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
2025 */
TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)2026 __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
2027 {
2028
2029 if ((int32_t)(IRQn) >= 0)
2030 {
2031 return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
2032 }
2033 else
2034 {
2035 return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
2036 }
2037 }
2038 #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
2039
2040 /*@} end of CMSIS_Core_NVICFunctions */
2041
2042 /* ########################## MPU functions #################################### */
2043
2044 #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
2045
2046 #include "mpu_armv8.h"
2047
2048 #endif
2049
2050 /* ########################## FPU functions #################################### */
2051 /**
2052 \ingroup CMSIS_Core_FunctionInterface
2053 \defgroup CMSIS_Core_FpuFunctions FPU Functions
2054 \brief Function that provides FPU type.
2055 @{
2056 */
2057
2058 /**
2059 \brief get FPU type
2060 \details returns the FPU type
2061 \returns
2062 - \b 0: No FPU
2063 - \b 1: Single precision FPU
2064 - \b 2: Double + Single precision FPU
2065 */
SCB_GetFPUType(void)2066 __STATIC_INLINE uint32_t SCB_GetFPUType(void)
2067 {
2068 return 0U; /* No FPU */
2069 }
2070
2071
2072 /*@} end of CMSIS_Core_FpuFunctions */
2073
2074
2075
2076 /* ########################## SAU functions #################################### */
2077 /**
2078 \ingroup CMSIS_Core_FunctionInterface
2079 \defgroup CMSIS_Core_SAUFunctions SAU Functions
2080 \brief Functions that configure the SAU.
2081 @{
2082 */
2083
2084 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2085
2086 /**
2087 \brief Enable SAU
2088 \details Enables the Security Attribution Unit (SAU).
2089 */
TZ_SAU_Enable(void)2090 __STATIC_INLINE void TZ_SAU_Enable(void)
2091 {
2092 SAU->CTRL |= (SAU_CTRL_ENABLE_Msk);
2093 }
2094
2095
2096
2097 /**
2098 \brief Disable SAU
2099 \details Disables the Security Attribution Unit (SAU).
2100 */
TZ_SAU_Disable(void)2101 __STATIC_INLINE void TZ_SAU_Disable(void)
2102 {
2103 SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
2104 }
2105
2106 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2107
2108 /*@} end of CMSIS_Core_SAUFunctions */
2109
2110
2111
2112
2113 /* ################################## Debug Control function ############################################ */
2114 /**
2115 \ingroup CMSIS_Core_FunctionInterface
2116 \defgroup CMSIS_Core_DCBFunctions Debug Control Functions
2117 \brief Functions that access the Debug Control Block.
2118 @{
2119 */
2120
2121
2122 /**
2123 \brief Set Debug Authentication Control Register
2124 \details writes to Debug Authentication Control register.
2125 \param [in] value value to be writen.
2126 */
DCB_SetAuthCtrl(uint32_t value)2127 __STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value)
2128 {
2129 __DSB();
2130 __ISB();
2131 DCB->DAUTHCTRL = value;
2132 __DSB();
2133 __ISB();
2134 }
2135
2136
2137 /**
2138 \brief Get Debug Authentication Control Register
2139 \details Reads Debug Authentication Control register.
2140 \return Debug Authentication Control Register.
2141 */
DCB_GetAuthCtrl(void)2142 __STATIC_INLINE uint32_t DCB_GetAuthCtrl(void)
2143 {
2144 return (DCB->DAUTHCTRL);
2145 }
2146
2147
2148 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2149 /**
2150 \brief Set Debug Authentication Control Register (non-secure)
2151 \details writes to non-secure Debug Authentication Control register when in secure state.
2152 \param [in] value value to be writen
2153 */
TZ_DCB_SetAuthCtrl_NS(uint32_t value)2154 __STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value)
2155 {
2156 __DSB();
2157 __ISB();
2158 DCB_NS->DAUTHCTRL = value;
2159 __DSB();
2160 __ISB();
2161 }
2162
2163
2164 /**
2165 \brief Get Debug Authentication Control Register (non-secure)
2166 \details Reads non-secure Debug Authentication Control register when in secure state.
2167 \return Debug Authentication Control Register.
2168 */
TZ_DCB_GetAuthCtrl_NS(void)2169 __STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void)
2170 {
2171 return (DCB_NS->DAUTHCTRL);
2172 }
2173 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2174
2175 /*@} end of CMSIS_Core_DCBFunctions */
2176
2177
2178
2179
2180 /* ################################## Debug Identification function ############################################ */
2181 /**
2182 \ingroup CMSIS_Core_FunctionInterface
2183 \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions
2184 \brief Functions that access the Debug Identification Block.
2185 @{
2186 */
2187
2188
2189 /**
2190 \brief Get Debug Authentication Status Register
2191 \details Reads Debug Authentication Status register.
2192 \return Debug Authentication Status Register.
2193 */
DIB_GetAuthStatus(void)2194 __STATIC_INLINE uint32_t DIB_GetAuthStatus(void)
2195 {
2196 return (DIB->DAUTHSTATUS);
2197 }
2198
2199
2200 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2201 /**
2202 \brief Get Debug Authentication Status Register (non-secure)
2203 \details Reads non-secure Debug Authentication Status register when in secure state.
2204 \return Debug Authentication Status Register.
2205 */
TZ_DIB_GetAuthStatus_NS(void)2206 __STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void)
2207 {
2208 return (DIB_NS->DAUTHSTATUS);
2209 }
2210 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2211
2212 /*@} end of CMSIS_Core_DCBFunctions */
2213
2214
2215
2216
2217 /* ################################## SysTick function ############################################ */
2218 /**
2219 \ingroup CMSIS_Core_FunctionInterface
2220 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
2221 \brief Functions that configure the System.
2222 @{
2223 */
2224
2225 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
2226
2227 /**
2228 \brief System Tick Configuration
2229 \details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
2230 Counter is in free running mode to generate periodic interrupts.
2231 \param [in] ticks Number of ticks between two interrupts.
2232 \return 0 Function succeeded.
2233 \return 1 Function failed.
2234 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2235 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
2236 must contain a vendor-specific implementation of this function.
2237 */
SysTick_Config(uint32_t ticks)2238 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
2239 {
2240 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2241 {
2242 return (1UL); /* Reload value impossible */
2243 }
2244
2245 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2246 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2247 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
2248 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2249 SysTick_CTRL_TICKINT_Msk |
2250 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2251 return (0UL); /* Function successful */
2252 }
2253
2254 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
2255 /**
2256 \brief System Tick Configuration (non-secure)
2257 \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
2258 Counter is in free running mode to generate periodic interrupts.
2259 \param [in] ticks Number of ticks between two interrupts.
2260 \return 0 Function succeeded.
2261 \return 1 Function failed.
2262 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
2263 function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
2264 must contain a vendor-specific implementation of this function.
2265
2266 */
TZ_SysTick_Config_NS(uint32_t ticks)2267 __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
2268 {
2269 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
2270 {
2271 return (1UL); /* Reload value impossible */
2272 }
2273
2274 SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
2275 TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
2276 SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
2277 SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
2278 SysTick_CTRL_TICKINT_Msk |
2279 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
2280 return (0UL); /* Function successful */
2281 }
2282 #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
2283
2284 #endif
2285
2286 /*@} end of CMSIS_Core_SysTickFunctions */
2287
2288
2289
2290
2291 #ifdef __cplusplus
2292 }
2293 #endif
2294
2295 #endif /* __CORE_CM23_H_DEPENDANT */
2296
2297 #endif /* __CMSIS_GENERIC */
2298
