1 /**************************************************************************//** 2 * @file core_ca55.h 3 * @brief CMSIS Cortex-A55 Core Peripheral Access Layer Header File 4 * @version V1.0.0 5 * @date Nov. 2022 6 ******************************************************************************/ 7 /* 8 * Copyright (c) 2021 Arm Limited. All rights reserved. 9 * Copyright 2021,2023 NXP 10 * 11 * SPDX-License-Identifier: Apache-2.0 12 * 13 * Licensed under the Apache License, Version 2.0 (the License); you may 14 * not use this file except in compliance with the License. 15 * You may obtain a copy of the License at 16 * 17 * www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 21 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 */ 25 26 #if defined ( __ICCARM__ ) 27 #pragma system_include /* treat file as system include file for MISRA check */ 28 #elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 29 #pragma clang system_header /* treat file as system include file */ 30 #endif 31 32 #ifndef __CORE_CA55_H_GENERIC 33 #define __CORE_CA55_H_GENERIC 34 35 #include <stdint.h> 36 #include <string.h> 37 38 #ifdef __cplusplus 39 extern "C" { 40 #endif 41 42 /******************************************************************************* 43 * CMSIS definitions 44 ******************************************************************************/ 45 46 #define __CORTEX_Axx (55U) /*!< Cortex-Axx Core */ 47 48 /* check device defines and use defaults */ 49 #if defined __CHECK_DEVICE_DEFINES 50 #ifndef __CA55_REV 51 #define __CA55_REV 0x0000U 52 #warning "__CA55_REV not defined in device header file; using default!" 53 #endif 54 55 #ifndef __CACHE_PRESENT 56 #define __CACHE_PRESENT 1U 57 #warning "__CACHE_PRESENT not defined in device header file; using default!" 58 #endif 59 60 #ifndef __FPU_PRESENT 61 #define __FPU_PRESENT 1U 62 #define __FPU_USED 1U 63 #warning "__FPU_PRESENT not defined in device header file; using default!" 64 #endif 65 66 #ifndef __GIC_PRESENT 67 #define __GIC_PRESENT 1U 68 #warning "__GIC_PRESENT not defined in device header file; using default!" 69 #endif 70 71 #ifndef __MMU_PRESENT 72 #define __MMU_PRESENT 1U 73 #warning "__MMU_PRESENT not defined in device header file; using default!" 74 #endif 75 #endif 76 77 #include "cmsis_compiler.h" /* Core Instruction and Function Access */ 78 79 #ifdef __cplusplus 80 } 81 #endif 82 83 #endif /* __CORE_CA55_H_GENERIC */ 84 85 #ifndef __CMSIS_GENERIC 86 87 #ifndef __CORE_CA55_H_DEPENDANT 88 #define __CORE_CA55_H_DEPENDANT 89 90 #ifdef __cplusplus 91 extern "C" { 92 #endif 93 94 /******************************************************************************* 95 * Cache Functions 96 ******************************************************************************/ 97 98 #define ICACHE_LINE_SIZE (64) 99 #define DCACHE_LINE_SIZE (64) 100 101 #include "core_common.h" 102 103 #ifdef __cplusplus 104 } 105 #endif 106 107 #endif /* __CORE_CA55_H_DEPENDANT */ 108 109 #endif /* __CMSIS_GENERIC */ 110
