1 /* 2 * Copyright (c) 2016-2020 Nordic Semiconductor ASA 3 * Copyright (c) 2016 Vinayak Kariappa Chettimada 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 #if defined(CONFIG_BT_CTLR_DEBUG_PINS) || \ 9 defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) 10 #if defined(CONFIG_BOARD_NRF5340DK) 11 #define DEBUG_PORT NRF_P1 12 #define DEBUG_PIN_IDX0 0 13 #define DEBUG_PIN_IDX1 1 14 #define DEBUG_PIN_IDX2 4 15 #define DEBUG_PIN_IDX3 5 16 #define DEBUG_PIN_IDX4 6 17 #define DEBUG_PIN_IDX5 7 18 #define DEBUG_PIN_IDX6 8 19 #define DEBUG_PIN_IDX7 9 20 #define DEBUG_PIN_IDX8 10 21 #define DEBUG_PIN_IDX9 11 22 #define DEBUG_PIN0 BIT(DEBUG_PIN_IDX0) 23 #define DEBUG_PIN1 BIT(DEBUG_PIN_IDX1) 24 #define DEBUG_PIN2 BIT(DEBUG_PIN_IDX2) 25 #define DEBUG_PIN3 BIT(DEBUG_PIN_IDX3) 26 #define DEBUG_PIN4 BIT(DEBUG_PIN_IDX4) 27 #define DEBUG_PIN5 BIT(DEBUG_PIN_IDX5) 28 #define DEBUG_PIN6 BIT(DEBUG_PIN_IDX6) 29 #define DEBUG_PIN7 BIT(DEBUG_PIN_IDX7) 30 #define DEBUG_PIN8 BIT(DEBUG_PIN_IDX8) 31 #define DEBUG_PIN9 BIT(DEBUG_PIN_IDX9) 32 #if defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP) || \ 33 (defined(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP_NS) && defined(CONFIG_BUILD_WITH_TFM)) 34 #include <soc_secure.h> 35 #define DEBUG_SETUP() \ 36 do { \ 37 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX0, NRF_GPIO_PIN_SEL_NETWORK); \ 38 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX1, NRF_GPIO_PIN_SEL_NETWORK); \ 39 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX2, NRF_GPIO_PIN_SEL_NETWORK); \ 40 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX3, NRF_GPIO_PIN_SEL_NETWORK); \ 41 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX4, NRF_GPIO_PIN_SEL_NETWORK); \ 42 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX5, NRF_GPIO_PIN_SEL_NETWORK); \ 43 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX6, NRF_GPIO_PIN_SEL_NETWORK); \ 44 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX7, NRF_GPIO_PIN_SEL_NETWORK); \ 45 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX8, NRF_GPIO_PIN_SEL_NETWORK); \ 46 soc_secure_gpio_pin_mcu_select(32 + DEBUG_PIN_IDX9, NRF_GPIO_PIN_SEL_NETWORK); \ 47 } while (0) 48 #else 49 #define DEBUG_SETUP() 50 #endif /* CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP */ 51 #elif defined(CONFIG_BOARD_NRF52840DK) || defined(CONFIG_BOARD_NRF52833DK) 52 #define DEBUG_PORT NRF_P1 53 #define DEBUG_PIN0 BIT(1) 54 #define DEBUG_PIN1 BIT(2) 55 #define DEBUG_PIN2 BIT(3) 56 #define DEBUG_PIN3 BIT(4) 57 #define DEBUG_PIN4 BIT(5) 58 #define DEBUG_PIN5 BIT(6) 59 #define DEBUG_PIN6 BIT(7) 60 #define DEBUG_PIN7 BIT(8) 61 #define DEBUG_PIN8 BIT(10) 62 #define DEBUG_PIN9 BIT(11) 63 #define DEBUG_SETUP() 64 #elif defined(CONFIG_BOARD_NRF52DK) 65 #define DEBUG_PORT NRF_GPIO 66 #define DEBUG_PIN0 BIT(11) 67 #define DEBUG_PIN1 BIT(12) 68 #define DEBUG_PIN2 BIT(13) 69 #define DEBUG_PIN3 BIT(14) 70 #define DEBUG_PIN4 BIT(15) 71 #define DEBUG_PIN5 BIT(16) 72 #define DEBUG_PIN6 BIT(17) 73 #define DEBUG_PIN7 BIT(18) 74 #define DEBUG_PIN8 BIT(19) 75 #define DEBUG_PIN9 BIT(20) 76 #define DEBUG_SETUP() 77 #elif defined(CONFIG_BOARD_NRF51DK) 78 #define DEBUG_PORT NRF_GPIO 79 #define DEBUG_PIN0 BIT(12) 80 #define DEBUG_PIN1 BIT(13) 81 #define DEBUG_PIN2 BIT(14) 82 #define DEBUG_PIN3 BIT(15) 83 #define DEBUG_PIN4 BIT(16) 84 #define DEBUG_PIN5 BIT(17) 85 #define DEBUG_PIN6 BIT(18) 86 #define DEBUG_PIN7 BIT(19) 87 #define DEBUG_PIN8 BIT(20) 88 #define DEBUG_PIN9 BIT(23) 89 #define DEBUG_SETUP() 90 #else 91 #error BT_CTLR_DEBUG_PINS not supported on this board. 92 #endif 93 94 #define DEBUG_PIN_MASK (DEBUG_PIN0 | DEBUG_PIN1 | DEBUG_PIN2 | DEBUG_PIN3 | \ 95 DEBUG_PIN4 | DEBUG_PIN5 | DEBUG_PIN6 | DEBUG_PIN7 | \ 96 DEBUG_PIN8 | DEBUG_PIN9) 97 #define DEBUG_CLOSE_MASK (DEBUG_PIN3 | DEBUG_PIN4 | DEBUG_PIN5 | DEBUG_PIN6) 98 99 /* below are some interesting macros referenced by controller 100 * which can be defined to SoC's GPIO toggle to observe/debug the 101 * controller's runtime behavior. 102 */ 103 #define DEBUG_INIT() \ 104 do { \ 105 DEBUG_PORT->DIRSET = DEBUG_PIN_MASK; \ 106 DEBUG_PORT->OUTCLR = DEBUG_PIN_MASK; \ 107 } while (false) 108 109 #define DEBUG_CPU_SLEEP(flag) \ 110 do { \ 111 if (flag) { \ 112 DEBUG_PORT->OUTSET = DEBUG_PIN0; \ 113 DEBUG_PORT->OUTCLR = DEBUG_PIN0; \ 114 } else { \ 115 DEBUG_PORT->OUTCLR = DEBUG_PIN0; \ 116 DEBUG_PORT->OUTSET = DEBUG_PIN0; \ 117 } \ 118 } while (false) 119 120 #define DEBUG_TICKER_ISR(flag) \ 121 do { \ 122 if (flag) { \ 123 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 124 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 125 } else { \ 126 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 127 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 128 } \ 129 } while (false) 130 131 #define DEBUG_TICKER_TASK(flag) \ 132 do { \ 133 if (flag) { \ 134 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 135 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 136 } else { \ 137 DEBUG_PORT->OUTSET = DEBUG_PIN1; \ 138 DEBUG_PORT->OUTCLR = DEBUG_PIN1; \ 139 } \ 140 } while (false) 141 142 #define DEBUG_TICKER_JOB(flag) \ 143 do { \ 144 if (flag) { \ 145 DEBUG_PORT->OUTCLR = DEBUG_PIN2; \ 146 DEBUG_PORT->OUTSET = DEBUG_PIN2; \ 147 } else { \ 148 DEBUG_PORT->OUTSET = DEBUG_PIN2; \ 149 DEBUG_PORT->OUTCLR = DEBUG_PIN2; \ 150 } \ 151 } while (false) 152 153 #define DEBUG_RADIO_ISR(flag) \ 154 do { \ 155 if (flag) { \ 156 DEBUG_PORT->OUTCLR = DEBUG_PIN7; \ 157 DEBUG_PORT->OUTSET = DEBUG_PIN7; \ 158 } else { \ 159 DEBUG_PORT->OUTSET = DEBUG_PIN7; \ 160 DEBUG_PORT->OUTCLR = DEBUG_PIN7; \ 161 } \ 162 } while (false) 163 164 #define DEBUG_RADIO_XTAL(flag) \ 165 do { \ 166 if (flag) { \ 167 DEBUG_PORT->OUTCLR = DEBUG_PIN8; \ 168 DEBUG_PORT->OUTSET = DEBUG_PIN8; \ 169 } else { \ 170 DEBUG_PORT->OUTSET = DEBUG_PIN8; \ 171 DEBUG_PORT->OUTCLR = DEBUG_PIN8; \ 172 } \ 173 } while (false) 174 175 #define DEBUG_RADIO_ACTIVE(flag) \ 176 do { \ 177 if (flag) { \ 178 DEBUG_PORT->OUTCLR = DEBUG_PIN9; \ 179 DEBUG_PORT->OUTSET = DEBUG_PIN9; \ 180 } else { \ 181 DEBUG_PORT->OUTSET = DEBUG_PIN9; \ 182 DEBUG_PORT->OUTCLR = DEBUG_PIN9; \ 183 } \ 184 } while (false) 185 186 #define DEBUG_RADIO_CLOSE(flag) \ 187 do { \ 188 if (flag) { \ 189 DEBUG_PORT->OUTCLR = 0x00000000; \ 190 DEBUG_PORT->OUTSET = 0x00000000; \ 191 } else { \ 192 DEBUG_PORT->OUTCLR = DEBUG_CLOSE_MASK; \ 193 } \ 194 } while (false) 195 196 #define DEBUG_RADIO_PREPARE_A(flag) \ 197 do { \ 198 if (flag) { \ 199 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 200 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 201 } else { \ 202 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 203 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 204 } \ 205 } while (false) 206 207 #define DEBUG_RADIO_START_A(flag) \ 208 do { \ 209 if (flag) { \ 210 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 211 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 212 } else { \ 213 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 214 DEBUG_PORT->OUTSET = DEBUG_PIN3; \ 215 } \ 216 } while (false) 217 218 #define DEBUG_RADIO_CLOSE_A(flag) \ 219 do { \ 220 if (flag) { \ 221 DEBUG_PORT->OUTCLR = 0x00000000; \ 222 DEBUG_PORT->OUTSET = 0x00000000; \ 223 } else { \ 224 DEBUG_PORT->OUTCLR = DEBUG_PIN3; \ 225 } \ 226 } while (false) 227 228 #define DEBUG_RADIO_PREPARE_S(flag) \ 229 do { \ 230 if (flag) { \ 231 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 232 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 233 } else { \ 234 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 235 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 236 } \ 237 } while (false) 238 239 #define DEBUG_RADIO_START_S(flag) \ 240 do { \ 241 if (flag) { \ 242 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 243 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 244 } else { \ 245 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 246 DEBUG_PORT->OUTSET = DEBUG_PIN4; \ 247 } \ 248 } while (false) 249 250 #define DEBUG_RADIO_CLOSE_S(flag) \ 251 do { \ 252 if (flag) { \ 253 DEBUG_PORT->OUTCLR = 0x00000000; \ 254 DEBUG_PORT->OUTSET = 0x00000000; \ 255 } else { \ 256 DEBUG_PORT->OUTCLR = DEBUG_PIN4; \ 257 } \ 258 } while (false) 259 260 #define DEBUG_RADIO_PREPARE_O(flag) \ 261 do { \ 262 if (flag) { \ 263 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 264 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 265 } else { \ 266 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 267 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 268 } \ 269 } while (false) 270 271 #define DEBUG_RADIO_START_O(flag) \ 272 do { \ 273 if (flag) { \ 274 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 275 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 276 } else { \ 277 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 278 DEBUG_PORT->OUTSET = DEBUG_PIN5; \ 279 } \ 280 } while (false) 281 282 #define DEBUG_RADIO_CLOSE_O(flag) \ 283 do { \ 284 if (flag) { \ 285 DEBUG_PORT->OUTCLR = 0x00000000; \ 286 DEBUG_PORT->OUTSET = 0x00000000; \ 287 } else { \ 288 DEBUG_PORT->OUTCLR = DEBUG_PIN5; \ 289 } \ 290 } while (false) 291 292 #define DEBUG_RADIO_PREPARE_M(flag) \ 293 do { \ 294 if (flag) { \ 295 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 296 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 297 } else { \ 298 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 299 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 300 } \ 301 } while (false) 302 303 #define DEBUG_RADIO_START_M(flag) \ 304 do { \ 305 if (flag) { \ 306 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 307 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 308 } else { \ 309 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 310 DEBUG_PORT->OUTSET = DEBUG_PIN6; \ 311 } \ 312 } while (false) 313 314 #define DEBUG_RADIO_CLOSE_M(flag) \ 315 do { \ 316 if (flag) { \ 317 DEBUG_PORT->OUTCLR = 0x00000000; \ 318 DEBUG_PORT->OUTSET = 0x00000000; \ 319 } else { \ 320 DEBUG_PORT->OUTCLR = DEBUG_PIN6; \ 321 } \ 322 } while (false) 323 324 #else 325 #define DEBUG_SETUP() 326 #define DEBUG_INIT() 327 #define DEBUG_CPU_SLEEP(flag) 328 #define DEBUG_TICKER_ISR(flag) 329 #define DEBUG_TICKER_TASK(flag) 330 #define DEBUG_TICKER_JOB(flag) 331 #define DEBUG_RADIO_ISR(flag) 332 #define DEBUG_RADIO_HCTO(flag) 333 #define DEBUG_RADIO_XTAL(flag) 334 #define DEBUG_RADIO_ACTIVE(flag) 335 #define DEBUG_RADIO_CLOSE(flag) 336 #define DEBUG_RADIO_PREPARE_A(flag) 337 #define DEBUG_RADIO_START_A(flag) 338 #define DEBUG_RADIO_CLOSE_A(flag) 339 #define DEBUG_RADIO_PREPARE_S(flag) 340 #define DEBUG_RADIO_START_S(flag) 341 #define DEBUG_RADIO_CLOSE_S(flag) 342 #define DEBUG_RADIO_PREPARE_O(flag) 343 #define DEBUG_RADIO_START_O(flag) 344 #define DEBUG_RADIO_CLOSE_O(flag) 345 #define DEBUG_RADIO_PREPARE_M(flag) 346 #define DEBUG_RADIO_START_M(flag) 347 #define DEBUG_RADIO_CLOSE_M(flag) 348 #endif /* CONFIG_BT_CTLR_DEBUG_PINS */ 349 350 #if defined(CONFIG_BT_CTLR_DEBUG_PINS) || \ 351 defined(CONFIG_BT_CTLR_DEBUG_PINS_CPUAPP) 352 #define DEBUG_COEX_PORT NRF_P1 353 #define DEBUG_COEX_PIN_GRANT BIT(12) 354 #define DEBUG_COEX_PIN_IRQ BIT(13) 355 #define DEBUG_COEX_PIN_MASK (DEBUG_COEX_PIN_IRQ | DEBUG_COEX_PIN_GRANT) 356 #define DEBUG_COEX_INIT() \ 357 do { \ 358 DEBUG_COEX_PORT->DIRSET = DEBUG_COEX_PIN_MASK; \ 359 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_MASK; \ 360 } while (0) 361 362 #define DEBUG_COEX_GRANT(flag) \ 363 do { \ 364 if (flag) { \ 365 DEBUG_COEX_PORT->OUTSET = DEBUG_COEX_PIN_GRANT; \ 366 } else { \ 367 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_GRANT; \ 368 } \ 369 } while (0) 370 371 372 #define DEBUG_COEX_IRQ(flag) \ 373 do { \ 374 if (flag) { \ 375 DEBUG_COEX_PORT->OUTSET = DEBUG_COEX_PIN_IRQ; \ 376 } else { \ 377 DEBUG_COEX_PORT->OUTCLR = DEBUG_COEX_PIN_IRQ; \ 378 } \ 379 } while (0) 380 #else 381 #define DEBUG_COEX_INIT() 382 #define DEBUG_COEX_GRANT(flag) 383 #define DEBUG_COEX_IRQ(flag) 384 #endif /* CONFIG_BT_CTLR_DEBUG_PINS */ 385
