1 /*
2 * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include <stddef.h>
7 #include <stdlib.h>
8 #include <stdio.h>
9 #include <string.h>
10
11 #include "esp_random.h"
12 #include "esp_heap_caps.h"
13 #include "esp_heap_caps_init.h"
14 #include "esp_mac.h"
15
16 #include "sdkconfig.h"
17
18 #if CONFIG_BT_NIMBLE_ENABLED
19 #include "nimble/nimble_port.h"
20 #endif // CONFIG_BT_NIMBLE_ENABLED
21 #include "nimble/nimble_port_freertos.h"
22 #include "esp_private/esp_modem_clock.h"
23
24 #ifdef ESP_PLATFORM
25 #include "esp_log.h"
26 #endif // ESP_PLATFORM
27
28 #if CONFIG_SW_COEXIST_ENABLE
29 #include "private/esp_coexist_internal.h"
30 #endif // CONFIG_SW_COEXIST_ENABLE
31
32 #include "nimble/nimble_npl_os.h"
33 #include "esp_hci_transport.h"
34 #include "os/endian.h"
35
36 #include "esp_bt.h"
37 #include "esp_intr_alloc.h"
38 #include "esp_sleep.h"
39 #include "esp_pm.h"
40 #include "esp_phy_init.h"
41 #include "esp_private/periph_ctrl.h"
42 #include "bt_osi_mem.h"
43
44 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
45 #include "esp_private/sleep_modem.h"
46 #include "esp_private/sleep_retention.h"
47 #endif // CONFIG_FREERTOS_USE_TICKLESS_IDLE
48
49 #include "freertos/FreeRTOS.h"
50 #include "freertos/task.h"
51
52 #include "esp_private/periph_ctrl.h"
53 #include "esp_sleep.h"
54 #include "soc/rtc.h"
55 /* Macro definition
56 ************************************************************************
57 */
58 #define NIMBLE_PORT_LOG_TAG "BLE_INIT"
59 #define OSI_COEX_VERSION 0x00010006
60 #define OSI_COEX_MAGIC_VALUE 0xFADEBEAD
61
62 #define EXT_FUNC_VERSION 0x20240422
63 #define EXT_FUNC_MAGIC_VALUE 0xA5A5A5A5
64
65 #define BT_ASSERT_PRINT ets_printf
66
67 /* Types definition
68 ************************************************************************
69 */
70 struct osi_coex_funcs_t {
71 uint32_t _magic;
72 uint32_t _version;
73 void (* _coex_wifi_sleep_set)(bool sleep);
74 int (* _coex_core_ble_conn_dyn_prio_get)(bool *low, bool *high);
75 void (* _coex_schm_status_bit_set)(uint32_t type, uint32_t status);
76 void (* _coex_schm_status_bit_clear)(uint32_t type, uint32_t status);
77 };
78
79 struct ext_funcs_t {
80 uint32_t ext_version;
81 int (*_esp_intr_alloc)(int source, int flags, intr_handler_t handler, void *arg, void **ret_handle);
82 int (*_esp_intr_free)(void **ret_handle);
83 void *(* _malloc)(size_t size);
84 void (*_free)(void *p);
85 int (* _task_create)(void *task_func, const char *name, uint32_t stack_depth, void *param,
86 uint32_t prio, void *task_handle, uint32_t core_id);
87 void (* _task_delete)(void *task_handle);
88 void (*_osi_assert)(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
89 uint32_t (* _os_random)(void);
90 int (* _ecc_gen_key_pair)(uint8_t *public, uint8_t *priv);
91 int (* _ecc_gen_dh_key)(const uint8_t *remote_pub_key_x, const uint8_t *remote_pub_key_y,
92 const uint8_t *local_priv_key, uint8_t *dhkey);
93 void (* _esp_reset_rpa_moudle)(void);
94 uint32_t magic;
95 };
96
97 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
98 typedef void (*interface_func_t) (uint32_t len, const uint8_t*addr, bool end);
99 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
100 /* External functions or variables
101 ************************************************************************
102 */
103 extern int ble_osi_coex_funcs_register(struct osi_coex_funcs_t *coex_funcs);
104 extern int r_ble_controller_init(esp_bt_controller_config_t *cfg);
105 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
106 extern int r_ble_log_init_async(interface_func_t bt_controller_log_interface, bool task_create, uint8_t buffers, uint32_t *bufs_size);
107 extern int r_ble_log_deinit_async(void);
108 extern void r_ble_log_async_select_dump_buffers(uint8_t buffers);
109 extern void r_ble_log_async_output_dump_all(bool output);
110 extern void esp_panic_handler_reconfigure_wdts(uint32_t timeout_ms);
111 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
112 extern int r_ble_controller_deinit(void);
113 extern int r_ble_controller_enable(uint8_t mode);
114 extern int r_ble_controller_disable(void);
115 extern int esp_register_ext_funcs (struct ext_funcs_t *);
116 extern void esp_unregister_ext_funcs (void);
117 extern int r_esp_ble_ll_set_public_addr(const uint8_t *addr);
118 extern int esp_register_npl_funcs (struct npl_funcs_t *p_npl_func);
119 extern void esp_unregister_npl_funcs (void);
120 extern void npl_freertos_mempool_deinit(void);
121 extern uint32_t r_os_cputime_get32(void);
122 extern uint32_t r_os_cputime_ticks_to_usecs(uint32_t ticks);
123 extern void r_ble_lll_rfmgmt_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg,
124 void *w_arg, uint32_t us_to_enabled);
125 extern void r_ble_rtc_wake_up_state_clr(void);
126 extern int os_msys_init(void);
127 extern void os_msys_deinit(void);
128 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
129 extern sleep_retention_entries_config_t *r_esp_ble_mac_retention_link_get(uint8_t *size, uint8_t extra);
130 extern void r_esp_ble_set_wakeup_overhead(uint32_t overhead);
131 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
132 #if CONFIG_PM_ENABLE
133 extern void r_esp_ble_stop_wakeup_timing(void);
134 #endif // CONFIG_PM_ENABLE
135 extern void r_esp_ble_change_rtc_freq(uint32_t freq);
136 extern int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x,
137 const uint8_t *peer_pub_key_y,
138 const uint8_t *our_priv_key, uint8_t *out_dhkey);
139 extern int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv);
140 extern int r_ble_txpwr_set(esp_ble_enhanced_power_type_t power_type, uint16_t handle, int power_level);
141 extern int r_ble_txpwr_get(esp_ble_enhanced_power_type_t power_type, uint16_t handle);
142 extern int r_ble_get_npl_element_info(esp_bt_controller_config_t *cfg, ble_npl_count_info_t * npl_info);
143 extern char *ble_controller_get_compile_version(void);
144 extern int esp_ble_register_bb_funcs(void);
145 extern void esp_ble_unregister_bb_funcs(void);
146 extern uint32_t _bt_bss_start;
147 extern uint32_t _bt_bss_end;
148 extern uint32_t _bt_controller_bss_start;
149 extern uint32_t _bt_controller_bss_end;
150 extern uint32_t _bt_data_start;
151 extern uint32_t _bt_data_end;
152 extern uint32_t _bt_controller_data_start;
153 extern uint32_t _bt_controller_data_end;
154
155 /* Local Function Declaration
156 *********************************************************************
157 */
158 static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status);
159 static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status);
160 static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
161 void *param, uint32_t prio, void *task_handle, uint32_t core_id);
162 static void task_delete_wrapper(void *task_handle);
163 static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
164 void *arg, void **ret_handle_in);
165 static int esp_intr_free_wrapper(void **ret_handle);
166 static void osi_assert_wrapper(const uint32_t ln, const char *fn, uint32_t param1, uint32_t param2);
167 static uint32_t osi_random_wrapper(void);
168 static void esp_reset_rpa_moudle(void);
169 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv);
170 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
171 const uint8_t *our_priv_key, uint8_t *out_dhkey);
172 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
173 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end);
174 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
175 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void);
176 #endif // #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
177 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
178 /* Local variable definition
179 ***************************************************************************
180 */
181 /* Static variable declare */
182 static DRAM_ATTR esp_bt_controller_status_t ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
183 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
184 const static uint32_t log_bufs_size[] = {CONFIG_BT_LE_LOG_CTRL_BUF1_SIZE, CONFIG_BT_LE_LOG_HCI_BUF_SIZE, CONFIG_BT_LE_LOG_CTRL_BUF2_SIZE};
185 enum log_out_mode {
186 LOG_DUMP_MEMORY,
187 LOG_ASYNC_OUT,
188 LOG_STORAGE_TO_FLASH,
189 };
190
191 bool log_is_inited = false;
192 #if CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
193 uint8_t log_output_mode = LOG_DUMP_MEMORY;
194 #else
195 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
196 uint8_t log_output_mode = LOG_STORAGE_TO_FLASH;
197 #else
198 uint8_t log_output_mode = LOG_ASYNC_OUT;
199 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
200 #endif // CONFIG_BT_LE_CONTROLLER_LOG_DUMP_ONLY
201
esp_bt_log_output_mode_set(uint8_t output_mode)202 void esp_bt_log_output_mode_set(uint8_t output_mode)
203 {
204 log_output_mode = output_mode;
205 }
206
esp_bt_log_output_mode_get(void)207 uint8_t esp_bt_log_output_mode_get(void)
208 {
209 return log_output_mode;
210 }
211
esp_bt_controller_log_init(uint8_t log_output_mode)212 esp_err_t esp_bt_controller_log_init(uint8_t log_output_mode)
213 {
214 esp_err_t ret = ESP_OK;
215 interface_func_t bt_controller_log_interface;
216 bt_controller_log_interface = esp_bt_controller_log_interface;
217 bool task_create;
218 uint8_t buffers = 0;
219
220 if (log_is_inited) {
221 return ret;
222 }
223
224 #if CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
225 buffers |= ESP_BLE_LOG_BUF_CONTROLLER;
226 #endif // CONFIG_BT_LE_CONTROLLER_LOG_CTRL_ENABLED
227 #if CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
228 buffers |= ESP_BLE_LOG_BUF_HCI;
229 #endif // CONFIG_BT_LE_CONTROLLER_LOG_HCI_ENABLED
230
231 switch (log_output_mode) {
232 case LOG_DUMP_MEMORY:
233 task_create = false;
234 break;
235 case LOG_ASYNC_OUT:
236 case LOG_STORAGE_TO_FLASH:
237 task_create = true;
238 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
239 if (log_output_mode == LOG_STORAGE_TO_FLASH) {
240 esp_bt_ctrl_log_partition_get_and_erase_first_block();
241 }
242 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
243 break;
244 default:
245 assert(0);
246 }
247
248 ret = r_ble_log_init_async(bt_controller_log_interface, task_create, buffers, (uint32_t *)log_bufs_size);
249 if (ret == ESP_OK) {
250 log_is_inited = true;
251 }
252 return ret;
253 }
254
esp_bt_ontroller_log_deinit(void)255 void esp_bt_ontroller_log_deinit(void)
256 {
257 r_ble_log_deinit_async();
258 log_is_inited = false;
259 }
260
261 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
262 #include "esp_partition.h"
263 #include "hal/wdt_hal.h"
264
265 #define MAX_STORAGE_SIZE (CONFIG_BT_LE_CONTROLLER_LOG_PARTITION_SIZE)
266 #define BLOCK_SIZE (4096)
267 #define THRESHOLD (3072)
268 #define PARTITION_NAME "bt_ctrl_log"
269
270 static const esp_partition_t *log_partition;
271 static uint32_t write_index = 0;
272 static uint32_t next_erase_index = BLOCK_SIZE;
273 static bool block_erased = false;
274 static bool stop_write = false;
275 static bool is_filled = false;
276
esp_bt_ctrl_log_partition_get_and_erase_first_block(void)277 static void esp_bt_ctrl_log_partition_get_and_erase_first_block(void)
278 {
279 log_partition = NULL;
280 assert(MAX_STORAGE_SIZE % BLOCK_SIZE == 0);
281 // Find the partition map in the partition table
282 log_partition = esp_partition_find_first(ESP_PARTITION_TYPE_DATA, ESP_PARTITION_SUBTYPE_ANY, PARTITION_NAME);
283 assert(log_partition != NULL);
284 // Prepare data to be read later using the mapped address
285 ESP_ERROR_CHECK(esp_partition_erase_range(log_partition, 0, BLOCK_SIZE));
286 write_index = 0;
287 next_erase_index = BLOCK_SIZE;
288 block_erased = false;
289 is_filled = false;
290 stop_write = false;
291 }
292
esp_bt_controller_log_storage(uint32_t len,const uint8_t * addr,bool end)293 static int esp_bt_controller_log_storage(uint32_t len, const uint8_t *addr, bool end)
294 {
295 if (len > MAX_STORAGE_SIZE) {
296 return -1;
297 }
298
299 if (stop_write) {
300 return 0;
301 }
302
303 if (((write_index) % BLOCK_SIZE) >= THRESHOLD && !block_erased) {
304 // esp_rom_printf("Ers nxt: %d,%d\n", next_erase_index, write_index);
305 esp_partition_erase_range(log_partition, next_erase_index, BLOCK_SIZE);
306 next_erase_index = (next_erase_index + BLOCK_SIZE) % MAX_STORAGE_SIZE;
307 block_erased = true;
308 }
309
310 if (((write_index + len) / BLOCK_SIZE) > (write_index / BLOCK_SIZE)) {
311 block_erased = false;
312 }
313
314 if (write_index + len <= MAX_STORAGE_SIZE) {
315 esp_partition_write(log_partition, write_index, addr, len);
316 write_index = (write_index + len) % MAX_STORAGE_SIZE;
317 } else {
318 uint32_t first_part_len = MAX_STORAGE_SIZE - write_index;
319 esp_partition_write(log_partition, write_index, addr, first_part_len);
320 esp_partition_write(log_partition, 0, addr + first_part_len, len - first_part_len);
321 write_index = len - first_part_len;
322 is_filled = true;
323 // esp_rom_printf("old idx: %d,%d\n",next_erase_index, write_index);
324 }
325
326 return 0;
327 }
328
esp_bt_read_ctrl_log_from_flash(bool output)329 void esp_bt_read_ctrl_log_from_flash(bool output)
330 {
331 esp_partition_mmap_handle_t mmap_handle;
332 uint32_t read_index;
333 const void *mapped_ptr;
334 const uint8_t *buffer;
335 uint32_t print_len;
336 uint32_t max_print_len;
337 esp_err_t err;
338
339 print_len = 0;
340 max_print_len = 4096;
341 err = esp_partition_mmap(log_partition, 0, MAX_STORAGE_SIZE, ESP_PARTITION_MMAP_DATA, &mapped_ptr, &mmap_handle);
342 if (err != ESP_OK) {
343 ESP_LOGE("FLASH", "Mmap failed: %s", esp_err_to_name(err));
344 return;
345 }
346
347 portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
348 portENTER_CRITICAL_SAFE(&spinlock);
349 esp_panic_handler_reconfigure_wdts(5000);
350 r_ble_log_async_output_dump_all(true);
351 esp_bt_ontroller_log_deinit();
352 stop_write = true;
353
354 buffer = (const uint8_t *)mapped_ptr;
355 esp_panic_handler_reconfigure_wdts(5000);
356 if (is_filled) {
357 read_index = next_erase_index;
358 } else {
359 read_index = 0;
360 }
361
362 esp_rom_printf("\r\nREAD_CHECK:%ld,%ld,%d\r\n",read_index, write_index, is_filled);
363 esp_rom_printf("\r\n[DUMP_START:");
364 while (read_index != write_index) {
365 esp_rom_printf("%02x ", buffer[read_index]);
366 if (print_len > max_print_len) {
367 esp_panic_handler_reconfigure_wdts(5000);
368 print_len = 0;
369 }
370
371 print_len++;
372 read_index = (read_index + 1) % MAX_STORAGE_SIZE;
373 }
374
375 esp_rom_printf(":DUMP_END]\r\n");
376 portEXIT_CRITICAL_SAFE(&spinlock);
377 esp_partition_munmap(mmap_handle);
378 err = esp_bt_controller_log_init(log_output_mode);
379 assert(err == ESP_OK);
380 }
381 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
382 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
383
384 /* This variable tells if BLE is running */
385 static bool s_ble_active = false;
386 #ifdef CONFIG_PM_ENABLE
387 static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
388 #endif // CONFIG_PM_ENABLE
389 static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
390
391 #define BLE_CONTROLLER_MALLOC_CAPS (MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT|MALLOC_CAP_DMA)
malloc_ble_controller_mem(size_t size)392 void *malloc_ble_controller_mem(size_t size)
393 {
394 return heap_caps_malloc(size, BLE_CONTROLLER_MALLOC_CAPS);
395 }
396
get_ble_controller_free_heap_size(void)397 uint32_t get_ble_controller_free_heap_size(void)
398 {
399 return heap_caps_get_free_size(BLE_CONTROLLER_MALLOC_CAPS);
400 }
401
402 #define BLE_RTC_DELAY_US_LIGHT_SLEEP (5100)
403 #define BLE_RTC_DELAY_US_MODEM_SLEEP (1500)
404
405 static const struct osi_coex_funcs_t s_osi_coex_funcs_ro = {
406 ._magic = OSI_COEX_MAGIC_VALUE,
407 ._version = OSI_COEX_VERSION,
408 ._coex_wifi_sleep_set = NULL,
409 ._coex_core_ble_conn_dyn_prio_get = NULL,
410 ._coex_schm_status_bit_set = coex_schm_status_bit_set_wrapper,
411 ._coex_schm_status_bit_clear = coex_schm_status_bit_clear_wrapper,
412 };
413
414 struct ext_funcs_t ext_funcs_ro = {
415 .ext_version = EXT_FUNC_VERSION,
416 ._esp_intr_alloc = esp_intr_alloc_wrapper,
417 ._esp_intr_free = esp_intr_free_wrapper,
418 ._malloc = bt_osi_mem_malloc_internal,
419 ._free = bt_osi_mem_free,
420 ._task_create = task_create_wrapper,
421 ._task_delete = task_delete_wrapper,
422 ._osi_assert = osi_assert_wrapper,
423 ._os_random = osi_random_wrapper,
424 ._ecc_gen_key_pair = esp_ecc_gen_key_pair,
425 ._ecc_gen_dh_key = esp_ecc_gen_dh_key,
426 ._esp_reset_rpa_moudle = esp_reset_rpa_moudle,
427 .magic = EXT_FUNC_MAGIC_VALUE,
428 };
429
esp_reset_rpa_moudle(void)430 static void IRAM_ATTR esp_reset_rpa_moudle(void)
431 {
432
433 }
434
osi_assert_wrapper(const uint32_t ln,const char * fn,uint32_t param1,uint32_t param2)435 static void IRAM_ATTR osi_assert_wrapper(const uint32_t ln, const char *fn,
436 uint32_t param1, uint32_t param2)
437 {
438 BT_ASSERT_PRINT("BLE assert: line %d in function %s, param: 0x%x, 0x%x", ln, fn, param1, param2);
439 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
440 esp_ble_controller_log_dump_all(true);
441 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
442 assert(0);
443 }
444
osi_random_wrapper(void)445 static uint32_t IRAM_ATTR osi_random_wrapper(void)
446 {
447 return esp_random();
448 }
449
coex_schm_status_bit_set_wrapper(uint32_t type,uint32_t status)450 static void coex_schm_status_bit_set_wrapper(uint32_t type, uint32_t status)
451 {
452 #if CONFIG_SW_COEXIST_ENABLE
453 coex_schm_status_bit_set(type, status);
454 #endif // CONFIG_SW_COEXIST_ENABLE
455 }
456
coex_schm_status_bit_clear_wrapper(uint32_t type,uint32_t status)457 static void coex_schm_status_bit_clear_wrapper(uint32_t type, uint32_t status)
458 {
459 #if CONFIG_SW_COEXIST_ENABLE
460 coex_schm_status_bit_clear(type, status);
461 #endif // CONFIG_SW_COEXIST_ENABLE
462 }
463
task_create_wrapper(void * task_func,const char * name,uint32_t stack_depth,void * param,uint32_t prio,void * task_handle,uint32_t core_id)464 static int task_create_wrapper(void *task_func, const char *name, uint32_t stack_depth,
465 void *param, uint32_t prio, void *task_handle, uint32_t core_id)
466 {
467 return (uint32_t)xTaskCreatePinnedToCore(task_func, name, stack_depth, param, prio, task_handle,
468 (core_id < portNUM_PROCESSORS ? core_id : tskNO_AFFINITY));
469 }
470
task_delete_wrapper(void * task_handle)471 static void task_delete_wrapper(void *task_handle)
472 {
473 vTaskDelete(task_handle);
474 }
475
esp_ecc_gen_key_pair(uint8_t * pub,uint8_t * priv)476 static int esp_ecc_gen_key_pair(uint8_t *pub, uint8_t *priv)
477 {
478 int rc = -1;
479 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
480 rc = ble_sm_alg_gen_key_pair(pub, priv);
481 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
482 return rc;
483 }
484
esp_ecc_gen_dh_key(const uint8_t * peer_pub_key_x,const uint8_t * peer_pub_key_y,const uint8_t * our_priv_key,uint8_t * out_dhkey)485 static int esp_ecc_gen_dh_key(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
486 const uint8_t *our_priv_key, uint8_t *out_dhkey)
487 {
488 int rc = -1;
489 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
490 rc = ble_sm_alg_gen_dhkey(peer_pub_key_x, peer_pub_key_y, our_priv_key, out_dhkey);
491 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
492 return rc;
493 }
494
esp_intr_alloc_wrapper(int source,int flags,intr_handler_t handler,void * arg,void ** ret_handle_in)495 static int esp_intr_alloc_wrapper(int source, int flags, intr_handler_t handler,
496 void *arg, void **ret_handle_in)
497 {
498 int rc = esp_intr_alloc(source, flags | ESP_INTR_FLAG_IRAM, handler,
499 arg, (intr_handle_t *)ret_handle_in);
500 return rc;
501 }
502
esp_intr_free_wrapper(void ** ret_handle)503 static int esp_intr_free_wrapper(void **ret_handle)
504 {
505 int rc = 0;
506 rc = esp_intr_free((intr_handle_t) * ret_handle);
507 *ret_handle = NULL;
508 return rc;
509 }
510
esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)511 void esp_bt_rtc_slow_clk_select(uint8_t slow_clk_src)
512 {
513 /* Select slow clock source for BT momdule */
514 switch (slow_clk_src) {
515 case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
516 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using main XTAL as clock source");
517 modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (320 - 1));
518 break;
519 case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
520 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 136 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
521 modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (5 - 1));
522 break;
523 case MODEM_CLOCK_LPCLK_SRC_XTAL32K:
524 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using external 32.768 kHz XTAL as clock source");
525 modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
526 break;
527 case MODEM_CLOCK_LPCLK_SRC_RC32K:
528 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz RC as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
529 modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
530 break;
531 case MODEM_CLOCK_LPCLK_SRC_EXT32K:
532 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Using 32 kHz oscillator as clock source, can only run legacy ADV or SCAN due to low clock accuracy!");
533 modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (1 - 1));
534 break;
535 default:
536 }
537 }
538
esp_bt_get_lpclk_src(void)539 modem_clock_lpclk_src_t esp_bt_get_lpclk_src(void)
540 {
541 return s_bt_lpclk_src;
542 }
543
esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)544 void esp_bt_set_lpclk_src(modem_clock_lpclk_src_t clk_src)
545 {
546 if (clk_src >= MODEM_CLOCK_LPCLK_SRC_MAX) {
547 return;
548 }
549
550 s_bt_lpclk_src = clk_src;
551 }
552
controller_sleep_cb(uint32_t enable_tick,void * arg)553 IRAM_ATTR void controller_sleep_cb(uint32_t enable_tick, void *arg)
554 {
555 if (!s_ble_active) {
556 return;
557 }
558 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
559 r_ble_rtc_wake_up_state_clr();
560 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
561 esp_phy_disable(PHY_MODEM_BT);
562 #ifdef CONFIG_PM_ENABLE
563 esp_pm_lock_release(s_pm_lock);
564 #endif // CONFIG_PM_ENABLE
565 s_ble_active = false;
566 }
567
controller_wakeup_cb(void * arg)568 IRAM_ATTR void controller_wakeup_cb(void *arg)
569 {
570 if (s_ble_active) {
571 return;
572 }
573 #ifdef CONFIG_PM_ENABLE
574 esp_pm_lock_acquire(s_pm_lock);
575 r_ble_rtc_wake_up_state_clr();
576 #endif //CONFIG_PM_ENABLE
577 esp_phy_enable(PHY_MODEM_BT);
578 s_ble_active = true;
579 }
580
581 #ifdef CONFIG_FREERTOS_USE_TICKLESS_IDLE
sleep_modem_ble_mac_retention_init(void * arg)582 static esp_err_t sleep_modem_ble_mac_retention_init(void *arg)
583 {
584 uint8_t size;
585 int extra = *(int *)arg;
586 sleep_retention_entries_config_t *ble_mac_modem_config = r_esp_ble_mac_retention_link_get(&size, extra);
587 esp_err_t err = sleep_retention_entries_create(ble_mac_modem_config, size, REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BLE_MAC);
588 if (err == ESP_OK) {
589 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Modem BLE MAC retention initialization");
590 }
591 return err;
592 }
593
sleep_modem_ble_mac_modem_state_init(uint8_t extra)594 static esp_err_t sleep_modem_ble_mac_modem_state_init(uint8_t extra)
595 {
596 int retention_args = extra;
597 sleep_retention_module_init_param_t init_param = {
598 .cbs = { .create = { .handle = sleep_modem_ble_mac_retention_init, .arg = &retention_args } },
599 .depends = BIT(SLEEP_RETENTION_MODULE_BT_BB)
600 };
601 esp_err_t err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_BLE_MAC, &init_param);
602 if (err == ESP_OK) {
603 err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_BLE_MAC);
604 }
605 return err;
606 }
607
sleep_modem_ble_mac_modem_state_deinit(void)608 static void sleep_modem_ble_mac_modem_state_deinit(void)
609 {
610 esp_err_t err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_BLE_MAC);
611 if (err == ESP_OK) {
612 err = sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_BLE_MAC);
613 assert(err == ESP_OK);
614 }
615 }
616
sleep_modem_light_sleep_overhead_set(uint32_t overhead)617 void IRAM_ATTR sleep_modem_light_sleep_overhead_set(uint32_t overhead)
618 {
619 r_esp_ble_set_wakeup_overhead(overhead);
620 }
621 #endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
622
623
controller_sleep_init(void)624 esp_err_t controller_sleep_init(void)
625 {
626 esp_err_t rc = 0;
627
628 #ifdef CONFIG_BT_LE_SLEEP_ENABLE
629 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "BLE modem sleep is enabled");
630 #if CONFIG_FREERTOS_USE_TICKLESS_IDLE
631 r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0,
632 BLE_RTC_DELAY_US_LIGHT_SLEEP);
633 #else
634 r_ble_lll_rfmgmt_set_sleep_cb(controller_sleep_cb, controller_wakeup_cb, 0, 0,
635 BLE_RTC_DELAY_US_MODEM_SLEEP);
636 #endif /* FREERTOS_USE_TICKLESS_IDLE */
637 #endif // CONFIG_BT_LE_SLEEP_ENABLE
638
639 #ifdef CONFIG_PM_ENABLE
640 rc = esp_pm_lock_create(ESP_PM_CPU_FREQ_MAX, 0, "bt", &s_pm_lock);
641 if (rc != ESP_OK) {
642 goto error;
643 }
644 rc = esp_deep_sleep_register_hook(&r_esp_ble_stop_wakeup_timing);
645 if (rc != ESP_OK) {
646 goto error;
647 }
648 #endif //CONFIG_PM_ENABLE
649 #if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
650 /* Create a new regdma link for BLE related register restoration */
651 rc = sleep_modem_ble_mac_modem_state_init(0);
652 if (rc != ESP_OK) {
653 goto error;
654 }
655 esp_sleep_enable_bt_wakeup();
656 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "Enable light sleep, the wake up source is BLE timer");
657
658 rc = esp_pm_register_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
659 if (rc != ESP_OK) {
660 goto error;
661 }
662 #endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
663 return rc;
664
665 #ifdef CONFIG_PM_ENABLE
666 error:
667 #endif // CONFIG_PM_ENABLE
668 #if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
669 esp_sleep_disable_bt_wakeup();
670 esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
671 #endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
672 #ifdef CONFIG_PM_ENABLE
673 esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
674 /*lock should release first and then delete*/
675 if (s_pm_lock != NULL) {
676 esp_pm_lock_delete(s_pm_lock);
677 s_pm_lock = NULL;
678 }
679 #endif // CONFIG_PM_ENABLE
680
681 return rc;
682 }
683
controller_sleep_deinit(void)684 void controller_sleep_deinit(void)
685 {
686 #if CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE
687 r_ble_rtc_wake_up_state_clr();
688 esp_sleep_disable_bt_wakeup();
689 sleep_modem_ble_mac_modem_state_deinit();
690 esp_pm_unregister_inform_out_light_sleep_overhead_callback(sleep_modem_light_sleep_overhead_set);
691 #endif /* CONFIG_BT_LE_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
692 #ifdef CONFIG_PM_ENABLE
693 esp_deep_sleep_deregister_hook(&r_esp_ble_stop_wakeup_timing);
694 /* lock should be released first */
695 esp_pm_lock_delete(s_pm_lock);
696 s_pm_lock = NULL;
697 #endif //CONFIG_PM_ENABLE
698 }
699
700 typedef enum {
701 FILTER_DUPLICATE_PDUTYPE = BIT(0),
702 FILTER_DUPLICATE_LENGTH = BIT(1),
703 FILTER_DUPLICATE_ADDRESS = BIT(2),
704 FILTER_DUPLICATE_ADVDATA = BIT(3),
705 FILTER_DUPLICATE_DEFAULT = FILTER_DUPLICATE_PDUTYPE | FILTER_DUPLICATE_ADDRESS,
706 FILTER_DUPLICATE_PDU_ALL = 0xF,
707 FILTER_DUPLICATE_EXCEPTION_FOR_MESH = BIT(4),
708 FILTER_DUPLICATE_AD_TYPE = BIT(5),
709 }disc_duplicate_mode_t;
710
711
712 extern void r_filter_duplicate_mode_enable(disc_duplicate_mode_t mode);
713 extern void r_filter_duplicate_mode_disable(disc_duplicate_mode_t mode);
714 extern void r_filter_duplicate_set_ring_list_max_num(uint32_t max_num);
715 extern void r_scan_duplicate_cache_refresh_set_time(uint32_t period_time);
716
717 int
ble_vhci_disc_duplicate_mode_enable(int mode)718 ble_vhci_disc_duplicate_mode_enable(int mode)
719 {
720 // TODO: use vendor hci to update
721 r_filter_duplicate_mode_enable(mode);
722 return true;
723 }
724
725 int
ble_vhci_disc_duplicate_mode_disable(int mode)726 ble_vhci_disc_duplicate_mode_disable(int mode)
727 {
728 // TODO: use vendor hci to update
729 r_filter_duplicate_mode_disable(mode);
730 return true;
731 }
732
ble_vhci_disc_duplicate_set_max_cache_size(int max_cache_size)733 int ble_vhci_disc_duplicate_set_max_cache_size(int max_cache_size){
734 // TODO: use vendor hci to update
735 r_filter_duplicate_set_ring_list_max_num(max_cache_size);
736 return true;
737 }
738
ble_vhci_disc_duplicate_set_period_refresh_time(int refresh_period_time)739 int ble_vhci_disc_duplicate_set_period_refresh_time(int refresh_period_time){
740 // TODO: use vendor hci to update
741 r_scan_duplicate_cache_refresh_set_time(refresh_period_time);
742 return true;
743 }
744
745 /**
746 * @brief Config scan duplicate option mode from menuconfig (Adapt to the old configuration method.)
747 */
ble_controller_scan_duplicate_config(void)748 void ble_controller_scan_duplicate_config(void)
749 {
750 uint32_t duplicate_mode = FILTER_DUPLICATE_DEFAULT;
751 uint32_t cache_size = 100;
752 #if CONFIG_BT_LE_SCAN_DUPL == true
753 cache_size = CONFIG_BT_LE_LL_DUP_SCAN_LIST_COUNT;
754 if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 0) {
755 duplicate_mode = FILTER_DUPLICATE_ADDRESS | FILTER_DUPLICATE_PDUTYPE;
756 } else if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 1) {
757 duplicate_mode = FILTER_DUPLICATE_ADVDATA;
758 } else if (CONFIG_BT_LE_SCAN_DUPL_TYPE == 2) {
759 duplicate_mode = FILTER_DUPLICATE_ADDRESS | FILTER_DUPLICATE_ADVDATA;
760 }
761 duplicate_mode |= FILTER_DUPLICATE_EXCEPTION_FOR_MESH;
762
763 ble_vhci_disc_duplicate_set_period_refresh_time(CONFIG_BT_LE_SCAN_DUPL_CACHE_REFRESH_PERIOD);
764 #endif
765
766 ble_vhci_disc_duplicate_mode_disable(0xFFFFFFFF);
767 ble_vhci_disc_duplicate_mode_enable(duplicate_mode);
768 ble_vhci_disc_duplicate_set_max_cache_size(cache_size);
769 }
770
ble_rtc_clk_init(esp_bt_controller_config_t * cfg)771 static void ble_rtc_clk_init(esp_bt_controller_config_t *cfg)
772 {
773 if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
774 #if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
775 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
776 #else
777 #if CONFIG_RTC_CLK_SRC_INT_RC
778 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
779 #elif CONFIG_RTC_CLK_SRC_EXT_CRYS
780 if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
781 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
782 } else {
783 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
784 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
785 }
786 #elif CONFIG_RTC_CLK_SRC_INT_RC32K
787 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
788 #elif CONFIG_RTC_CLK_SRC_EXT_OSC
789 s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
790 #else
791 ESP_LOGE(NIMBLE_PORT_LOG_TAG, "Unsupported clock source");
792 assert(0);
793 #endif
794 #endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
795 }
796
797 if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
798 cfg->rtc_freq = 100000;
799 } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
800 cfg->rtc_freq = 32768;
801 } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
802 cfg->rtc_freq = 30000;
803 } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
804 cfg->rtc_freq = 32000;
805 } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
806 cfg->rtc_freq = 32000;
807 }
808 esp_bt_rtc_slow_clk_select(s_bt_lpclk_src);
809 }
810
esp_bt_controller_init(esp_bt_controller_config_t * cfg)811 esp_err_t esp_bt_controller_init(esp_bt_controller_config_t *cfg)
812 {
813 uint8_t mac[6];
814 esp_err_t ret = ESP_OK;
815 ble_npl_count_info_t npl_info;
816 uint8_t hci_transport_mode;
817
818 memset(&npl_info, 0, sizeof(ble_npl_count_info_t));
819 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
820 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
821 return ESP_ERR_INVALID_STATE;
822 }
823
824 if (!cfg) {
825 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "cfg is NULL");
826 return ESP_ERR_INVALID_ARG;
827 }
828
829 ret = esp_register_ext_funcs(&ext_funcs_ro);
830 if (ret != ESP_OK) {
831 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "register extend functions failed");
832 return ret;
833 }
834
835 /* Initialize the function pointers for OS porting */
836 npl_freertos_funcs_init();
837 struct npl_funcs_t *p_npl_funcs = npl_freertos_funcs_get();
838 if (!p_npl_funcs) {
839 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions get failed");
840 return ESP_ERR_INVALID_ARG;
841 }
842
843 ret = esp_register_npl_funcs(p_npl_funcs);
844 if (ret != ESP_OK) {
845 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl functions register failed");
846 goto free_mem;
847 }
848
849 r_ble_get_npl_element_info(cfg, &npl_info);
850 npl_freertos_set_controller_npl_info(&npl_info);
851 if (npl_freertos_mempool_init() != 0) {
852 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "npl mempool init failed");
853 ret = ESP_ERR_INVALID_ARG;
854 goto free_mem;
855 }
856
857 #if CONFIG_BT_NIMBLE_ENABLED
858 /* ble_npl_eventq_init() needs to use npl functions in rom and
859 * must be called after esp_bt_controller_init().
860 */
861 ble_npl_eventq_init(nimble_port_get_dflt_eventq());
862 #endif // CONFIG_BT_NIMBLE_ENABLED
863 /* Enable BT-related clocks */
864 modem_clock_module_enable(PERIPH_BT_MODULE);
865 modem_clock_module_mac_reset(PERIPH_BT_MODULE);
866 /* Select slow clock source for BT momdule */
867 ble_rtc_clk_init(cfg);
868
869 if (ble_osi_coex_funcs_register((struct osi_coex_funcs_t *)&s_osi_coex_funcs_ro) != 0) {
870 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "osi coex funcs reg failed");
871 ret = ESP_ERR_INVALID_ARG;
872 goto modem_deint;
873 }
874
875 #if CONFIG_SW_COEXIST_ENABLE
876 coex_init();
877 #endif // CONFIG_SW_COEXIST_ENABLE
878
879 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
880 ret = esp_bt_controller_log_init(log_output_mode);
881 if (ret != ESP_OK) {
882 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "ble_controller_log_init failed %d", ret);
883 goto modem_deint;
884 }
885 #endif // CONFIG_BT_CONTROLLER_LOG_ENABLED
886 ret = esp_ble_register_bb_funcs();
887 if (ret != ESP_OK) {
888 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "esp_ble_register_bb_funcs failed %d", ret);
889 goto modem_deint;
890 }
891
892 ret = r_ble_controller_init(cfg);
893 if (ret != ESP_OK) {
894 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "r_ble_controller_init failed %d", ret);
895 goto modem_deint;
896 }
897
898 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "ble controller commit:[%s]", ble_controller_get_compile_version());
899
900 ble_controller_scan_duplicate_config();
901
902 ret = os_msys_init();
903 if (ret != ESP_OK) {
904 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "msys_init failed %d", ret);
905 goto free_controller;
906 }
907
908 ret = controller_sleep_init();
909 if (ret != ESP_OK) {
910 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "controller_sleep_init failed %d", ret);
911 goto free_controller;
912 }
913 ESP_ERROR_CHECK(esp_read_mac((uint8_t *)mac, ESP_MAC_BT));
914 ESP_LOGI(NIMBLE_PORT_LOG_TAG, "Bluetooth MAC: %02x:%02x:%02x:%02x:%02x:%02x",
915 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
916 swap_in_place(mac, 6);
917 r_esp_ble_ll_set_public_addr(mac);
918
919 ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
920
921 #if CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
922 hci_transport_mode = HCI_TRANSPORT_VHCI;
923 #elif CONFIG_BT_LE_HCI_INTERFACE_USE_UART
924 hci_transport_mode = HCI_TRANSPORT_UART_NO_DMA;
925 #if CONFIG_BT_LE_UART_HCI_DMA_MODE
926 hci_transport_mode = HCI_TRANSPORT_UART_UHCI;
927 #endif // CONFIG_BT_LE_UART_HCI_DMA_MODE
928 #endif // CONFIG_BT_LE_HCI_INTERFACE_USE_RAM
929 ret = hci_transport_init(hci_transport_mode);
930 if (ret) {
931 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "hci transport init failed %d", ret);
932 goto free_controller;
933 }
934
935 return ESP_OK;
936 free_controller:
937 hci_transport_deinit();
938 controller_sleep_deinit();
939 os_msys_deinit();
940 r_ble_controller_deinit();
941 modem_deint:
942 esp_ble_unregister_bb_funcs();
943 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
944 esp_bt_ontroller_log_deinit();
945 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
946 modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
947 modem_clock_module_disable(PERIPH_BT_MODULE);
948 #if CONFIG_BT_NIMBLE_ENABLED
949 ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
950 #endif // CONFIG_BT_NIMBLE_ENABLED
951 free_mem:
952 npl_freertos_mempool_deinit();
953 esp_unregister_npl_funcs();
954 npl_freertos_funcs_deinit();
955 esp_unregister_ext_funcs();
956 return ret;
957 }
958
esp_bt_controller_deinit(void)959 esp_err_t esp_bt_controller_deinit(void)
960 {
961 if ((ble_controller_status < ESP_BT_CONTROLLER_STATUS_INITED) ||
962 (ble_controller_status >= ESP_BT_CONTROLLER_STATUS_ENABLED)) {
963 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
964 return ESP_FAIL;
965 }
966
967 hci_transport_deinit();
968 controller_sleep_deinit();
969
970 os_msys_deinit();
971
972 modem_clock_deselect_lp_clock_source(PERIPH_BT_MODULE);
973 modem_clock_module_disable(PERIPH_BT_MODULE);
974
975 r_ble_controller_deinit();
976 esp_ble_unregister_bb_funcs();
977 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
978 esp_bt_ontroller_log_deinit();
979 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
980
981 #if CONFIG_BT_NIMBLE_ENABLED
982 /* De-initialize default event queue */
983 ble_npl_eventq_deinit(nimble_port_get_dflt_eventq());
984 #endif // CONFIG_BT_NIMBLE_ENABLED
985
986 esp_unregister_npl_funcs();
987
988 esp_unregister_ext_funcs();
989
990 /* De-initialize npl functions */
991 npl_freertos_funcs_deinit();
992
993 npl_freertos_mempool_deinit();
994
995 ble_controller_status = ESP_BT_CONTROLLER_STATUS_IDLE;
996
997 return ESP_OK;
998 }
999
esp_bt_controller_enable(esp_bt_mode_t mode)1000 esp_err_t esp_bt_controller_enable(esp_bt_mode_t mode)
1001 {
1002 esp_err_t ret = ESP_OK;
1003
1004 if (mode != ESP_BT_MODE_BLE) {
1005 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller mode");
1006 return ESP_FAIL;
1007 }
1008 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_INITED) {
1009 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
1010 return ESP_FAIL;
1011 }
1012 if (!s_ble_active) {
1013 #if CONFIG_PM_ENABLE
1014 esp_pm_lock_acquire(s_pm_lock);
1015 #endif // CONFIG_PM_ENABLE
1016 esp_phy_enable(PHY_MODEM_BT);
1017 s_ble_active = true;
1018 }
1019 esp_btbb_enable();
1020 #if CONFIG_SW_COEXIST_ENABLE
1021 coex_enable();
1022 #endif // CONFIG_SW_COEXIST_ENABLE
1023
1024 if (r_ble_controller_enable(mode) != 0) {
1025 ret = ESP_FAIL;
1026 goto error;
1027 }
1028 ble_controller_status = ESP_BT_CONTROLLER_STATUS_ENABLED;
1029 return ESP_OK;
1030
1031 error:
1032 #if CONFIG_SW_COEXIST_ENABLE
1033 coex_disable();
1034 #endif
1035 esp_btbb_disable();
1036 if (s_ble_active) {
1037 esp_phy_disable(PHY_MODEM_BT);
1038 #if CONFIG_PM_ENABLE
1039 esp_pm_lock_release(s_pm_lock);
1040 #endif // CONFIG_PM_ENABLE
1041 s_ble_active = false;
1042 }
1043 return ret;
1044 }
1045
esp_bt_controller_disable(void)1046 esp_err_t esp_bt_controller_disable(void)
1047 {
1048 if (ble_controller_status < ESP_BT_CONTROLLER_STATUS_ENABLED) {
1049 ESP_LOGW(NIMBLE_PORT_LOG_TAG, "invalid controller state");
1050 return ESP_FAIL;
1051 }
1052 if (r_ble_controller_disable() != 0) {
1053 return ESP_FAIL;
1054 }
1055 #if CONFIG_SW_COEXIST_ENABLE
1056 coex_disable();
1057 #endif
1058 esp_btbb_disable();
1059 if (s_ble_active) {
1060 esp_phy_disable(PHY_MODEM_BT);
1061 #if CONFIG_PM_ENABLE
1062 esp_pm_lock_release(s_pm_lock);
1063 #endif // CONFIG_PM_ENABLE
1064 s_ble_active = false;
1065 }
1066 ble_controller_status = ESP_BT_CONTROLLER_STATUS_INITED;
1067 return ESP_OK;
1068 }
1069
esp_bt_controller_mem_release(esp_bt_mode_t mode)1070 esp_err_t esp_bt_controller_mem_release(esp_bt_mode_t mode)
1071 {
1072 ESP_LOGD(NIMBLE_PORT_LOG_TAG, "%s not implemented, return OK", __func__);
1073 return ESP_OK;
1074 }
1075
try_heap_caps_add_region(intptr_t start,intptr_t end)1076 static esp_err_t try_heap_caps_add_region(intptr_t start, intptr_t end)
1077 {
1078 int ret = heap_caps_add_region(start, end);
1079
1080 /* heap_caps_add_region() returns ESP_ERR_INVALID_SIZE if the memory region is
1081 * is too small to fit a heap. This cannot be termed as a fatal error and hence
1082 * we replace it by ESP_OK
1083 */
1084 if (ret == ESP_ERR_INVALID_SIZE) {
1085 return ESP_OK;
1086 }
1087 return ret;
1088 }
1089
1090
1091 typedef struct {
1092 intptr_t start;
1093 intptr_t end;
1094 const char* name;
1095 } bt_area_t;
1096
esp_bt_mem_release_area(const bt_area_t * area)1097 static esp_err_t esp_bt_mem_release_area(const bt_area_t *area)
1098 {
1099 esp_err_t ret = ESP_OK;
1100 intptr_t mem_start = area->start;
1101 intptr_t mem_end = area->end;
1102 if (mem_start != mem_end) {
1103 ESP_LOGD(NIMBLE_PORT_LOG_TAG, "Release %s [0x%08x] - [0x%08x], len %d", area->name, mem_start, mem_end, mem_end - mem_start);
1104 ret = try_heap_caps_add_region(mem_start, mem_end);
1105 }
1106 return ret;
1107 }
1108
esp_bt_mem_release_areas(const bt_area_t * area1,const bt_area_t * area2)1109 static esp_err_t esp_bt_mem_release_areas(const bt_area_t *area1, const bt_area_t *area2)
1110 {
1111 esp_err_t ret = ESP_OK;
1112
1113 if (area1->end == area2->start) {
1114 bt_area_t merged_area = {
1115 .start = area1->start,
1116 .end = area2->end,
1117 .name = area1->name
1118 };
1119 ret = esp_bt_mem_release_area(&merged_area);
1120 } else {
1121 esp_bt_mem_release_area(area1);
1122 ret = esp_bt_mem_release_area(area2);
1123 }
1124
1125 return ret;
1126 }
1127
esp_bt_mem_release(esp_bt_mode_t mode)1128 esp_err_t esp_bt_mem_release(esp_bt_mode_t mode)
1129 {
1130 esp_err_t ret = ESP_OK;
1131
1132 if (ble_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) {
1133 return ESP_ERR_INVALID_STATE;
1134 }
1135
1136 bt_area_t bss = {
1137 .start = (intptr_t)&_bt_bss_start,
1138 .end = (intptr_t)&_bt_bss_end,
1139 .name = "BT BSS",
1140 };
1141 bt_area_t cont_bss = {
1142 .start = (intptr_t)&_bt_controller_bss_start,
1143 .end = (intptr_t)&_bt_controller_bss_end,
1144 .name = "BT Controller BSS",
1145 };
1146 bt_area_t data = {
1147 .start = (intptr_t)&_bt_data_start,
1148 .end = (intptr_t)&_bt_data_end,
1149 .name = "BT Data",
1150 };
1151 bt_area_t cont_data = {
1152 .start = (intptr_t)&_bt_controller_data_start,
1153 .end = (intptr_t)&_bt_controller_data_end,
1154 .name = "BT Controller Data"
1155 };
1156
1157 if (mode & ESP_BT_MODE_BLE) {
1158 /* Start by freeing Bluetooth BSS section */
1159 if (ret == ESP_OK) {
1160 ret = esp_bt_mem_release_areas(&bss, &cont_bss);
1161 }
1162
1163 /* Do the same thing with the Bluetooth data section */
1164 if (ret == ESP_OK) {
1165 ret = esp_bt_mem_release_areas(&data, &cont_data);
1166 }
1167 }
1168
1169 return ret;
1170 }
1171
1172
esp_bt_controller_get_status(void)1173 esp_bt_controller_status_t esp_bt_controller_get_status(void)
1174 {
1175 return ble_controller_status;
1176 }
1177
esp_ble_tx_power_set(esp_ble_power_type_t power_type,esp_power_level_t power_level)1178 esp_err_t esp_ble_tx_power_set(esp_ble_power_type_t power_type, esp_power_level_t power_level)
1179 {
1180 esp_err_t stat = ESP_FAIL;
1181
1182 switch (power_type) {
1183 case ESP_BLE_PWR_TYPE_DEFAULT:
1184 case ESP_BLE_PWR_TYPE_ADV:
1185 case ESP_BLE_PWR_TYPE_SCAN:
1186 if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
1187 stat = ESP_OK;
1188 }
1189 break;
1190 case ESP_BLE_PWR_TYPE_CONN_HDL0:
1191 case ESP_BLE_PWR_TYPE_CONN_HDL1:
1192 case ESP_BLE_PWR_TYPE_CONN_HDL2:
1193 case ESP_BLE_PWR_TYPE_CONN_HDL3:
1194 case ESP_BLE_PWR_TYPE_CONN_HDL4:
1195 case ESP_BLE_PWR_TYPE_CONN_HDL5:
1196 case ESP_BLE_PWR_TYPE_CONN_HDL6:
1197 case ESP_BLE_PWR_TYPE_CONN_HDL7:
1198 case ESP_BLE_PWR_TYPE_CONN_HDL8:
1199 if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type, power_level) == 0) {
1200 stat = ESP_OK;
1201 }
1202 break;
1203 default:
1204 stat = ESP_ERR_NOT_SUPPORTED;
1205 break;
1206 }
1207
1208 return stat;
1209 }
1210
esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type,uint16_t handle,esp_power_level_t power_level)1211 esp_err_t esp_ble_tx_power_set_enhanced(esp_ble_enhanced_power_type_t power_type, uint16_t handle,
1212 esp_power_level_t power_level)
1213 {
1214 esp_err_t stat = ESP_FAIL;
1215 switch (power_type) {
1216 case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
1217 case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
1218 case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
1219 if (r_ble_txpwr_set(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0, power_level) == 0) {
1220 stat = ESP_OK;
1221 }
1222 break;
1223 case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
1224 case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
1225 if (r_ble_txpwr_set(power_type, handle, power_level) == 0) {
1226 stat = ESP_OK;
1227 }
1228 break;
1229 default:
1230 stat = ESP_ERR_NOT_SUPPORTED;
1231 break;
1232 }
1233
1234 return stat;
1235 }
1236
esp_ble_tx_power_get(esp_ble_power_type_t power_type)1237 esp_power_level_t esp_ble_tx_power_get(esp_ble_power_type_t power_type)
1238 {
1239 int tx_level = 0;
1240
1241 switch (power_type) {
1242 case ESP_BLE_PWR_TYPE_ADV:
1243 case ESP_BLE_PWR_TYPE_SCAN:
1244 case ESP_BLE_PWR_TYPE_DEFAULT:
1245 tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
1246 break;
1247 case ESP_BLE_PWR_TYPE_CONN_HDL0:
1248 case ESP_BLE_PWR_TYPE_CONN_HDL1:
1249 case ESP_BLE_PWR_TYPE_CONN_HDL2:
1250 case ESP_BLE_PWR_TYPE_CONN_HDL3:
1251 case ESP_BLE_PWR_TYPE_CONN_HDL4:
1252 case ESP_BLE_PWR_TYPE_CONN_HDL5:
1253 case ESP_BLE_PWR_TYPE_CONN_HDL6:
1254 case ESP_BLE_PWR_TYPE_CONN_HDL7:
1255 case ESP_BLE_PWR_TYPE_CONN_HDL8:
1256 tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_CONN, power_type);
1257 break;
1258 default:
1259 return ESP_PWR_LVL_INVALID;
1260 }
1261
1262 if (tx_level < 0) {
1263 return ESP_PWR_LVL_INVALID;
1264 }
1265
1266 return (esp_power_level_t)tx_level;
1267 }
1268
esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type,uint16_t handle)1269 esp_power_level_t esp_ble_tx_power_get_enhanced(esp_ble_enhanced_power_type_t power_type,
1270 uint16_t handle)
1271 {
1272 int tx_level = 0;
1273
1274 switch (power_type) {
1275 case ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT:
1276 case ESP_BLE_ENHANCED_PWR_TYPE_SCAN:
1277 case ESP_BLE_ENHANCED_PWR_TYPE_INIT:
1278 tx_level = r_ble_txpwr_get(ESP_BLE_ENHANCED_PWR_TYPE_DEFAULT, 0);
1279 break;
1280 case ESP_BLE_ENHANCED_PWR_TYPE_ADV:
1281 case ESP_BLE_ENHANCED_PWR_TYPE_CONN:
1282 tx_level = r_ble_txpwr_get(power_type, handle);
1283 break;
1284 default:
1285 return ESP_PWR_LVL_INVALID;
1286 }
1287
1288 if (tx_level < 0) {
1289 return ESP_PWR_LVL_INVALID;
1290 }
1291
1292 return (esp_power_level_t)tx_level;
1293 }
1294
1295 #if CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
esp_bt_controller_log_interface(uint32_t len,const uint8_t * addr,bool end)1296 static void esp_bt_controller_log_interface(uint32_t len, const uint8_t *addr, bool end)
1297 {
1298 if (log_output_mode == LOG_STORAGE_TO_FLASH) {
1299 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
1300 esp_bt_controller_log_storage(len, addr, end);
1301 #endif //CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
1302 } else {
1303 portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
1304 portENTER_CRITICAL_SAFE(&spinlock);
1305 esp_panic_handler_reconfigure_wdts(1000);
1306 for (int i = 0; i < len; i++) {
1307 esp_rom_printf("%02x ", addr[i]);
1308 }
1309
1310 if (end) {
1311 esp_rom_printf("\n");
1312 }
1313 portEXIT_CRITICAL_SAFE(&spinlock);
1314 }
1315 }
1316
esp_ble_controller_log_dump_all(bool output)1317 void esp_ble_controller_log_dump_all(bool output)
1318 {
1319 #if CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
1320 esp_bt_read_ctrl_log_from_flash(output);
1321 #else
1322 portMUX_TYPE spinlock = portMUX_INITIALIZER_UNLOCKED;
1323
1324 portENTER_CRITICAL_SAFE(&spinlock);
1325 esp_panic_handler_reconfigure_wdts(5000);
1326 BT_ASSERT_PRINT("\r\n[DUMP_START:");
1327 r_ble_log_async_output_dump_all(output);
1328 BT_ASSERT_PRINT(":DUMP_END]\r\n");
1329 portEXIT_CRITICAL_SAFE(&spinlock);
1330 #endif // CONFIG_BT_LE_CONTROLLER_LOG_STORAGE_ENABLE
1331 }
1332 #endif // CONFIG_BT_LE_CONTROLLER_LOG_ENABLED
1333
1334 #if (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
1335 #if CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
1336 #define BLE_SM_KEY_ERR 0x17
1337 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1338 #include "mbedtls/aes.h"
1339 #if CONFIG_BT_LE_SM_SC
1340 #include "mbedtls/cipher.h"
1341 #include "mbedtls/entropy.h"
1342 #include "mbedtls/ctr_drbg.h"
1343 #include "mbedtls/cmac.h"
1344 #include "mbedtls/ecdh.h"
1345 #include "mbedtls/ecp.h"
1346
1347 static mbedtls_ecp_keypair keypair;
1348 #endif // CONFIG_BT_LE_SM_SC
1349
1350 #else
1351 #include "tinycrypt/aes.h"
1352 #include "tinycrypt/constants.h"
1353 #include "tinycrypt/utils.h"
1354
1355 #if CONFIG_BT_LE_SM_SC
1356 #include "tinycrypt/cmac_mode.h"
1357 #include "tinycrypt/ecc_dh.h"
1358 #endif // CONFIG_BT_LE_SM_SC
1359 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1360
1361 /* Based on Core Specification 4.2 Vol 3. Part H 2.3.5.6.1 */
1362 static const uint8_t ble_sm_alg_dbg_priv_key[32] = {
1363 0x3f, 0x49, 0xf6, 0xd4, 0xa3, 0xc5, 0x5f, 0x38, 0x74, 0xc9, 0xb3, 0xe3,
1364 0xd2, 0x10, 0x3f, 0x50, 0x4a, 0xff, 0x60, 0x7b, 0xeb, 0x40, 0xb7, 0x99,
1365 0x58, 0x99, 0xb8, 0xa6, 0xcd, 0x3c, 0x1a, 0xbd
1366 };
1367
ble_sm_alg_gen_dhkey(const uint8_t * peer_pub_key_x,const uint8_t * peer_pub_key_y,const uint8_t * our_priv_key,uint8_t * out_dhkey)1368 int ble_sm_alg_gen_dhkey(const uint8_t *peer_pub_key_x, const uint8_t *peer_pub_key_y,
1369 const uint8_t *our_priv_key, uint8_t *out_dhkey)
1370 {
1371 uint8_t dh[32];
1372 uint8_t pk[64];
1373 uint8_t priv[32];
1374 int rc = BLE_SM_KEY_ERR;
1375
1376 swap_buf(pk, peer_pub_key_x, 32);
1377 swap_buf(&pk[32], peer_pub_key_y, 32);
1378 swap_buf(priv, our_priv_key, 32);
1379
1380 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1381 struct mbedtls_ecp_point pt = {0}, Q = {0};
1382 mbedtls_mpi z = {0}, d = {0};
1383 mbedtls_ctr_drbg_context ctr_drbg = {0};
1384 mbedtls_entropy_context entropy = {0};
1385
1386 uint8_t pub[65] = {0};
1387 /* Hardcoded first byte of pub key for MBEDTLS_ECP_PF_UNCOMPRESSED */
1388 pub[0] = 0x04;
1389 memcpy(&pub[1], pk, 64);
1390
1391 /* Initialize the required structures here */
1392 mbedtls_ecp_point_init(&pt);
1393 mbedtls_ecp_point_init(&Q);
1394 mbedtls_ctr_drbg_init(&ctr_drbg);
1395 mbedtls_entropy_init(&entropy);
1396 mbedtls_mpi_init(&d);
1397 mbedtls_mpi_init(&z);
1398
1399 /* Below 3 steps are to validate public key on curve secp256r1 */
1400 if (mbedtls_ecp_group_load(&keypair.MBEDTLS_PRIVATE(grp), MBEDTLS_ECP_DP_SECP256R1) != 0) {
1401 goto exit;
1402 }
1403
1404 if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &pt, pub, 65) != 0) {
1405 goto exit;
1406 }
1407
1408 if (mbedtls_ecp_check_pubkey(&keypair.MBEDTLS_PRIVATE(grp), &pt) != 0) {
1409 goto exit;
1410 }
1411
1412 /* Set PRNG */
1413 if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy, NULL, 0)) != 0) {
1414 goto exit;
1415 }
1416
1417 /* Prepare point Q from pub key */
1418 if (mbedtls_ecp_point_read_binary(&keypair.MBEDTLS_PRIVATE(grp), &Q, pub, 65) != 0) {
1419 goto exit;
1420 }
1421
1422 if (mbedtls_mpi_read_binary(&d, priv, 32) != 0) {
1423 goto exit;
1424 }
1425
1426 rc = mbedtls_ecdh_compute_shared(&keypair.MBEDTLS_PRIVATE(grp), &z, &Q, &d,
1427 mbedtls_ctr_drbg_random, &ctr_drbg);
1428 if (rc != 0) {
1429 goto exit;
1430 }
1431
1432 rc = mbedtls_mpi_write_binary(&z, dh, 32);
1433 if (rc != 0) {
1434 goto exit;
1435 }
1436
1437 exit:
1438 mbedtls_ecp_point_free(&pt);
1439 mbedtls_mpi_free(&z);
1440 mbedtls_mpi_free(&d);
1441 mbedtls_ecp_point_free(&Q);
1442 mbedtls_entropy_free(&entropy);
1443 mbedtls_ctr_drbg_free(&ctr_drbg);
1444 if (rc != 0) {
1445 return BLE_SM_KEY_ERR;
1446 }
1447
1448 #else
1449 if (uECC_valid_public_key(pk, &curve_secp256r1) < 0) {
1450 return BLE_SM_KEY_ERR;
1451 }
1452
1453 rc = uECC_shared_secret(pk, priv, dh, &curve_secp256r1);
1454 if (rc == TC_CRYPTO_FAIL) {
1455 return BLE_SM_KEY_ERR;
1456 }
1457 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1458
1459 swap_buf(out_dhkey, dh, 32);
1460 return 0;
1461 }
1462
1463 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
mbedtls_gen_keypair(uint8_t * public_key,uint8_t * private_key)1464 static int mbedtls_gen_keypair(uint8_t *public_key, uint8_t *private_key)
1465 {
1466 int rc = BLE_SM_KEY_ERR;
1467 mbedtls_entropy_context entropy = {0};
1468 mbedtls_ctr_drbg_context ctr_drbg = {0};
1469
1470 mbedtls_entropy_init(&entropy);
1471 mbedtls_ctr_drbg_init(&ctr_drbg);
1472 mbedtls_ecp_keypair_init(&keypair);
1473
1474 if ((rc = mbedtls_ctr_drbg_seed(&ctr_drbg, mbedtls_entropy_func, &entropy,
1475 NULL, 0)) != 0) {
1476 goto exit;
1477 }
1478
1479 if ((rc = mbedtls_ecp_gen_key(MBEDTLS_ECP_DP_SECP256R1, &keypair,
1480 mbedtls_ctr_drbg_random, &ctr_drbg)) != 0) {
1481 goto exit;
1482 }
1483
1484 if ((rc = mbedtls_mpi_write_binary(&keypair.MBEDTLS_PRIVATE(d), private_key, 32)) != 0) {
1485 goto exit;
1486 }
1487
1488 size_t olen = 0;
1489 uint8_t pub[65] = {0};
1490
1491 if ((rc = mbedtls_ecp_point_write_binary(&keypair.MBEDTLS_PRIVATE(grp), &keypair.MBEDTLS_PRIVATE(Q), MBEDTLS_ECP_PF_UNCOMPRESSED,
1492 &olen, pub, 65)) != 0) {
1493 goto exit;
1494 }
1495
1496 memcpy(public_key, &pub[1], 64);
1497
1498 exit:
1499 mbedtls_ctr_drbg_free(&ctr_drbg);
1500 mbedtls_entropy_free(&entropy);
1501 if (rc != 0) {
1502 mbedtls_ecp_keypair_free(&keypair);
1503 return BLE_SM_KEY_ERR;
1504 }
1505
1506 return 0;
1507 }
1508 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1509
1510 /**
1511 * pub: 64 bytes
1512 * priv: 32 bytes
1513 */
ble_sm_alg_gen_key_pair(uint8_t * pub,uint8_t * priv)1514 int ble_sm_alg_gen_key_pair(uint8_t *pub, uint8_t *priv)
1515 {
1516 #if CONFIG_BT_LE_SM_SC_DEBUG_KEYS
1517 swap_buf(pub, ble_sm_alg_dbg_pub_key, 32);
1518 swap_buf(&pub[32], &ble_sm_alg_dbg_pub_key[32], 32);
1519 swap_buf(priv, ble_sm_alg_dbg_priv_key, 32);
1520 #else
1521 uint8_t pk[64];
1522
1523 do {
1524 #if CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1525 if (mbedtls_gen_keypair(pk, priv) != 0) {
1526 return BLE_SM_KEY_ERR;
1527 }
1528 #else
1529 if (uECC_make_key(pk, priv, &curve_secp256r1) != TC_CRYPTO_SUCCESS) {
1530 return BLE_SM_KEY_ERR;
1531 }
1532 #endif // CONFIG_BT_LE_CRYPTO_STACK_MBEDTLS
1533 /* Make sure generated key isn't debug key. */
1534 } while (memcmp(priv, ble_sm_alg_dbg_priv_key, 32) == 0);
1535
1536 swap_buf(pub, pk, 32);
1537 swap_buf(&pub[32], &pk[32], 32);
1538 swap_in_place(priv, 32);
1539 #endif // CONFIG_BT_LE_SM_SC_DEBUG_KEYS
1540 return 0;
1541 }
1542
1543 #endif // CONFIG_BT_LE_SM_LEGACY || CONFIG_BT_LE_SM_SC
1544 #endif // (!CONFIG_BT_NIMBLE_ENABLED) && (CONFIG_BT_CONTROLLER_ENABLED)
1545
