1 // Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_SPI_FLASH_H_ 16 #define _ROM_SPI_FLASH_H_ 17 18 #ifndef CONFIG_IDF_TARGET_ESP32S2 19 #error This file should only be included for ESP32-S2 target 20 #endif 21 22 #include <stdint.h> 23 #include <stdbool.h> 24 25 #include "esp_attr.h" 26 #include "soc/spi_mem_reg.h" 27 28 #ifdef __cplusplus 29 extern "C" { 30 #endif 31 32 /** \defgroup spi_flash_apis, spi flash operation related apis 33 * @brief spi_flash apis 34 */ 35 36 /** @addtogroup spi_flash_apis 37 * @{ 38 */ 39 40 /************************************************************* 41 * Note 42 ************************************************************* 43 * 1. ESP32 chip have 4 SPI slave/master, however, SPI0 is 44 * used as an SPI master to access Flash and ext-SRAM by 45 * Cache module. It will support Decryto read for Flash, 46 * read/write for ext-SRAM. And SPI1 is also used as an 47 * SPI master for Flash read/write and ext-SRAM read/write. 48 * It will support Encrypto write for Flash. 49 * 2. As an SPI master, SPI support Highest clock to 80M, 50 * however, Flash with 80M Clock should be configured 51 * for different Flash chips. If you want to use 80M 52 * clock We should use the SPI that is certified by 53 * Espressif. However, the certification is not started 54 * at the time, so please use 40M clock at the moment. 55 * 3. SPI Flash can use 2 lines or 4 lines mode. If you 56 * use 2 lines mode, you can save two pad SPIHD and 57 * SPIWP for gpio. ESP32 support configured SPI pad for 58 * Flash, the configuration is stored in efuse and flash. 59 * However, the configurations of pads should be certified 60 * by Espressif. If you use this function, please use 40M 61 * clock at the moment. 62 * 4. ESP32 support to use Common SPI command to configure 63 * Flash to QIO mode, if you failed to configure with fix 64 * command. With Common SPI Command, ESP32 can also provide 65 * a way to use same Common SPI command groups on different 66 * Flash chips. 67 * 5. This functions are not protected by packeting, Please use the 68 ************************************************************* 69 */ 70 71 #define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) 72 #define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) 73 #define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) 74 #define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) 75 #define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) 76 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) 77 #define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) 78 #define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) 79 #define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) 80 #define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) 81 #define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) 82 #define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) 83 #define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) 84 #define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) 85 #define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) 86 #define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) 87 #define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) 88 89 #define SPI0_R_QIO_DUMMY_CYCLELEN 5 90 #define SPI0_R_QIO_ADDR_BITSLEN 23 91 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 92 #define SPI0_R_DIO_DUMMY_CYCLELEN 3 93 #define SPI0_R_FAST_ADDR_BITSLEN 23 94 #define SPI0_R_SIO_ADDR_BITSLEN 23 95 96 #define SPI1_R_QIO_DUMMY_CYCLELEN 5 97 #define SPI1_R_QIO_ADDR_BITSLEN 23 98 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 99 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 100 #define SPI1_R_DIO_ADDR_BITSLEN 23 101 #define SPI1_R_FAST_ADDR_BITSLEN 23 102 #define SPI1_R_SIO_ADDR_BITSLEN 23 103 104 #define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 105 106 #define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B 107 108 //SPI address register 109 #define ESP_ROM_SPIFLASH_BYTES_LEN 24 110 #define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 111 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 112 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf 113 114 //SPI status register 115 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 116 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 117 #define ESP_ROM_SPIFLASH_BP0 BIT2 118 #define ESP_ROM_SPIFLASH_BP1 BIT3 119 #define ESP_ROM_SPIFLASH_BP2 BIT4 120 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 121 #define ESP_ROM_SPIFLASH_QE BIT9 122 #define ESP_ROM_SPIFLASH_BP_MASK_ISSI (BIT7 | BIT5 | BIT4 | BIT3 | BIT2) 123 124 #define FLASH_ID_GD25LQ32C 0xC86016 125 126 typedef enum { 127 ESP_ROM_SPIFLASH_QIO_MODE = 0, 128 ESP_ROM_SPIFLASH_QOUT_MODE, 129 ESP_ROM_SPIFLASH_DIO_MODE, 130 ESP_ROM_SPIFLASH_DOUT_MODE, 131 ESP_ROM_SPIFLASH_FASTRD_MODE, 132 ESP_ROM_SPIFLASH_SLOWRD_MODE, 133 ESP_ROM_SPIFLASH_OPI_STR_MODE, 134 ESP_ROM_SPIFLASH_OPI_DTR_MODE, 135 ESP_ROM_SPIFLASH_OOUT_MODE, 136 ESP_ROM_SPIFLASH_OIO_STR_MODE, 137 ESP_ROM_SPIFLASH_OIO_DTR_MODE, 138 } esp_rom_spiflash_read_mode_t; 139 140 typedef enum { 141 ESP_ROM_SPIFLASH_RESULT_OK, 142 ESP_ROM_SPIFLASH_RESULT_ERR, 143 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 144 } esp_rom_spiflash_result_t; 145 146 typedef struct { 147 uint32_t device_id; 148 uint32_t chip_size; // chip size in bytes 149 uint32_t block_size; 150 uint32_t sector_size; 151 uint32_t page_size; 152 uint32_t status_mask; 153 } esp_rom_spiflash_chip_t; 154 155 typedef struct { 156 uint8_t data_length; 157 uint8_t read_cmd0; 158 uint8_t read_cmd1; 159 uint8_t write_cmd; 160 uint16_t data_mask; 161 uint16_t data; 162 } esp_rom_spiflash_common_cmd_t; 163 164 /** 165 * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. 166 * Please do not call this function in SDK. 167 * 168 * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). 169 * 170 * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. 171 * 172 * @return None 173 */ 174 void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); 175 176 /** 177 * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. 178 * Please do not call this function in SDK. 179 * 180 * @param uint8_t wp_gpio_num: WP gpio number. 181 * 182 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 183 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 184 * 185 * @return None 186 */ 187 void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); 188 189 /** 190 * @brief Set SPI Flash pad drivers. 191 * Please do not call this function in SDK. 192 * 193 * @param uint8_t wp_gpio_num: WP gpio number. 194 * 195 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 196 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 197 * 198 * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid 199 * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. 200 * Values usually read from falsh by rom code, function usually callde by rom code. 201 * if value with bit(3) set, the value is valid, bit[2:0] is the real value. 202 * 203 * @return None 204 */ 205 void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); 206 207 /** 208 * @brief Select SPI Flash function for pads. 209 * Please do not call this function in SDK. 210 * 211 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 212 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 213 * 214 * @return None 215 */ 216 void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); 217 218 /** 219 * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. 220 * Please do not call this function in SDK. 221 * 222 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 223 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 224 * 225 * @param uint8_t legacy: In legacy mode, more SPI command is used in line. 226 * 227 * @return None 228 */ 229 void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); 230 231 /** 232 * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). 233 * Please do not call this function in SDK. 234 * 235 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 236 * 237 * @param uint32_t *status : The pointer to which to return the Flash status value. 238 * 239 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 240 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 241 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 242 */ 243 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); 244 245 /** 246 * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). 247 * Please do not call this function in SDK. 248 * 249 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 250 * 251 * @param uint32_t *status : The pointer to which to return the Flash status value. 252 * 253 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 254 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 255 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 256 */ 257 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); 258 259 /** 260 * @brief Write status to Falsh status register. 261 * Please do not call this function in SDK. 262 * 263 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 264 * 265 * @param uint32_t status_value : Value to . 266 * 267 * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. 268 * ESP_ROM_SPIFLASH_RESULT_ERR : write error. 269 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. 270 */ 271 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 272 273 /** 274 * @brief Use a command to Read Flash status register. 275 * Please do not call this function in SDK. 276 * 277 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 278 * 279 * @param uint32_t*status : The pointer to which to return the Flash status value. 280 * 281 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 282 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 283 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 284 */ 285 esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); 286 287 /** 288 * @brief Config SPI Flash read mode when init. 289 * Please do not call this function in SDK. 290 * 291 * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. 292 * 293 * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. 294 * 295 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 296 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 297 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 298 */ 299 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); 300 301 /** 302 * @brief Config SPI Flash clock divisor. 303 * Please do not call this function in SDK. 304 * 305 * @param uint8_t freqdiv: clock divisor. 306 * 307 * @param uint8_t spi: 0 for SPI0, 1 for SPI1. 308 * 309 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 310 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 311 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 312 */ 313 esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); 314 315 /** 316 * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. 317 * Please do not call this function in SDK. 318 * 319 * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. 320 * 321 * @return uint16_t 0 : do not send command any more. 322 * 1 : go to the next command. 323 * n > 1 : skip (n - 1) commands. 324 */ 325 uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); 326 327 /** 328 * @brief Unlock SPI write protect. 329 * Please do not call this function in SDK. 330 * 331 * @param None. 332 * 333 * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. 334 * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. 335 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. 336 */ 337 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); 338 339 /** 340 * @brief SPI write protect. 341 * Please do not call this function in SDK. 342 * 343 * @param None. 344 * 345 * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. 346 * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. 347 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. 348 */ 349 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); 350 351 /** 352 * @brief Update SPI Flash parameter. 353 * Please do not call this function in SDK. 354 * 355 * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. 356 * 357 * @param uint32_t chip_size : The Flash size. 358 * 359 * @param uint32_t block_size : The Flash block size. 360 * 361 * @param uint32_t sector_size : The Flash sector size. 362 * 363 * @param uint32_t page_size : The Flash page size. 364 * 365 * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). 366 * 367 * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. 368 * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. 369 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. 370 */ 371 esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 372 uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 373 374 /** 375 * @brief Erase whole flash chip. 376 * Please do not call this function in SDK. 377 * 378 * @param None 379 * 380 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 381 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 382 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 383 */ 384 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); 385 386 /** 387 * @brief Erase a 64KB block of flash 388 * Uses SPI flash command D8H. 389 * Please do not call this function in SDK. 390 * 391 * @param uint32_t block_num : Which block to erase. 392 * 393 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 394 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 395 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 396 */ 397 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); 398 399 /** 400 * @brief Erase a sector of flash. 401 * Uses SPI flash command 20H. 402 * Please do not call this function in SDK. 403 * 404 * @param uint32_t sector_num : Which sector to erase. 405 * 406 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 407 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 408 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 409 */ 410 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); 411 412 /** 413 * @brief Erase some sectors. 414 * Please do not call this function in SDK. 415 * 416 * @param uint32_t start_addr : Start addr to erase, should be sector aligned. 417 * 418 * @param uint32_t area_len : Length to erase, should be sector aligned. 419 * 420 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 421 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 422 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 423 */ 424 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); 425 426 /** 427 * @brief Write Data to Flash, you should Erase it yourself if need. 428 * Please do not call this function in SDK. 429 * 430 * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. 431 * 432 * @param const uint32_t *src : The pointer to data which is to write. 433 * 434 * @param uint32_t len : Length to write, should be 4 bytes aligned. 435 * 436 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. 437 * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. 438 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. 439 */ 440 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); 441 442 /** 443 * @brief Read Data from Flash, you should Erase it yourself if need. 444 * Please do not call this function in SDK. 445 * 446 * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. 447 * 448 * @param uint32_t *dest : The buf to read the data. 449 * 450 * @param uint32_t len : Length to read, should be 4 bytes aligned. 451 * 452 * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. 453 * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. 454 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. 455 */ 456 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); 457 458 /** 459 * @brief SPI1 go into encrypto mode. 460 * Please do not call this function in SDK. 461 * 462 * @param None 463 * 464 * @return None 465 */ 466 void esp_rom_spiflash_write_encrypted_enable(void); 467 468 /** 469 * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. 470 * Please do not call this function in SDK. 471 * 472 * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. 473 * 474 * @param uint32_t *data : The pointer to data which is to write. 475 * 476 * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. 477 * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. 478 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. 479 */ 480 esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); 481 482 /** 483 * @brief SPI1 go out of encrypto mode. 484 * Please do not call this function in SDK. 485 * 486 * @param None 487 * 488 * @return None 489 */ 490 void esp_rom_spiflash_write_encrypted_disable(void); 491 492 /** 493 * @brief Write data to flash with transparent encryption. 494 * @note Sectors to be written should already be erased. 495 * 496 * @note Please do not call this function in SDK. 497 * 498 * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. 499 * 500 * @param uint32_t *data : The pointer to data to write. Note, this pointer must 501 * be 32 bit aligned and the content of the data will be 502 * modified by the encryption function. 503 * 504 * @param uint32_t len : Length to write, should be 32 bytes aligned. 505 * 506 * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. 507 * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. 508 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. 509 */ 510 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); 511 512 513 /* TODO: figure out how to map these to their new names */ 514 typedef enum { 515 SPI_ENCRYPT_DESTINATION_FLASH, 516 SPI_ENCRYPT_DESTINATION_PSRAM, 517 } SpiEncryptDest; 518 519 typedef esp_rom_spiflash_result_t SpiFlashOpResult; 520 521 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void* data, uint32_t len); 522 SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void* data, uint32_t len); 523 void SPI_Write_Encrypt_Enable(void); 524 void SPI_Write_Encrypt_Disable(void); 525 526 /** @brief Wait until SPI flash write operation is complete 527 * 528 * @note Please do not call this function in SDK. 529 * 530 * Reads the Write In Progress bit of the SPI flash status register, 531 * repeats until this bit is zero (indicating write complete). 532 * 533 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete 534 * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. 535 */ 536 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); 537 538 539 /** @brief Enable Quad I/O pin functions 540 * 541 * @note Please do not call this function in SDK. 542 * 543 * Sets the HD & WP pin functions for Quad I/O modes, based on the 544 * efuse SPI pin configuration. 545 * 546 * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. 547 * 548 * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). 549 * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. 550 * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. 551 * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used 552 * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). 553 * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. 554 */ 555 void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); 556 557 /** 558 * @brief Clear WEL bit unconditionally. 559 * 560 * @return always ESP_ROM_SPIFLASH_RESULT_OK 561 */ 562 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); 563 564 /** @brief Global esp_rom_spiflash_chip_t structure used by ROM functions 565 * 566 */ 567 extern esp_rom_spiflash_chip_t g_rom_flashchip; 568 569 extern uint8_t g_rom_spiflash_dummy_len_plus[]; 570 571 /** 572 * @} 573 */ 574 575 #ifdef __cplusplus 576 } 577 #endif 578 579 #endif /* _ROM_SPI_FLASH_H_ */ 580
