1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_SPI_FLASH_H_ 16 #define _ROM_SPI_FLASH_H_ 17 18 #include <stdint.h> 19 #include <stdbool.h> 20 21 #include "esp_attr.h" 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /** \defgroup spi_flash_apis, spi flash operation related apis 28 * @brief spi_flash apis 29 */ 30 31 /** @addtogroup spi_flash_apis 32 * @{ 33 */ 34 35 #define PERIPHS_SPI_FLASH_CMD SPI_MEM_CMD_REG(1) 36 #define PERIPHS_SPI_FLASH_ADDR SPI_MEM_ADDR_REG(1) 37 #define PERIPHS_SPI_FLASH_CTRL SPI_MEM_CTRL_REG(1) 38 #define PERIPHS_SPI_FLASH_CTRL1 SPI_MEM_CTRL1_REG(1) 39 #define PERIPHS_SPI_FLASH_STATUS SPI_MEM_RD_STATUS_REG(1) 40 #define PERIPHS_SPI_FLASH_USRREG SPI_MEM_USER_REG(1) 41 #define PERIPHS_SPI_FLASH_USRREG1 SPI_MEM_USER1_REG(1) 42 #define PERIPHS_SPI_FLASH_USRREG2 SPI_MEM_USER2_REG(1) 43 #define PERIPHS_SPI_FLASH_C0 SPI_MEM_W0_REG(1) 44 #define PERIPHS_SPI_FLASH_C1 SPI_MEM_W1_REG(1) 45 #define PERIPHS_SPI_FLASH_C2 SPI_MEM_W2_REG(1) 46 #define PERIPHS_SPI_FLASH_C3 SPI_MEM_W3_REG(1) 47 #define PERIPHS_SPI_FLASH_C4 SPI_MEM_W4_REG(1) 48 #define PERIPHS_SPI_FLASH_C5 SPI_MEM_W5_REG(1) 49 #define PERIPHS_SPI_FLASH_C6 SPI_MEM_W6_REG(1) 50 #define PERIPHS_SPI_FLASH_C7 SPI_MEM_W7_REG(1) 51 #define PERIPHS_SPI_FLASH_TX_CRC SPI_MEM_TX_CRC_REG(1) 52 53 #define SPI0_R_QIO_DUMMY_CYCLELEN 5 54 #define SPI0_R_QIO_ADDR_BITSLEN 23 55 #define SPI0_R_FAST_DUMMY_CYCLELEN 7 56 #define SPI0_R_DIO_DUMMY_CYCLELEN 3 57 #define SPI0_R_FAST_ADDR_BITSLEN 23 58 #define SPI0_R_SIO_ADDR_BITSLEN 23 59 60 #define SPI1_R_QIO_DUMMY_CYCLELEN 5 61 #define SPI1_R_QIO_ADDR_BITSLEN 23 62 #define SPI1_R_FAST_DUMMY_CYCLELEN 7 63 #define SPI1_R_DIO_DUMMY_CYCLELEN 3 64 #define SPI1_R_DIO_ADDR_BITSLEN 23 65 #define SPI1_R_FAST_ADDR_BITSLEN 23 66 #define SPI1_R_SIO_ADDR_BITSLEN 23 67 68 #define ESP_ROM_SPIFLASH_W_SIO_ADDR_BITSLEN 23 69 70 #define ESP_ROM_SPIFLASH_TWO_BYTE_STATUS_EN SPI_MEM_WRSR_2B 71 72 //SPI address register 73 #define ESP_ROM_SPIFLASH_BYTES_LEN 24 74 #define ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE_NUM 32 75 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_NUM 16 76 #define ESP_ROM_SPIFLASH_BUFF_BYTE_READ_BITS 0xf 77 78 //SPI status register 79 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 80 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 81 #define ESP_ROM_SPIFLASH_BP0 BIT2 82 #define ESP_ROM_SPIFLASH_BP1 BIT3 83 #define ESP_ROM_SPIFLASH_BP2 BIT4 84 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 85 #define ESP_ROM_SPIFLASH_QE BIT9 86 87 #define FLASH_ID_GD25LQ32C 0xC86016 88 89 typedef enum { 90 ESP_ROM_SPIFLASH_QIO_MODE = 0, 91 ESP_ROM_SPIFLASH_QOUT_MODE, 92 ESP_ROM_SPIFLASH_DIO_MODE, 93 ESP_ROM_SPIFLASH_DOUT_MODE, 94 ESP_ROM_SPIFLASH_FASTRD_MODE, 95 ESP_ROM_SPIFLASH_SLOWRD_MODE 96 } esp_rom_spiflash_read_mode_t; 97 98 typedef enum { 99 ESP_ROM_SPIFLASH_RESULT_OK, 100 ESP_ROM_SPIFLASH_RESULT_ERR, 101 ESP_ROM_SPIFLASH_RESULT_TIMEOUT 102 } esp_rom_spiflash_result_t; 103 104 typedef struct { 105 uint32_t device_id; 106 uint32_t chip_size; // chip size in bytes 107 uint32_t block_size; 108 uint32_t sector_size; 109 uint32_t page_size; 110 uint32_t status_mask; 111 } esp_rom_spiflash_chip_t; 112 113 typedef struct { 114 uint8_t data_length; 115 uint8_t read_cmd0; 116 uint8_t read_cmd1; 117 uint8_t write_cmd; 118 uint16_t data_mask; 119 uint16_t data; 120 } esp_rom_spiflash_common_cmd_t; 121 122 /** 123 * @brief Fix the bug in SPI hardware communication with Flash/Ext-SRAM in High Speed. 124 * Please do not call this function in SDK. 125 * 126 * @param uint8_t spi: 0 for SPI0(Cache Access), 1 for SPI1(Flash read/write). 127 * 128 * @param uint8_t freqdiv: Pll is 80M, 4 for 20M, 3 for 26.7M, 2 for 40M, 1 for 80M. 129 * 130 * @return None 131 */ 132 void esp_rom_spiflash_fix_dummylen(uint8_t spi, uint8_t freqdiv); 133 134 /** 135 * @brief Select SPI Flash to QIO mode when WP pad is read from Flash. 136 * Please do not call this function in SDK. 137 * 138 * @param uint8_t wp_gpio_num: WP gpio number. 139 * 140 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 141 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 142 * 143 * @return None 144 */ 145 void esp_rom_spiflash_select_qiomode(uint8_t wp_gpio_num, uint32_t ishspi); 146 147 /** 148 * @brief Set SPI Flash pad drivers. 149 * Please do not call this function in SDK. 150 * 151 * @param uint8_t wp_gpio_num: WP gpio number. 152 * 153 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 154 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 155 * 156 * @param uint8_t *drvs: drvs[0]-bit[3:0] for cpiclk, bit[7:4] for spiq, drvs[1]-bit[3:0] for spid, drvs[1]-bit[7:4] for spid 157 * drvs[2]-bit[3:0] for spihd, drvs[2]-bit[7:4] for spiwp. 158 * Values usually read from falsh by rom code, function usually callde by rom code. 159 * if value with bit(3) set, the value is valid, bit[2:0] is the real value. 160 * 161 * @return None 162 */ 163 void esp_rom_spiflash_set_drvs(uint8_t wp_gpio_num, uint32_t ishspi, uint8_t *drvs); 164 165 /** 166 * @brief Select SPI Flash function for pads. 167 * Please do not call this function in SDK. 168 * 169 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 170 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 171 * 172 * @return None 173 */ 174 void esp_rom_spiflash_select_padsfunc(uint32_t ishspi); 175 176 /** 177 * @brief SPI Flash init, clock divisor is 4, use 1 line Slow read mode. 178 * Please do not call this function in SDK. 179 * 180 * @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping 181 * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd 182 * 183 * @param uint8_t legacy: In legacy mode, more SPI command is used in line. 184 * 185 * @return None 186 */ 187 void esp_rom_spiflash_attach(uint32_t ishspi, bool legacy); 188 189 /** 190 * @brief SPI Read Flash status register. We use CMD 0x05 (RDSR). 191 * Please do not call this function in SDK. 192 * 193 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 194 * 195 * @param uint32_t *status : The pointer to which to return the Flash status value. 196 * 197 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 198 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 199 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 200 */ 201 esp_rom_spiflash_result_t esp_rom_spiflash_read_status(esp_rom_spiflash_chip_t *spi, uint32_t *status); 202 203 /** 204 * @brief SPI Read Flash status register bits 8-15. We use CMD 0x35 (RDSR2). 205 * Please do not call this function in SDK. 206 * 207 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 208 * 209 * @param uint32_t *status : The pointer to which to return the Flash status value. 210 * 211 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 212 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 213 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 214 */ 215 esp_rom_spiflash_result_t esp_rom_spiflash_read_statushigh(esp_rom_spiflash_chip_t *spi, uint32_t *status); 216 217 /** 218 * @brief Write status to Falsh status register. 219 * Please do not call this function in SDK. 220 * 221 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 222 * 223 * @param uint32_t status_value : Value to . 224 * 225 * @return ESP_ROM_SPIFLASH_RESULT_OK : write OK. 226 * ESP_ROM_SPIFLASH_RESULT_ERR : write error. 227 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : write timeout. 228 */ 229 esp_rom_spiflash_result_t esp_rom_spiflash_write_status(esp_rom_spiflash_chip_t *spi, uint32_t status_value); 230 231 /** 232 * @brief Use a command to Read Flash status register. 233 * Please do not call this function in SDK. 234 * 235 * @param esp_rom_spiflash_chip_t *spi : The information for Flash, which is exported from ld file. 236 * 237 * @param uint32_t*status : The pointer to which to return the Flash status value. 238 * 239 * @return ESP_ROM_SPIFLASH_RESULT_OK : read OK. 240 * ESP_ROM_SPIFLASH_RESULT_ERR : read error. 241 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : read timeout. 242 */ 243 esp_rom_spiflash_result_t esp_rom_spiflash_read_user_cmd(uint32_t *status, uint8_t cmd); 244 245 /** 246 * @brief Config SPI Flash read mode when init. 247 * Please do not call this function in SDK. 248 * 249 * @param esp_rom_spiflash_read_mode_t mode : QIO/QOUT/DIO/DOUT/FastRD/SlowRD. 250 * 251 * This function does not try to set the QIO Enable bit in the status register, caller is responsible for this. 252 * 253 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 254 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 255 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 256 */ 257 esp_rom_spiflash_result_t esp_rom_spiflash_config_readmode(esp_rom_spiflash_read_mode_t mode); 258 259 /** 260 * @brief Config SPI Flash clock divisor. 261 * Please do not call this function in SDK. 262 * 263 * @param uint8_t freqdiv: clock divisor. 264 * 265 * @param uint8_t spi: 0 for SPI0, 1 for SPI1. 266 * 267 * @return ESP_ROM_SPIFLASH_RESULT_OK : config OK. 268 * ESP_ROM_SPIFLASH_RESULT_ERR : config error. 269 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : config timeout. 270 */ 271 esp_rom_spiflash_result_t esp_rom_spiflash_config_clk(uint8_t freqdiv, uint8_t spi); 272 273 /** 274 * @brief Send CommonCmd to Flash so that is can go into QIO mode, some Flash use different CMD. 275 * Please do not call this function in SDK. 276 * 277 * @param esp_rom_spiflash_common_cmd_t *cmd : A struct to show the action of a command. 278 * 279 * @return uint16_t 0 : do not send command any more. 280 * 1 : go to the next command. 281 * n > 1 : skip (n - 1) commands. 282 */ 283 uint16_t esp_rom_spiflash_common_cmd(esp_rom_spiflash_common_cmd_t *cmd); 284 285 /** 286 * @brief Unlock SPI write protect. 287 * Please do not call this function in SDK. 288 * 289 * @param None. 290 * 291 * @return ESP_ROM_SPIFLASH_RESULT_OK : Unlock OK. 292 * ESP_ROM_SPIFLASH_RESULT_ERR : Unlock error. 293 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Unlock timeout. 294 */ 295 esp_rom_spiflash_result_t esp_rom_spiflash_unlock(void); 296 297 /** 298 * @brief SPI write protect. 299 * Please do not call this function in SDK. 300 * 301 * @param None. 302 * 303 * @return ESP_ROM_SPIFLASH_RESULT_OK : Lock OK. 304 * ESP_ROM_SPIFLASH_RESULT_ERR : Lock error. 305 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Lock timeout. 306 */ 307 esp_rom_spiflash_result_t esp_rom_spiflash_lock(void); 308 309 /** 310 * @brief Update SPI Flash parameter. 311 * Please do not call this function in SDK. 312 * 313 * @param uint32_t deviceId : Device ID read from SPI, the low 32 bit. 314 * 315 * @param uint32_t chip_size : The Flash size. 316 * 317 * @param uint32_t block_size : The Flash block size. 318 * 319 * @param uint32_t sector_size : The Flash sector size. 320 * 321 * @param uint32_t page_size : The Flash page size. 322 * 323 * @param uint32_t status_mask : The Mask used when read status from Flash(use single CMD). 324 * 325 * @return ESP_ROM_SPIFLASH_RESULT_OK : Update OK. 326 * ESP_ROM_SPIFLASH_RESULT_ERR : Update error. 327 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Update timeout. 328 */ 329 esp_rom_spiflash_result_t esp_rom_spiflash_config_param(uint32_t deviceId, uint32_t chip_size, uint32_t block_size, 330 uint32_t sector_size, uint32_t page_size, uint32_t status_mask); 331 332 /** 333 * @brief Erase whole flash chip. 334 * Please do not call this function in SDK. 335 * 336 * @param None 337 * 338 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 339 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 340 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 341 */ 342 esp_rom_spiflash_result_t esp_rom_spiflash_erase_chip(void); 343 344 /** 345 * @brief Erase a 64KB block of flash 346 * Uses SPI flash command D8H. 347 * Please do not call this function in SDK. 348 * 349 * @param uint32_t block_num : Which block to erase. 350 * 351 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 352 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 353 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 354 */ 355 esp_rom_spiflash_result_t esp_rom_spiflash_erase_block(uint32_t block_num); 356 357 /** 358 * @brief Erase a sector of flash. 359 * Uses SPI flash command 20H. 360 * Please do not call this function in SDK. 361 * 362 * @param uint32_t sector_num : Which sector to erase. 363 * 364 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 365 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 366 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 367 */ 368 esp_rom_spiflash_result_t esp_rom_spiflash_erase_sector(uint32_t sector_num); 369 370 /** 371 * @brief Erase some sectors. 372 * Please do not call this function in SDK. 373 * 374 * @param uint32_t start_addr : Start addr to erase, should be sector aligned. 375 * 376 * @param uint32_t area_len : Length to erase, should be sector aligned. 377 * 378 * @return ESP_ROM_SPIFLASH_RESULT_OK : Erase OK. 379 * ESP_ROM_SPIFLASH_RESULT_ERR : Erase error. 380 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Erase timeout. 381 */ 382 esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len); 383 384 /** 385 * @brief Write Data to Flash, you should Erase it yourself if need. 386 * Please do not call this function in SDK. 387 * 388 * @param uint32_t dest_addr : Address to write, should be 4 bytes aligned. 389 * 390 * @param const uint32_t *src : The pointer to data which is to write. 391 * 392 * @param uint32_t len : Length to write, should be 4 bytes aligned. 393 * 394 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write OK. 395 * ESP_ROM_SPIFLASH_RESULT_ERR : Write error. 396 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Write timeout. 397 */ 398 esp_rom_spiflash_result_t esp_rom_spiflash_write(uint32_t dest_addr, const uint32_t *src, int32_t len); 399 400 /** 401 * @brief Read Data from Flash, you should Erase it yourself if need. 402 * Please do not call this function in SDK. 403 * 404 * @param uint32_t src_addr : Address to read, should be 4 bytes aligned. 405 * 406 * @param uint32_t *dest : The buf to read the data. 407 * 408 * @param uint32_t len : Length to read, should be 4 bytes aligned. 409 * 410 * @return ESP_ROM_SPIFLASH_RESULT_OK : Read OK. 411 * ESP_ROM_SPIFLASH_RESULT_ERR : Read error. 412 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Read timeout. 413 */ 414 esp_rom_spiflash_result_t esp_rom_spiflash_read(uint32_t src_addr, uint32_t *dest, int32_t len); 415 416 /** 417 * @brief SPI1 go into encrypto mode. 418 * Please do not call this function in SDK. 419 * 420 * @param None 421 * 422 * @return None 423 */ 424 void esp_rom_spiflash_write_encrypted_enable(void); 425 426 /** 427 * @brief Prepare 32 Bytes data to encrpto writing, you should Erase it yourself if need. 428 * Please do not call this function in SDK. 429 * 430 * @param uint32_t flash_addr : Address to write, should be 32 bytes aligned. 431 * 432 * @param uint32_t *data : The pointer to data which is to write. 433 * 434 * @return ESP_ROM_SPIFLASH_RESULT_OK : Prepare OK. 435 * ESP_ROM_SPIFLASH_RESULT_ERR : Prepare error. 436 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Prepare timeout. 437 */ 438 esp_rom_spiflash_result_t esp_rom_spiflash_prepare_encrypted_data(uint32_t flash_addr, uint32_t *data); 439 440 /** 441 * @brief SPI1 go out of encrypto mode. 442 * Please do not call this function in SDK. 443 * 444 * @param None 445 * 446 * @return None 447 */ 448 void esp_rom_spiflash_write_encrypted_disable(void); 449 450 /** 451 * @brief Write data to flash with transparent encryption. 452 * @note Sectors to be written should already be erased. 453 * 454 * @note Please do not call this function in SDK. 455 * 456 * @param uint32_t flash_addr : Address to write, should be 32 byte aligned. 457 * 458 * @param uint32_t *data : The pointer to data to write. Note, this pointer must 459 * be 32 bit aligned and the content of the data will be 460 * modified by the encryption function. 461 * 462 * @param uint32_t len : Length to write, should be 32 bytes aligned. 463 * 464 * @return ESP_ROM_SPIFLASH_RESULT_OK : Data written successfully. 465 * ESP_ROM_SPIFLASH_RESULT_ERR : Encryption write error. 466 * ESP_ROM_SPIFLASH_RESULT_TIMEOUT : Encrypto write timeout. 467 */ 468 esp_rom_spiflash_result_t esp_rom_spiflash_write_encrypted(uint32_t flash_addr, uint32_t *data, uint32_t len); 469 470 471 /* TODO: figure out how to map these to their new names */ 472 typedef enum { 473 SPI_ENCRYPT_DESTINATION_FLASH, 474 } SpiEncryptDest; 475 476 typedef esp_rom_spiflash_result_t SpiFlashOpResult; 477 478 SpiFlashOpResult SPI_Encrypt_Write(uint32_t flash_addr, const void *data, uint32_t len); 479 SpiFlashOpResult SPI_Encrypt_Write_Dest(SpiEncryptDest dest, uint32_t flash_addr, const void *data, uint32_t len); 480 void SPI_Write_Encrypt_Enable(void); 481 void SPI_Write_Encrypt_Disable(void); 482 483 /** @brief Wait until SPI flash write operation is complete 484 * 485 * @note Please do not call this function in SDK. 486 * 487 * Reads the Write In Progress bit of the SPI flash status register, 488 * repeats until this bit is zero (indicating write complete). 489 * 490 * @return ESP_ROM_SPIFLASH_RESULT_OK : Write is complete 491 * ESP_ROM_SPIFLASH_RESULT_ERR : Error while reading status. 492 */ 493 esp_rom_spiflash_result_t esp_rom_spiflash_wait_idle(esp_rom_spiflash_chip_t *spi); 494 495 496 /** @brief Enable Quad I/O pin functions 497 * 498 * @note Please do not call this function in SDK. 499 * 500 * Sets the HD & WP pin functions for Quad I/O modes, based on the 501 * efuse SPI pin configuration. 502 * 503 * @param wp_gpio_num - Number of the WP pin to reconfigure for quad I/O. 504 * 505 * @param spiconfig - Pin configuration, as returned from ets_efuse_get_spiconfig(). 506 * - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is ignored. 507 * - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is ignored. 508 * - For other values, this parameter encodes the HD pin number and also the CLK pin number. CLK pin selection is used 509 * to determine if HSPI or SPI peripheral will be used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI). 510 * Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral. 511 */ 512 void esp_rom_spiflash_select_qio_pins(uint8_t wp_gpio_num, uint32_t spiconfig); 513 514 515 typedef void (* spi_flash_func_t)(void); 516 typedef SpiFlashOpResult (* spi_flash_op_t)(void); 517 typedef SpiFlashOpResult (* spi_flash_erase_t)(uint32_t); 518 typedef SpiFlashOpResult (* spi_flash_rd_t)(uint32_t, uint32_t*, int); 519 typedef SpiFlashOpResult (* spi_flash_wr_t)(uint32_t, const uint32_t*, int); 520 typedef SpiFlashOpResult (* spi_flash_ewr_t)(uint32_t, const void*, uint32_t); 521 typedef SpiFlashOpResult (* spi_flash_wren_t)(void*); 522 523 typedef struct { 524 uint32_t read_sub_len; 525 uint32_t write_sub_len; 526 spi_flash_op_t unlock; 527 spi_flash_erase_t erase_sector; 528 spi_flash_erase_t erase_block; 529 spi_flash_rd_t read; 530 spi_flash_wr_t write; 531 spi_flash_ewr_t encrypt_write; 532 spi_flash_func_t check_sus; 533 spi_flash_wren_t wren; 534 spi_flash_op_t wait_idle; 535 } spiflash_legacy_funcs_t; 536 537 538 extern const spiflash_legacy_funcs_t *rom_spiflash_legacy_funcs; 539 540 /** @brief Global ROM spiflash data, as used by legacy 541 SPI flash functions 542 */ 543 typedef struct { 544 esp_rom_spiflash_chip_t chip; 545 uint8_t dummy_len_plus[3]; 546 uint8_t sig_matrix; 547 } spiflash_legacy_data_t; 548 549 extern spiflash_legacy_data_t *rom_spiflash_legacy_data; 550 551 /* Defines to make the C3 ROM legacvy data access compatible with previous chips */ 552 #define g_rom_flashchip (rom_spiflash_legacy_data->chip) 553 #define g_rom_spiflash_dummy_len_plus (rom_spiflash_legacy_data->dummy_len_plus) 554 555 /** 556 * @brief Clear WEL bit unconditionally. 557 * 558 * @return always ESP_ROM_SPIFLASH_RESULT_OK 559 */ 560 esp_rom_spiflash_result_t esp_rom_spiflash_write_disable(void); 561 562 /** 563 * @} 564 */ 565 566 #ifdef __cplusplus 567 } 568 #endif 569 570 #endif /* _ROM_SPI_FLASH_H_ */ 571
