1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file vbat.h 28 *MEC1501 VBAT Registers and memory definitions 29 */ 30 /** @defgroup MEC1501 Peripherals VBAT 31 */ 32 33 #ifndef _VBAT_H 34 #define _VBAT_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* 42 * VBAT Registers Registers 43 */ 44 45 #define MCHP_VBAT_REGISTERS_ADDR 0x4000a400u 46 #define MCHP_VBAT_MEMORY_ADDR 0x4000a800u 47 #define MCHP_VBAT_MEMORY_SIZE 64u 48 49 /* 50 * Offset 0x00 Power-Fail and Reset Status 51 */ 52 #define MCHP_VBATR_PFRS_OFS 0u 53 #define MCHP_VBATR_PFRS_MASK 0x7cu 54 #define MCHP_VBATR_PFRS_SYS_RST_POS 2u 55 #define MCHP_VBATR_PFRS_JTAG_POS 3u 56 #define MCHP_VBATR_PFRS_RESETI_POS 4u 57 #define MCHP_VBATR_PFRS_WDT_POS 5u 58 #define MCHP_VBATR_PFRS_SYSRESETREQ_POS 6u 59 #define MCHP_VBATR_PFRS_VBAT_RST_POS 7u 60 61 #define MCHP_VBATR_PFRS_SYS_RST BIT(2) 62 #define MCHP_VBATR_PFRS_JTAG BIT(3) 63 #define MCHP_VBATR_PFRS_RESETI BIT(4) 64 #define MCHP_VBATR_PFRS_WDT BIT(5) 65 #define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6) 66 #define MCHP_VBATR_PFRS_VBAT_RST BIT(7) 67 68 /* 69 * Offset 0x08 32K Clock Enable 70 */ 71 #define MCHP_VBATR_CLKEN_OFS 0x08u 72 #define MCHP_VBATR_CLKEN_MASK 0x0eu 73 #define MCHP_VBATR_CLKEN_32K_DOM_POS 1 74 #define MCHP_VBATR_CLKEN_32K_SRC_POS 2 75 #define MCHP_VBATR_CLKEN_XTAL_SEL_POS 3 76 77 #define MCHP_VBATR_CLKEN_32K_DOM_ALWYS_ON 0 78 #define MCHP_VBATR_CLKEN_32K_DOM_32K_IN_PIN BIT(1u << 1) 79 #define MCHP_VBATR_CLKEN_32K_ALWYS_ON_SI_OSC 0 80 #define MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL BIT(2) 81 #define MCHP_VBATR_CLKEN_XTAL12_PARALLEL 0 82 #define MCHP_VBATR_CLKEN_XTAL2_SE_32K BIT(3) 83 84 #define MCHP_VBATR_USE_SIL_OSC 0u 85 #define MCHP_VBATR_USE_32KIN_PIN \ 86 MCHP_VBATR_CLKEN_32K_DOM_32K_IN_PIN 87 #define MCHP_VBATR_USE_PAR_CRYSTAL \ 88 (MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL | \ 89 MCHP_VBATR_CLKEN_XTAL12_PARALLEL) 90 #define MCHP_VBATR_USE_SE_CRYSTAL \ 91 (MCHP_VBATR_CLKEN_32K_ALWYS_ON_XTAL | \ 92 MCHP_VBATR_CLKEN_XTAL2_SE_32K) 93 94 /* Monotonic Counter */ 95 #define MCHP_VBATR_MCNT_LSW_OFS 0x20u 96 #define MCHP_VBATR_MCNT_MSW_OFS 0x24u 97 98 /* Register access */ 99 #define MCHP_VBATR_PFRS() \ 100 REG8(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_PFRS_OFS) 101 102 #define MCHP_VBATR_CLKEN() \ 103 REG8(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_CLKEN_OFS) 104 105 #define MCHP_VBATR_MCNT_LO() \ 106 REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_LSW_OFS) 107 108 #define MCHP_VBATR_MCNT_HI() \ 109 REG32(MCHP_VBAT_REGISTERS_ADDR + MCHP_VBATR_MCNT_MSW_OFS) 110 111 /* =========================================================================*/ 112 /* ================ VBATR ================ */ 113 /* =========================================================================*/ 114 115 /** @brief VBAT Register Bank (VBATR) */ 116 typedef struct vbatr_regs { 117 __IOM uint32_t PFRS; /*! (@ 0x00000000) VBATR Power Fail Reset Status */ 118 uint8_t RSVD1[4]; 119 __IOM uint32_t CLK32_EN; /*! (@ 0x00000008) VBATR 32K clock enable */ 120 __IOM uint32_t SHDN_EN; /*! (@ 0x0000000c) VBATR SHD pin enable */ 121 uint8_t RSVD2[12]; 122 __IOM uint32_t CKK32_TRIM; /*! (@ 0x0000001c) VBATR 32 clock override */ 123 __IOM uint32_t MCNT_LO; /*! (@ 0x00000020) VBATR monotonic count lo */ 124 __IOM uint32_t MCNT_HI; /*! (@ 0x00000024) VBATR monotonic count hi */ 125 } VBATR_Type; 126 127 /* =========================================================================*/ 128 /* ================ VBATM ================ */ 129 /* =========================================================================*/ 130 131 /** @brief VBAT Memory (VBATM) */ 132 #define MCHP_VBAT_MEM_LEN 64u 133 134 typedef struct vbatm_regs { 135 union vbmem_u { 136 uint32_t u32[(MCHP_VBAT_MEM_LEN) / 4]; 137 uint16_t u16[(MCHP_VBAT_MEM_LEN) / 2]; 138 uint8_t u8[MCHP_VBAT_MEM_LEN]; 139 } MEM; 140 } VBATM_Type; 141 142 /* =========================================================================*/ 143 /* ================ VCI =================== */ 144 /* =========================================================================*/ 145 146 #define MCHP_VCI_BASE_ADDR 0x4000ae00u 147 148 /* 149 * VCI interrupts 150 */ 151 #define MCHP_VCI_OVRD_GIRQ 21 152 #define MCHP_VCI_IN0_GIRQ 21 153 #define MCHP_VCI_IN1_GIRQ 21 154 #define MCHP_VCI_IN2_GIRQ 21 155 #define MCHP_VCI_IN3_GIRQ 21 156 157 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 158 #define MCHP_VCI_OVRD_GIRQ_POS 10 159 #define MCHP_VCI_IN0_GIRQ_POS 11 160 #define MCHP_VCI_IN1_GIRQ_POS 12 161 #define MCHP_VCI_IN2_GIRQ_POS 13 162 #define MCHP_VCI_IN3_GIRQ_POS 14 163 164 #define MCHP_VCI_OVRD_GIRQ_VAL BIT(MCHP_VCI_OVRD_GIRQ_POS) 165 #define MCHP_VCI_IN0_GIRQ_VAL BIT(MCHP_VCI_IN0_GIRQ_POS) 166 #define MCHP_VCI_IN1_GIRQ_VAL BIT(MCHP_VCI_IN1_GIRQ_POS) 167 #define MCHP_VCI_IN2_GIRQ_VAL BIT(MCHP_VCI_IN2_GIRQ_POS) 168 #define MCHP_VCI_IN3_GIRQ_VAL BIT(MCHP_VCI_IN3_GIRQ_POS) 169 170 /* VCI GIRQ aggregated NVIC input */ 171 #define MCHP_VCI_OVRD_NVIC_AGGR 13 172 #define MCHP_VCI_IN0_NVIC_AGGR 13 173 #define MCHP_VCI_IN1_NVIC_AGGR 13 174 #define MCHP_VCI_IN2_NVIC_AGGR 13 175 #define MCHP_VCI_IN3_NVIC_AGGR 13 176 177 /* VCI direct NVIC inputs */ 178 #define MCHP_VCI_OVRD_NVIC_DIRECT 121 179 #define MCHP_VCI_IN0_NVIC_DIRECT 122 180 #define MCHP_VCI_IN1_NVIC_DIRECT 123 181 #define MCHP_VCI_IN2_NVIC_DIRECT 124 182 #define MCHP_VCI_IN3_NVIC_DIRECT 125 183 184 /* VCI Config register */ 185 #define MCHP_VCI_CFG_REG_OFS 0 186 #define MCHP_VCI_CFG_REG_MASK 0x00071f8fu 187 #define MCHP_VCI_CFG_IN03_MASK 0x0fu 188 #define MCHP_VCI_CFG_IN0_HI 0x01u 189 #define MCHP_VCI_CFG_IN1_HI 0x02u 190 #define MCHP_VCI_CFG_IN2_HI 0x04u 191 #define MCHP_VCI_CFG_IN3_HI 0x08u 192 #define MCHP_VCI_CFG_VPWR_POS 7 193 #define MCHP_VCI_CFG_VPWR_VTR 0 194 #define MCHP_VCI_CFG_VPWR_VBAT BIT(7) 195 #define MCHP_VCI_VCI_OVRD_IN_PIN BIT(8) 196 #define MCHP_VCI_VCI_OUT_PIN BIT(9) 197 #define MCHP_VCI_FW_CTRL_EN BIT(10) 198 #define MCHP_VCI_FW_EXT_SEL BIT(11) 199 #define MCHP_VCI_FILTER_BYPASS BIT(12) 200 #define MCHP_VCI_WEEK_ALARM BIT(16) 201 #define MCHP_VCI_RTC_ALARM BIT(17) 202 #define MCHP_VCI_SYS_PWR_PRES BIT(18) 203 204 /* VCI Latch Enable register */ 205 #define MCHP_VCI_LE_REG_OFS 4 206 #define MCHP_VCI_LE_REG_MASK 0x0003000fu 207 #define MCHP_VCI_LE_IN03_MASK 0x0fu 208 #define MCHP_VCI_LE_IN0 0x01u 209 #define MCHP_VCI_LE_IN1 0x02u 210 #define MCHP_VCI_LE_IN2 0x04u 211 #define MCHP_VCI_LE_IN3 0x08u 212 #define MCHP_VCI_LE_WEEK_ALARM BIT(16) 213 #define MCHP_VCI_LE_RTC_ALARM BIT(17) 214 215 /* VCI Latch Resets register */ 216 #define MCHP_VCI_LR_REG_OFS 8 217 #define MCHP_VCI_LR_REG_MASK 0x0003000fu 218 #define MCHP_VCI_LR_IN03_MASK 0x0fu 219 #define MCHP_VCI_LR_IN0 0x01u 220 #define MCHP_VCI_LR_IN1 0x02u 221 #define MCHP_VCI_LR_IN2 0x04u 222 #define MCHP_VCI_LR_IN3 0x08u 223 #define MCHP_VCI_LR_WEEK_ALARM BIT(16) 224 #define MCHP_VCI_LR_RTC_ALARM BIT(17) 225 226 /* VCI Input Enable register */ 227 #define MCHP_VCI_INPUT_EN_REG_OFS 0x0c 228 #define MCHP_VCI_INPUT_EN_REG_MASK 0x0fu 229 #define MCHP_VCI_INPUT_EN_IE30_MASK 0x0fu 230 #define MCHP_VCI_INPUT_EN_IN0 0x01u 231 #define MCHP_VCI_INPUT_EN_IN1 0x02u 232 #define MCHP_VCI_INPUT_EN_IN2 0x04u 233 #define MCHP_VCI_INPUT_EN_IN3 0x08u 234 235 /* VCI Hold Off Count register */ 236 #define MCHP_VCI_HDO_REG_OFS 0x10 237 #define MCHP_VCI_HDO_REG_MASK 0xffu 238 239 /* VCI Polarity register */ 240 #define MCHP_VCI_POL_REG_OFS 0x14 241 #define MCHP_VCI_POL_REG_MASK 0x0fu 242 #define MCHP_VCI_POL_IE30_MASK 0x0fu 243 #define MCHP_VCI_POL_ACT_HI_IN0 0x01u 244 #define MCHP_VCI_POL_ACT_HI_IN1 0x02u 245 #define MCHP_VCI_POL_ACT_HI_IN2 0x04u 246 #define MCHP_VCI_POL_ACT_HI_IN3 0x08u 247 248 /* VCI Positive Edge Detect register */ 249 #define MCHP_VCI_PDET_REG_OFS 0x18 250 #define MCHP_VCI_PDET_REG_MASK 0x0fu 251 #define MCHP_VCI_PDET_IE30_MASK 0x0fu 252 #define MCHP_VCI_PDET_IN0 0x01u 253 #define MCHP_VCI_PDET_IN1 0x02u 254 #define MCHP_VCI_PDET_IN2 0x04u 255 #define MCHP_VCI_PDET_IN3 0x08u 256 257 /* VCI Positive Edge Detect register */ 258 #define MCHP_VCI_NDET_REG_OFS 0x1c 259 #define MCHP_VCI_NDET_REG_MASK 0x0fu 260 #define MCHP_VCI_NDET_IE30_MASK 0x0fu 261 #define MCHP_VCI_NDET_IN0 0x01u 262 #define MCHP_VCI_NDET_IN1 0x02u 263 #define MCHP_VCI_NDET_IN2 0x04u 264 #define MCHP_VCI_NDET_IN3 0x08u 265 266 /* VCI Buffer Enable register */ 267 #define MCHP_VCI_BEN_REG_OFS 0x20 268 #define MCHP_VCI_BEN_REG_MASK 0x0fu 269 #define MCHP_VCI_BEN_IE30_MASK 0x0fu 270 #define MCHP_VCI_BEN_IN0 0x01u 271 #define MCHP_VCI_BEN_IN1 0x02u 272 #define MCHP_VCI_BEN_IN2 0x04u 273 #define MCHP_VCI_BEN_IN3 0x08u 274 275 /** @brief VBAT powered control interface (VCI) */ 276 typedef struct vci_regs { 277 __IOM uint32_t CONFIG; /*! (@ 0x0000) VCI Config register */ 278 __IOM uint32_t LATCH_EN; /*! (@ 0x0004) VCI Latch enable register */ 279 __IOM uint32_t LATCH_RST; /*! (@ 0x0008) VCI Latch resets register */ 280 __IOM uint32_t INPUT_EN; /*! (@ 0x000c) VCI Input enable register */ 281 __IOM uint32_t HOLD_OFF; /*! (@ 0x0010) VCI Hold off count register */ 282 __IOM uint32_t POLARITY; /*! (@ 0x0014) VCI Polarity register */ 283 __IOM uint32_t PEDGE_DET; /*! (@ 0x0018) VCI Positive edge detect register */ 284 __IOM uint32_t NEDGE_DET; /*! (@ 0x001c) VCI Negative edge detect register */ 285 __IOM uint32_t BUFFER_EN; /*! (@ 0x0020) VCI Buffer enable register */ 286 } VCI_Type; 287 288 #endif /* #ifndef _VBAT_H */ 289 /* end vbat.h */ 290 /** @} 291 */ 292
