1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file uart.h 28 *MEC1501 UART Peripheral Library API 29 */ 30 /** @defgroup MEC1501 Peripherals UART 31 */ 32 33 #ifndef _UART_H 34 #define _UART_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 #define MCHP_UART0_ID 0u 42 #define MCHP_UART1_ID 1u 43 #define MCHP_UART2_ID 2u 44 #define MCHP_UART_MAX_ID 3u 45 46 #define MCHP_UART_RX_FIFO_MAX_LEN 16u 47 #define MCHP_UART_TX_FIFO_MAX_LEN 16u 48 49 #define MCHP_UART_BAUD_RATE_MIN 50u 50 #define MCHP_UART_BAUD_RATE_MAX 1500000u 51 52 #define MCHP_UART0_BASE_ADDRESS 0x400f2400u 53 #define MCHP_UART1_BASE_ADDRESS 0x400f2800u 54 #define MCHP_UART2_BASE_ADDRESS 0x400f2c00u 55 56 #define MCHP_UART_BASE_ADDR(n) \ 57 (MCHP_UART0_BASE_ADDRESS + ((uint32_t)(n) << 10u)) 58 59 #define MCHP_UART_GIRQ_NUM 15u 60 #define MCHP_UART_GIRQ_ID 7u 61 #define MCHP_UART_GIRQ_SRC_ADDR 0x4000e08cu 62 #define MCHP_UART_GIRQ_EN_SET_ADDR 0x4000e090u 63 #define MCHP_UART_GIRQ_RESULT_ADDR 0x4000e094u 64 #define MCHP_UART_GIRQ_EN_CLR_ADDR 0x4000e098u 65 #define MCHP_UART0_GIRQ_BIT 0u 66 #define MCHP_UART1_GIRQ_BIT 1u 67 #define MCHP_UART2_GIRQ_BIT 4u 68 #define MCHP_UART0_GIRQ_VAL (1u << (MCHP_UART0_GIRQ_BIT)) 69 #define MCHP_UART1_GIRQ_VAL (1u << (MCHP_UART1_GIRQ_BIT)) 70 #define MCHP_UART2_GIRQ_VAL (1u << (MCHP_UART2_GIRQ_BIT)) 71 #define MCHP_UART0_NVIC_DIRECT_NUM 40u 72 #define MCHP_UART1_NVIC_DIRECT_NUM 41u 73 #define MCHP_UART2_NVIC_DIRECT_NUM 44u 74 #define MCHP_UART_NVIC_SETEN_GIRQ_ADDR 0xe000e100u 75 #define MCHP_UART_NVIC_SETEN_GIRQ_BIT 7u /* aggregated */ 76 #define MCHP_UART_NVIC_SETEN_DIRECT_ADDR 0xe000e104u 77 #define MCHP_UART0_NVIC_SETEN_DIRECT_BIT (40u - 32u) 78 #define MCHP_UART1_NVIC_SETEN_DIRECT_BIT (41u - 32u) 79 #define MCHP_UART2_NVIC_SETEN_DIRECT_BIT (44u - 32u) 80 81 /* CMSIS NVIC macro IRQn parameter */ 82 #define MCHP_UART_NVIC_IRQn 7u /* aggregated */ 83 #define MCHP_UART0_NVIC_IRQn 41u /* UART0 direct mode */ 84 #define MCHP_UART1_NVIC_IRQn 42u /* UART1 direct mode */ 85 #define MCHP_UART2_NVIC_IRQn 44u /* UART2 direct mode */ 86 87 /* 88 * LCR DLAB=0 89 * Transmit buffer(WO), Receive buffer(RO) 90 * LCR DLAB=1, BAUD rate divisor LSB 91 */ 92 #define MCHP_UART_RTXB_OFS 0u 93 #define MCHP_UART_BRGD_LSB_OFS 0u 94 95 /* 96 * LCR DLAB=0 97 * Interrupt Enable Register, R/W 98 * LCR DLAB=1, BAUD rate divisor MSB 99 */ 100 #define MCHP_UART_BRGD_MSB_OFS 1u 101 #define MCHP_UART_IER_OFS 1u 102 #define MCHP_UART_IER_MASK 0x0fu 103 #define MCHP_UART_IER_ERDAI 0x01u /* Received data available and timeouts */ 104 #define MCHP_UART_IER_ETHREI 0x02u /* TX Holding register empty */ 105 #define MCHP_UART_IER_ELSI 0x04u /* Errors: Overrun, Parity, Framing, and Break */ 106 #define MCHP_UART_IER_EMSI 0x08u /* Modem Status */ 107 #define MCHP_UART_IER_ALL 0x0fu 108 109 /* FIFO Contro Register, Write-Only */ 110 #define MCHP_UART_FCR_OFS 2u 111 #define MCHP_UART_FCR_MASK 0xcfu 112 #define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */ 113 #define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */ 114 #define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */ 115 #define MCHP_UART_FCR_DMA_EN 0x08u /* DMA Mode Enable. Not implemented */ 116 #define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xc0u /* RX FIFO trigger level mask */ 117 #define MCHP_UART_FCR_RX_FIFO_LVL_1 0x00u 118 #define MCHP_UART_FCR_RX_FIFO_LVL_4 0x40u 119 #define MCHP_UART_FCR_RX_FIFO_LVL_8 0x80u 120 #define MCHP_UART_FCR_RX_FIFO_LVL_14 0xc0u 121 122 /* Interrupt Identification Register, Read-Only */ 123 #define MCHP_UART_IIR_OFS 2u 124 #define MCHP_UART_IIR_MASK 0xcfu 125 #define MCHP_UART_IIR_NOT_IPEND 0x01u 126 #define MCHP_UART_IIR_INTID_MASK0 0x07u 127 #define MCHP_UART_IIR_INTID_POS 1u 128 #define MCHP_UART_IIR_INTID_MASK 0x0eu 129 #define MCHP_UART_IIR_FIFO_EN_MASK 0xc0u 130 /* interrupt values */ 131 #define MCHP_UART_IIR_INT_NONE 0x01u 132 #define MCHP_UART_IIR_INT_LS 0x06u /* Highest priority: Line status, overrun, framing, or break */ 133 #define MCHP_UART_IIR_INT_RX 0x04u /* Highest-1. RX data available or RX FIFO trigger level reached */ 134 #define MCHP_UART_IIR_INT_RX_TMOUT 0x0cu /* Highest-2. RX timeout */ 135 #define MCHP_UART_IIR_INT_THRE 0x02u /* Highest-3. TX Holding register empty. */ 136 #define MCHP_UART_IIR_INT_MS 0x00u /* Highest-4. MODEM status. */ 137 138 /* Line Control Register R/W */ 139 #define MCHP_UART_LCR_OFS 3u 140 #define MCHP_UART_LCR_WORD_LEN_MASK 0x03u 141 #define MCHP_UART_LCR_WORD_LEN_5 0x00u 142 #define MCHP_UART_LCR_WORD_LEN_6 0x01u 143 #define MCHP_UART_LCR_WORD_LEN_7 0x02u 144 #define MCHP_UART_LCR_WORD_LEN_8 0x03u 145 #define MCHP_UART_LCR_STOP_BIT_1 0x00u 146 #define MCHP_UART_LCR_STOP_BIT_2 0x04u /* 2 for 6-8 bits or 1.5 for 5 bits */ 147 #define MCHP_UART_LCR_PARITY_NONE 0x00u 148 #define MCHP_UART_LCR_PARITY_EN 0x08u 149 #define MCHP_UART_LCR_PARITY_ODD 0x00u 150 #define MCHP_UART_LCR_PARITY_EVEN 0x10u 151 #define MCHP_UART_LCR_STICK_PARITY 0x20u 152 #define MCHP_UART_LCR_BREAK_EN 0x40u 153 #define MCHP_UART_LCR_DLAB_EN 0x80u 154 155 /* MODEM Control Register R/W */ 156 #define MCHP_UART_MCR_OFS 4u 157 #define MCHP_UART_MCR_MASK 0x1fu 158 #define MCHP_UART_MCR_DTRn 0x01u 159 #define MCHP_UART_MCR_RTSn 0x02u 160 #define MCHP_UART_MCR_OUT1 0x04u 161 #define MCHP_UART_MCR_OUT2 0x08u 162 #define MCHP_UART_MCR_LOOPBCK_EN 0x10u 163 164 /* Line Status Register RO */ 165 #define MCHP_UART_LSR_OFS 5u 166 #define MCHP_UART_LSR_DATA_RDY 0x01u 167 #define MCHP_UART_LSR_OVERRUN 0x02u 168 #define MCHP_UART_LSR_PARITY 0x04u 169 #define MCHP_UART_LSR_FRAME 0x08u 170 #define MCHP_UART_LSR_RX_BREAK 0x10u 171 #define MCHP_UART_LSR_THRE 0x20u 172 #define MCHP_UART_LSR_TEMT 0x40u 173 #define MCHP_UART_LSR_FIFO_ERR 0x80u 174 #define MCHP_UART_LSR_ANY 0xffu 175 176 /* MODEM Status Register RO */ 177 #define MCHP_UART_MSR_OFS 6u 178 #define MCHP_UART_MSR_DCTS 0x01u 179 #define MCHP_UART_MSR_DDSR 0x02u 180 #define MCHP_UART_MSR_TERI 0x04u 181 #define MCHP_UART_MSR_DDCD 0x08u 182 #define MCHP_UART_MSR_CTS 0x10u 183 #define MCHP_UART_MSR_DSR 0x20u 184 #define MCHP_UART_MSR_RI 0x40u 185 #define MCHP_UART_MSR_DCD 0x80u 186 187 /* Scratch Register RO */ 188 #define MCHP_UART_SCR_OFS 7u 189 190 /* UART Logical Device Activate Register */ 191 #define MCHP_UART_LD_ACT 0x330u 192 #define MCHP_UART_LD_ACTIVATE 0x01u 193 194 /* UART Logical Device Config Register */ 195 #define MCHP_UART_LD_CFG 0x3f0u 196 #define MCHP_UART_LD_CFG_INTCLK (0u << 0) 197 #define MCHP_UART_LD_CFG_EXTCLK (1u << 0) 198 #define MCHP_UART_LD_CFG_RESET_SYS (0u << 1) 199 #define MCHP_UART_LD_CFG_RESET_VCC (1u << 1) 200 #define MCHP_UART_LD_CFG_NO_INVERT (0u << 2) 201 #define MCHP_UART_LD_CFG_INVERT (1u << 2) 202 203 /* BAUD rate generator */ 204 #define MCHP_UART_INT_CLK_24M (1u << 15) 205 206 /* 1.8MHz internal clock source */ 207 #define MCHP_UART_1P8M_BAUD_50 2304u 208 #define MCHP_UART_1P8M_BAUD_110 1536u 209 #define MCHP_UART_1P8M_BAUD_150 768u 210 #define MCHP_UART_1P8M_BAUD_300 384u 211 #define MCHP_UART_1P8M_BAUD_1200 96u 212 #define MCHP_UART_1P8M_BAUD_2400 48u 213 #define MCHP_UART_1P8M_BAUD_9600 12u 214 #define MCHP_UART_1P8M_BAUD_19200 6u 215 #define MCHP_UART_1P8M_BAUD_38400 3u 216 #define MCHP_UART_1P8M_BAUD_57600 2u 217 #define MCHP_UART_1P8M_BAUD_115200 1u 218 219 /* 24MHz internal clock source. n = 24e6 / (BAUD * 16) = 1500000 / BAUD */ 220 #define MCHP_UART_24M_BAUD_115200 ((13u) + (MCHP_UART_INT_CLK_24M)) 221 #define MCHP_UART_24M_BAUD_57600 ((26u) + (MCHP_UART_INT_CLK_24M)) 222 223 /* 224 * Register access by UART zero based ID 225 * 0 <= uart id <= 1 226 */ 227 #define MCHP_UART_TXB_WO_ID(id) \ 228 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS) 229 #define MCHP_UART_RXB_RO_ID(id) \ 230 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_RTXB_OFS) 231 #define MCHP_UART_BRGD_LSB_ID(id) \ 232 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_LSB_OFS) 233 #define MCHP_UART_BRGD_MSB_ID(id) \ 234 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_BRGD_MSB_OFS) 235 #define MCHP_UART_FCR_WO_ID(id) \ 236 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_FCR_OFS) 237 #define MCHP_UART_IIR_RO_ID(id) \ 238 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_IIR_OFS) 239 #define MCHP_UART_LCR_ID(id) \ 240 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LCR_OFS) 241 #define MCHP_UART_MCR_ID(id) \ 242 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MCR_OFS) 243 #define MCHP_UART_LSR_RO_ID(id) \ 244 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_LSR_OFS) 245 #define MCHP_UART_MSR_RO_ID(id) \ 246 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_MSR_OFS) 247 #define MCHP_UART_SCR_ID(id) \ 248 REG8(MCHP_UART_BASE_ADDR(id) + MCHP_UART_SCR_OFS) 249 250 /* 251 * Register access by UART base address 252 */ 253 #define MCHP_UART_TXB_WO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS) 254 #define MCHP_UART_RXB_RO(ba) REG8_OFS((ba), MCHP_UART_RTXB_OFS) 255 #define MCHP_UART_BRGD_LSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_LSB_OFS) 256 #define MCHP_UART_BRGD_MSB(ba) REG8_OFS((ba), MCHP_UART_BRGD_MSB_OFS) 257 #define MCHP_UART_FCR_WO(ba) REG8_OFS((ba), MCHP_UART_FCR_OFS) 258 #define MCHP_UART_IIR_RO(ba) REG8_OFS((ba), MCHP_UART_IIR_OFS) 259 #define MCHP_UART_LCR(ba) REG8_OFS((ba), MCHP_UART_LCR_OFS) 260 #define MCHP_UART_MCR(ba) REG8_OFS((ba), MCHP_UART_MCR_OFS) 261 #define MCHP_UART_LSR_RO(ba) REG8_OFS((ba), MCHP_UART_LSR_OFS) 262 #define MCHP_UART_MSR_RO(ba) REG8_OFS((ba), MCHP_UART_MSR_OFS) 263 #define MCHP_UART_SCR(ba) REG8_OFS((ba), MCHP_UART_SCR_OFS) 264 265 /* =========================================================================*/ 266 /* ================ UART ================ */ 267 /* =========================================================================*/ 268 269 /** 270 * @brief UART interface (UART) 271 */ 272 273 #define MCHP_UART_NUM_INSTANCES 3u 274 #define MCHP_UART_SPACING 0x400u 275 #define MCHP_UART_SPACING_PWROF2 10u 276 277 typedef struct uart_regs 278 { /*!< (@ 0x400f2400) UART Structure */ 279 __IOM uint8_t RTXB; /*!< (@ 0x0000) UART RXB(RO), TXB(WO). BRGD_LSB(RW LCR.DLAB=1) */ 280 __IOM uint8_t IER; /*!< (@ 0x0001) UART IER(RW). BRGD_MSB(RW LCR.DLAB=1) */ 281 __IOM uint8_t IIR_FCR; /*!< (@ 0x0002) UART IIR(RO), FCR(WO) */ 282 __IOM uint8_t LCR; /*!< (@ 0x0003) UART Line Control(RW) */ 283 __IOM uint8_t MCR; /*!< (@ 0x0004) UART Modem Control(RW) */ 284 __IOM uint8_t LSR; /*!< (@ 0x0005) UART Line Status(RO) */ 285 __IOM uint8_t MSR; /*!< (@ 0x0006) UART Modem Status(RO) */ 286 __IOM uint8_t SCR; /*!< (@ 0x0007) UART Scratch(RW) */ 287 uint8_t RSVDA[0x330u - 0x08u]; 288 __IOM uint8_t ACTV; /*!< (@ 0x0330) UART Activate(RW) */ 289 uint8_t RSVDB[0x3f0u - 0x331u]; 290 __IOM uint8_t CFG_SEL; /*!< (@ 0x03f0) UART Configuration Select(RW) */ 291 } UART_Type; 292 293 #endif /* #ifndef _MCHP_UART_H */ 294 /* end uart.h */ 295 /** @} 296 */ 297
