1 /** 2 * \file 3 * 4 * \brief Component description for TC 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_TC_COMPONENT_ 30 #define _SAML21_TC_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR TC */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_TC Basic Timer Counter */ 36 /*@{*/ 37 38 #define TC_U2249 39 #define REV_TC 0x200 40 41 /* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 32) Control A -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint32_t MODE:2; /*!< bit: 2.. 3 Timer Counter Mode */ 48 uint32_t PRESCSYNC:2; /*!< bit: 4.. 5 Prescaler and Counter Synchronization */ 49 uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 50 uint32_t ONDEMAND:1; /*!< bit: 7 Clock On Demand */ 51 uint32_t PRESCALER:3; /*!< bit: 8..10 Prescaler */ 52 uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ 53 uint32_t :4; /*!< bit: 12..15 Reserved */ 54 uint32_t CAPTEN0:1; /*!< bit: 16 Capture Channel 0 Enable */ 55 uint32_t CAPTEN1:1; /*!< bit: 17 Capture Channel 1 Enable */ 56 uint32_t :2; /*!< bit: 18..19 Reserved */ 57 uint32_t COPEN0:1; /*!< bit: 20 Capture On Pin 0 Enable */ 58 uint32_t COPEN1:1; /*!< bit: 21 Capture On Pin 1 Enable */ 59 uint32_t :10; /*!< bit: 22..31 Reserved */ 60 } bit; /*!< Structure used for bit access */ 61 struct { 62 uint32_t :16; /*!< bit: 0..15 Reserved */ 63 uint32_t CAPTEN:2; /*!< bit: 16..17 Capture Channel x Enable */ 64 uint32_t :2; /*!< bit: 18..19 Reserved */ 65 uint32_t COPEN:2; /*!< bit: 20..21 Capture On Pin x Enable */ 66 uint32_t :10; /*!< bit: 22..31 Reserved */ 67 } vec; /*!< Structure used for vec access */ 68 uint32_t reg; /*!< Type used for register access */ 69 } TC_CTRLA_Type; 70 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 71 72 #define TC_CTRLA_OFFSET 0x00 /**< \brief (TC_CTRLA offset) Control A */ 73 #define TC_CTRLA_RESETVALUE _U(0x00000000) /**< \brief (TC_CTRLA reset_value) Control A */ 74 75 #define TC_CTRLA_SWRST_Pos 0 /**< \brief (TC_CTRLA) Software Reset */ 76 #define TC_CTRLA_SWRST (_U(0x1) << TC_CTRLA_SWRST_Pos) 77 #define TC_CTRLA_ENABLE_Pos 1 /**< \brief (TC_CTRLA) Enable */ 78 #define TC_CTRLA_ENABLE (_U(0x1) << TC_CTRLA_ENABLE_Pos) 79 #define TC_CTRLA_MODE_Pos 2 /**< \brief (TC_CTRLA) Timer Counter Mode */ 80 #define TC_CTRLA_MODE_Msk (_U(0x3) << TC_CTRLA_MODE_Pos) 81 #define TC_CTRLA_MODE(value) (TC_CTRLA_MODE_Msk & ((value) << TC_CTRLA_MODE_Pos)) 82 #define TC_CTRLA_MODE_COUNT16_Val _U(0x0) /**< \brief (TC_CTRLA) Counter in 16-bit mode */ 83 #define TC_CTRLA_MODE_COUNT8_Val _U(0x1) /**< \brief (TC_CTRLA) Counter in 8-bit mode */ 84 #define TC_CTRLA_MODE_COUNT32_Val _U(0x2) /**< \brief (TC_CTRLA) Counter in 32-bit mode */ 85 #define TC_CTRLA_MODE_COUNT16 (TC_CTRLA_MODE_COUNT16_Val << TC_CTRLA_MODE_Pos) 86 #define TC_CTRLA_MODE_COUNT8 (TC_CTRLA_MODE_COUNT8_Val << TC_CTRLA_MODE_Pos) 87 #define TC_CTRLA_MODE_COUNT32 (TC_CTRLA_MODE_COUNT32_Val << TC_CTRLA_MODE_Pos) 88 #define TC_CTRLA_PRESCSYNC_Pos 4 /**< \brief (TC_CTRLA) Prescaler and Counter Synchronization */ 89 #define TC_CTRLA_PRESCSYNC_Msk (_U(0x3) << TC_CTRLA_PRESCSYNC_Pos) 90 #define TC_CTRLA_PRESCSYNC(value) (TC_CTRLA_PRESCSYNC_Msk & ((value) << TC_CTRLA_PRESCSYNC_Pos)) 91 #define TC_CTRLA_PRESCSYNC_GCLK_Val _U(0x0) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock */ 92 #define TC_CTRLA_PRESCSYNC_PRESC_Val _U(0x1) /**< \brief (TC_CTRLA) Reload or reset the counter on next prescaler clock */ 93 #define TC_CTRLA_PRESCSYNC_RESYNC_Val _U(0x2) /**< \brief (TC_CTRLA) Reload or reset the counter on next generic clock and reset the prescaler counter */ 94 #define TC_CTRLA_PRESCSYNC_GCLK (TC_CTRLA_PRESCSYNC_GCLK_Val << TC_CTRLA_PRESCSYNC_Pos) 95 #define TC_CTRLA_PRESCSYNC_PRESC (TC_CTRLA_PRESCSYNC_PRESC_Val << TC_CTRLA_PRESCSYNC_Pos) 96 #define TC_CTRLA_PRESCSYNC_RESYNC (TC_CTRLA_PRESCSYNC_RESYNC_Val << TC_CTRLA_PRESCSYNC_Pos) 97 #define TC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (TC_CTRLA) Run during Standby */ 98 #define TC_CTRLA_RUNSTDBY (_U(0x1) << TC_CTRLA_RUNSTDBY_Pos) 99 #define TC_CTRLA_ONDEMAND_Pos 7 /**< \brief (TC_CTRLA) Clock On Demand */ 100 #define TC_CTRLA_ONDEMAND (_U(0x1) << TC_CTRLA_ONDEMAND_Pos) 101 #define TC_CTRLA_PRESCALER_Pos 8 /**< \brief (TC_CTRLA) Prescaler */ 102 #define TC_CTRLA_PRESCALER_Msk (_U(0x7) << TC_CTRLA_PRESCALER_Pos) 103 #define TC_CTRLA_PRESCALER(value) (TC_CTRLA_PRESCALER_Msk & ((value) << TC_CTRLA_PRESCALER_Pos)) 104 #define TC_CTRLA_PRESCALER_DIV1_Val _U(0x0) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC */ 105 #define TC_CTRLA_PRESCALER_DIV2_Val _U(0x1) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/2 */ 106 #define TC_CTRLA_PRESCALER_DIV4_Val _U(0x2) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/4 */ 107 #define TC_CTRLA_PRESCALER_DIV8_Val _U(0x3) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/8 */ 108 #define TC_CTRLA_PRESCALER_DIV16_Val _U(0x4) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/16 */ 109 #define TC_CTRLA_PRESCALER_DIV64_Val _U(0x5) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/64 */ 110 #define TC_CTRLA_PRESCALER_DIV256_Val _U(0x6) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/256 */ 111 #define TC_CTRLA_PRESCALER_DIV1024_Val _U(0x7) /**< \brief (TC_CTRLA) Prescaler: GCLK_TC/1024 */ 112 #define TC_CTRLA_PRESCALER_DIV1 (TC_CTRLA_PRESCALER_DIV1_Val << TC_CTRLA_PRESCALER_Pos) 113 #define TC_CTRLA_PRESCALER_DIV2 (TC_CTRLA_PRESCALER_DIV2_Val << TC_CTRLA_PRESCALER_Pos) 114 #define TC_CTRLA_PRESCALER_DIV4 (TC_CTRLA_PRESCALER_DIV4_Val << TC_CTRLA_PRESCALER_Pos) 115 #define TC_CTRLA_PRESCALER_DIV8 (TC_CTRLA_PRESCALER_DIV8_Val << TC_CTRLA_PRESCALER_Pos) 116 #define TC_CTRLA_PRESCALER_DIV16 (TC_CTRLA_PRESCALER_DIV16_Val << TC_CTRLA_PRESCALER_Pos) 117 #define TC_CTRLA_PRESCALER_DIV64 (TC_CTRLA_PRESCALER_DIV64_Val << TC_CTRLA_PRESCALER_Pos) 118 #define TC_CTRLA_PRESCALER_DIV256 (TC_CTRLA_PRESCALER_DIV256_Val << TC_CTRLA_PRESCALER_Pos) 119 #define TC_CTRLA_PRESCALER_DIV1024 (TC_CTRLA_PRESCALER_DIV1024_Val << TC_CTRLA_PRESCALER_Pos) 120 #define TC_CTRLA_ALOCK_Pos 11 /**< \brief (TC_CTRLA) Auto Lock */ 121 #define TC_CTRLA_ALOCK (_U(0x1) << TC_CTRLA_ALOCK_Pos) 122 #define TC_CTRLA_CAPTEN0_Pos 16 /**< \brief (TC_CTRLA) Capture Channel 0 Enable */ 123 #define TC_CTRLA_CAPTEN0 (1 << TC_CTRLA_CAPTEN0_Pos) 124 #define TC_CTRLA_CAPTEN1_Pos 17 /**< \brief (TC_CTRLA) Capture Channel 1 Enable */ 125 #define TC_CTRLA_CAPTEN1 (1 << TC_CTRLA_CAPTEN1_Pos) 126 #define TC_CTRLA_CAPTEN_Pos 16 /**< \brief (TC_CTRLA) Capture Channel x Enable */ 127 #define TC_CTRLA_CAPTEN_Msk (_U(0x3) << TC_CTRLA_CAPTEN_Pos) 128 #define TC_CTRLA_CAPTEN(value) (TC_CTRLA_CAPTEN_Msk & ((value) << TC_CTRLA_CAPTEN_Pos)) 129 #define TC_CTRLA_COPEN0_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin 0 Enable */ 130 #define TC_CTRLA_COPEN0 (1 << TC_CTRLA_COPEN0_Pos) 131 #define TC_CTRLA_COPEN1_Pos 21 /**< \brief (TC_CTRLA) Capture On Pin 1 Enable */ 132 #define TC_CTRLA_COPEN1 (1 << TC_CTRLA_COPEN1_Pos) 133 #define TC_CTRLA_COPEN_Pos 20 /**< \brief (TC_CTRLA) Capture On Pin x Enable */ 134 #define TC_CTRLA_COPEN_Msk (_U(0x3) << TC_CTRLA_COPEN_Pos) 135 #define TC_CTRLA_COPEN(value) (TC_CTRLA_COPEN_Msk & ((value) << TC_CTRLA_COPEN_Pos)) 136 #define TC_CTRLA_MASK _U(0x00330FFF) /**< \brief (TC_CTRLA) MASK Register */ 137 138 /* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */ 139 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 140 typedef union { 141 struct { 142 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 143 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 144 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 145 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 146 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 147 } bit; /*!< Structure used for bit access */ 148 uint8_t reg; /*!< Type used for register access */ 149 } TC_CTRLBCLR_Type; 150 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 151 152 #define TC_CTRLBCLR_OFFSET 0x04 /**< \brief (TC_CTRLBCLR offset) Control B Clear */ 153 #define TC_CTRLBCLR_RESETVALUE _U(0x00) /**< \brief (TC_CTRLBCLR reset_value) Control B Clear */ 154 155 #define TC_CTRLBCLR_DIR_Pos 0 /**< \brief (TC_CTRLBCLR) Counter Direction */ 156 #define TC_CTRLBCLR_DIR (_U(0x1) << TC_CTRLBCLR_DIR_Pos) 157 #define TC_CTRLBCLR_LUPD_Pos 1 /**< \brief (TC_CTRLBCLR) Lock Update */ 158 #define TC_CTRLBCLR_LUPD (_U(0x1) << TC_CTRLBCLR_LUPD_Pos) 159 #define TC_CTRLBCLR_ONESHOT_Pos 2 /**< \brief (TC_CTRLBCLR) One-Shot on Counter */ 160 #define TC_CTRLBCLR_ONESHOT (_U(0x1) << TC_CTRLBCLR_ONESHOT_Pos) 161 #define TC_CTRLBCLR_CMD_Pos 5 /**< \brief (TC_CTRLBCLR) Command */ 162 #define TC_CTRLBCLR_CMD_Msk (_U(0x7) << TC_CTRLBCLR_CMD_Pos) 163 #define TC_CTRLBCLR_CMD(value) (TC_CTRLBCLR_CMD_Msk & ((value) << TC_CTRLBCLR_CMD_Pos)) 164 #define TC_CTRLBCLR_CMD_NONE_Val _U(0x0) /**< \brief (TC_CTRLBCLR) No action */ 165 #define TC_CTRLBCLR_CMD_RETRIGGER_Val _U(0x1) /**< \brief (TC_CTRLBCLR) Force a start, restart or retrigger */ 166 #define TC_CTRLBCLR_CMD_STOP_Val _U(0x2) /**< \brief (TC_CTRLBCLR) Force a stop */ 167 #define TC_CTRLBCLR_CMD_UPDATE_Val _U(0x3) /**< \brief (TC_CTRLBCLR) Force update of double-buffered register */ 168 #define TC_CTRLBCLR_CMD_READSYNC_Val _U(0x4) /**< \brief (TC_CTRLBCLR) Force a read synchronization of COUNT */ 169 #define TC_CTRLBCLR_CMD_DMAOS_Val _U(0x5) /**< \brief (TC_CTRLBCLR) One-shot DMA trigger */ 170 #define TC_CTRLBCLR_CMD_NONE (TC_CTRLBCLR_CMD_NONE_Val << TC_CTRLBCLR_CMD_Pos) 171 #define TC_CTRLBCLR_CMD_RETRIGGER (TC_CTRLBCLR_CMD_RETRIGGER_Val << TC_CTRLBCLR_CMD_Pos) 172 #define TC_CTRLBCLR_CMD_STOP (TC_CTRLBCLR_CMD_STOP_Val << TC_CTRLBCLR_CMD_Pos) 173 #define TC_CTRLBCLR_CMD_UPDATE (TC_CTRLBCLR_CMD_UPDATE_Val << TC_CTRLBCLR_CMD_Pos) 174 #define TC_CTRLBCLR_CMD_READSYNC (TC_CTRLBCLR_CMD_READSYNC_Val << TC_CTRLBCLR_CMD_Pos) 175 #define TC_CTRLBCLR_CMD_DMAOS (TC_CTRLBCLR_CMD_DMAOS_Val << TC_CTRLBCLR_CMD_Pos) 176 #define TC_CTRLBCLR_MASK _U(0xE7) /**< \brief (TC_CTRLBCLR) MASK Register */ 177 178 /* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */ 179 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 180 typedef union { 181 struct { 182 uint8_t DIR:1; /*!< bit: 0 Counter Direction */ 183 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 184 uint8_t ONESHOT:1; /*!< bit: 2 One-Shot on Counter */ 185 uint8_t :2; /*!< bit: 3.. 4 Reserved */ 186 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 187 } bit; /*!< Structure used for bit access */ 188 uint8_t reg; /*!< Type used for register access */ 189 } TC_CTRLBSET_Type; 190 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 191 192 #define TC_CTRLBSET_OFFSET 0x05 /**< \brief (TC_CTRLBSET offset) Control B Set */ 193 #define TC_CTRLBSET_RESETVALUE _U(0x00) /**< \brief (TC_CTRLBSET reset_value) Control B Set */ 194 195 #define TC_CTRLBSET_DIR_Pos 0 /**< \brief (TC_CTRLBSET) Counter Direction */ 196 #define TC_CTRLBSET_DIR (_U(0x1) << TC_CTRLBSET_DIR_Pos) 197 #define TC_CTRLBSET_LUPD_Pos 1 /**< \brief (TC_CTRLBSET) Lock Update */ 198 #define TC_CTRLBSET_LUPD (_U(0x1) << TC_CTRLBSET_LUPD_Pos) 199 #define TC_CTRLBSET_ONESHOT_Pos 2 /**< \brief (TC_CTRLBSET) One-Shot on Counter */ 200 #define TC_CTRLBSET_ONESHOT (_U(0x1) << TC_CTRLBSET_ONESHOT_Pos) 201 #define TC_CTRLBSET_CMD_Pos 5 /**< \brief (TC_CTRLBSET) Command */ 202 #define TC_CTRLBSET_CMD_Msk (_U(0x7) << TC_CTRLBSET_CMD_Pos) 203 #define TC_CTRLBSET_CMD(value) (TC_CTRLBSET_CMD_Msk & ((value) << TC_CTRLBSET_CMD_Pos)) 204 #define TC_CTRLBSET_CMD_NONE_Val _U(0x0) /**< \brief (TC_CTRLBSET) No action */ 205 #define TC_CTRLBSET_CMD_RETRIGGER_Val _U(0x1) /**< \brief (TC_CTRLBSET) Force a start, restart or retrigger */ 206 #define TC_CTRLBSET_CMD_STOP_Val _U(0x2) /**< \brief (TC_CTRLBSET) Force a stop */ 207 #define TC_CTRLBSET_CMD_UPDATE_Val _U(0x3) /**< \brief (TC_CTRLBSET) Force update of double-buffered register */ 208 #define TC_CTRLBSET_CMD_READSYNC_Val _U(0x4) /**< \brief (TC_CTRLBSET) Force a read synchronization of COUNT */ 209 #define TC_CTRLBSET_CMD_DMAOS_Val _U(0x5) /**< \brief (TC_CTRLBSET) One-shot DMA trigger */ 210 #define TC_CTRLBSET_CMD_NONE (TC_CTRLBSET_CMD_NONE_Val << TC_CTRLBSET_CMD_Pos) 211 #define TC_CTRLBSET_CMD_RETRIGGER (TC_CTRLBSET_CMD_RETRIGGER_Val << TC_CTRLBSET_CMD_Pos) 212 #define TC_CTRLBSET_CMD_STOP (TC_CTRLBSET_CMD_STOP_Val << TC_CTRLBSET_CMD_Pos) 213 #define TC_CTRLBSET_CMD_UPDATE (TC_CTRLBSET_CMD_UPDATE_Val << TC_CTRLBSET_CMD_Pos) 214 #define TC_CTRLBSET_CMD_READSYNC (TC_CTRLBSET_CMD_READSYNC_Val << TC_CTRLBSET_CMD_Pos) 215 #define TC_CTRLBSET_CMD_DMAOS (TC_CTRLBSET_CMD_DMAOS_Val << TC_CTRLBSET_CMD_Pos) 216 #define TC_CTRLBSET_MASK _U(0xE7) /**< \brief (TC_CTRLBSET) MASK Register */ 217 218 /* -------- TC_EVCTRL : (TC Offset: 0x06) (R/W 16) Event Control -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { 221 struct { 222 uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */ 223 uint16_t :1; /*!< bit: 3 Reserved */ 224 uint16_t TCINV:1; /*!< bit: 4 TC Event Input Polarity */ 225 uint16_t TCEI:1; /*!< bit: 5 TC Event Enable */ 226 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 227 uint16_t OVFEO:1; /*!< bit: 8 Event Output Enable */ 228 uint16_t :3; /*!< bit: 9..11 Reserved */ 229 uint16_t MCEO0:1; /*!< bit: 12 MC Event Output Enable 0 */ 230 uint16_t MCEO1:1; /*!< bit: 13 MC Event Output Enable 1 */ 231 uint16_t :2; /*!< bit: 14..15 Reserved */ 232 } bit; /*!< Structure used for bit access */ 233 struct { 234 uint16_t :12; /*!< bit: 0..11 Reserved */ 235 uint16_t MCEO:2; /*!< bit: 12..13 MC Event Output Enable x */ 236 uint16_t :2; /*!< bit: 14..15 Reserved */ 237 } vec; /*!< Structure used for vec access */ 238 uint16_t reg; /*!< Type used for register access */ 239 } TC_EVCTRL_Type; 240 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 241 242 #define TC_EVCTRL_OFFSET 0x06 /**< \brief (TC_EVCTRL offset) Event Control */ 243 #define TC_EVCTRL_RESETVALUE _U(0x0000) /**< \brief (TC_EVCTRL reset_value) Event Control */ 244 245 #define TC_EVCTRL_EVACT_Pos 0 /**< \brief (TC_EVCTRL) Event Action */ 246 #define TC_EVCTRL_EVACT_Msk (_U(0x7) << TC_EVCTRL_EVACT_Pos) 247 #define TC_EVCTRL_EVACT(value) (TC_EVCTRL_EVACT_Msk & ((value) << TC_EVCTRL_EVACT_Pos)) 248 #define TC_EVCTRL_EVACT_OFF_Val _U(0x0) /**< \brief (TC_EVCTRL) Event action disabled */ 249 #define TC_EVCTRL_EVACT_RETRIGGER_Val _U(0x1) /**< \brief (TC_EVCTRL) Start, restart or retrigger TC on event */ 250 #define TC_EVCTRL_EVACT_COUNT_Val _U(0x2) /**< \brief (TC_EVCTRL) Count on event */ 251 #define TC_EVCTRL_EVACT_START_Val _U(0x3) /**< \brief (TC_EVCTRL) Start TC on event */ 252 #define TC_EVCTRL_EVACT_STAMP_Val _U(0x4) /**< \brief (TC_EVCTRL) Time stamp capture */ 253 #define TC_EVCTRL_EVACT_PPW_Val _U(0x5) /**< \brief (TC_EVCTRL) Period captured in CC0, pulse width in CC1 */ 254 #define TC_EVCTRL_EVACT_PWP_Val _U(0x6) /**< \brief (TC_EVCTRL) Period captured in CC1, pulse width in CC0 */ 255 #define TC_EVCTRL_EVACT_PW_Val _U(0x7) /**< \brief (TC_EVCTRL) Pulse width capture */ 256 #define TC_EVCTRL_EVACT_OFF (TC_EVCTRL_EVACT_OFF_Val << TC_EVCTRL_EVACT_Pos) 257 #define TC_EVCTRL_EVACT_RETRIGGER (TC_EVCTRL_EVACT_RETRIGGER_Val << TC_EVCTRL_EVACT_Pos) 258 #define TC_EVCTRL_EVACT_COUNT (TC_EVCTRL_EVACT_COUNT_Val << TC_EVCTRL_EVACT_Pos) 259 #define TC_EVCTRL_EVACT_START (TC_EVCTRL_EVACT_START_Val << TC_EVCTRL_EVACT_Pos) 260 #define TC_EVCTRL_EVACT_STAMP (TC_EVCTRL_EVACT_STAMP_Val << TC_EVCTRL_EVACT_Pos) 261 #define TC_EVCTRL_EVACT_PPW (TC_EVCTRL_EVACT_PPW_Val << TC_EVCTRL_EVACT_Pos) 262 #define TC_EVCTRL_EVACT_PWP (TC_EVCTRL_EVACT_PWP_Val << TC_EVCTRL_EVACT_Pos) 263 #define TC_EVCTRL_EVACT_PW (TC_EVCTRL_EVACT_PW_Val << TC_EVCTRL_EVACT_Pos) 264 #define TC_EVCTRL_TCINV_Pos 4 /**< \brief (TC_EVCTRL) TC Event Input Polarity */ 265 #define TC_EVCTRL_TCINV (_U(0x1) << TC_EVCTRL_TCINV_Pos) 266 #define TC_EVCTRL_TCEI_Pos 5 /**< \brief (TC_EVCTRL) TC Event Enable */ 267 #define TC_EVCTRL_TCEI (_U(0x1) << TC_EVCTRL_TCEI_Pos) 268 #define TC_EVCTRL_OVFEO_Pos 8 /**< \brief (TC_EVCTRL) Event Output Enable */ 269 #define TC_EVCTRL_OVFEO (_U(0x1) << TC_EVCTRL_OVFEO_Pos) 270 #define TC_EVCTRL_MCEO0_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable 0 */ 271 #define TC_EVCTRL_MCEO0 (1 << TC_EVCTRL_MCEO0_Pos) 272 #define TC_EVCTRL_MCEO1_Pos 13 /**< \brief (TC_EVCTRL) MC Event Output Enable 1 */ 273 #define TC_EVCTRL_MCEO1 (1 << TC_EVCTRL_MCEO1_Pos) 274 #define TC_EVCTRL_MCEO_Pos 12 /**< \brief (TC_EVCTRL) MC Event Output Enable x */ 275 #define TC_EVCTRL_MCEO_Msk (_U(0x3) << TC_EVCTRL_MCEO_Pos) 276 #define TC_EVCTRL_MCEO(value) (TC_EVCTRL_MCEO_Msk & ((value) << TC_EVCTRL_MCEO_Pos)) 277 #define TC_EVCTRL_MASK _U(0x3137) /**< \brief (TC_EVCTRL) MASK Register */ 278 279 /* -------- TC_INTENCLR : (TC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 280 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 281 typedef union { 282 struct { 283 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Disable */ 284 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Disable */ 285 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 286 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Disable 0 */ 287 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Disable 1 */ 288 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 289 } bit; /*!< Structure used for bit access */ 290 struct { 291 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 292 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Disable x */ 293 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 294 } vec; /*!< Structure used for vec access */ 295 uint8_t reg; /*!< Type used for register access */ 296 } TC_INTENCLR_Type; 297 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 298 299 #define TC_INTENCLR_OFFSET 0x08 /**< \brief (TC_INTENCLR offset) Interrupt Enable Clear */ 300 #define TC_INTENCLR_RESETVALUE _U(0x00) /**< \brief (TC_INTENCLR reset_value) Interrupt Enable Clear */ 301 302 #define TC_INTENCLR_OVF_Pos 0 /**< \brief (TC_INTENCLR) OVF Interrupt Disable */ 303 #define TC_INTENCLR_OVF (_U(0x1) << TC_INTENCLR_OVF_Pos) 304 #define TC_INTENCLR_ERR_Pos 1 /**< \brief (TC_INTENCLR) ERR Interrupt Disable */ 305 #define TC_INTENCLR_ERR (_U(0x1) << TC_INTENCLR_ERR_Pos) 306 #define TC_INTENCLR_MC0_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable 0 */ 307 #define TC_INTENCLR_MC0 (1 << TC_INTENCLR_MC0_Pos) 308 #define TC_INTENCLR_MC1_Pos 5 /**< \brief (TC_INTENCLR) MC Interrupt Disable 1 */ 309 #define TC_INTENCLR_MC1 (1 << TC_INTENCLR_MC1_Pos) 310 #define TC_INTENCLR_MC_Pos 4 /**< \brief (TC_INTENCLR) MC Interrupt Disable x */ 311 #define TC_INTENCLR_MC_Msk (_U(0x3) << TC_INTENCLR_MC_Pos) 312 #define TC_INTENCLR_MC(value) (TC_INTENCLR_MC_Msk & ((value) << TC_INTENCLR_MC_Pos)) 313 #define TC_INTENCLR_MASK _U(0x33) /**< \brief (TC_INTENCLR) MASK Register */ 314 315 /* -------- TC_INTENSET : (TC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 316 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 317 typedef union { 318 struct { 319 uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Enable */ 320 uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Enable */ 321 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 322 uint8_t MC0:1; /*!< bit: 4 MC Interrupt Enable 0 */ 323 uint8_t MC1:1; /*!< bit: 5 MC Interrupt Enable 1 */ 324 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 325 } bit; /*!< Structure used for bit access */ 326 struct { 327 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 328 uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Enable x */ 329 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 330 } vec; /*!< Structure used for vec access */ 331 uint8_t reg; /*!< Type used for register access */ 332 } TC_INTENSET_Type; 333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 #define TC_INTENSET_OFFSET 0x09 /**< \brief (TC_INTENSET offset) Interrupt Enable Set */ 336 #define TC_INTENSET_RESETVALUE _U(0x00) /**< \brief (TC_INTENSET reset_value) Interrupt Enable Set */ 337 338 #define TC_INTENSET_OVF_Pos 0 /**< \brief (TC_INTENSET) OVF Interrupt Enable */ 339 #define TC_INTENSET_OVF (_U(0x1) << TC_INTENSET_OVF_Pos) 340 #define TC_INTENSET_ERR_Pos 1 /**< \brief (TC_INTENSET) ERR Interrupt Enable */ 341 #define TC_INTENSET_ERR (_U(0x1) << TC_INTENSET_ERR_Pos) 342 #define TC_INTENSET_MC0_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable 0 */ 343 #define TC_INTENSET_MC0 (1 << TC_INTENSET_MC0_Pos) 344 #define TC_INTENSET_MC1_Pos 5 /**< \brief (TC_INTENSET) MC Interrupt Enable 1 */ 345 #define TC_INTENSET_MC1 (1 << TC_INTENSET_MC1_Pos) 346 #define TC_INTENSET_MC_Pos 4 /**< \brief (TC_INTENSET) MC Interrupt Enable x */ 347 #define TC_INTENSET_MC_Msk (_U(0x3) << TC_INTENSET_MC_Pos) 348 #define TC_INTENSET_MC(value) (TC_INTENSET_MC_Msk & ((value) << TC_INTENSET_MC_Pos)) 349 #define TC_INTENSET_MASK _U(0x33) /**< \brief (TC_INTENSET) MASK Register */ 350 351 /* -------- TC_INTFLAG : (TC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 352 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 353 typedef union { // __I to avoid read-modify-write on write-to-clear register 354 struct { 355 __I uint8_t OVF:1; /*!< bit: 0 OVF Interrupt Flag */ 356 __I uint8_t ERR:1; /*!< bit: 1 ERR Interrupt Flag */ 357 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ 358 __I uint8_t MC0:1; /*!< bit: 4 MC Interrupt Flag 0 */ 359 __I uint8_t MC1:1; /*!< bit: 5 MC Interrupt Flag 1 */ 360 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 361 } bit; /*!< Structure used for bit access */ 362 struct { 363 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ 364 __I uint8_t MC:2; /*!< bit: 4.. 5 MC Interrupt Flag x */ 365 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 366 } vec; /*!< Structure used for vec access */ 367 uint8_t reg; /*!< Type used for register access */ 368 } TC_INTFLAG_Type; 369 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 370 371 #define TC_INTFLAG_OFFSET 0x0A /**< \brief (TC_INTFLAG offset) Interrupt Flag Status and Clear */ 372 #define TC_INTFLAG_RESETVALUE _U(0x00) /**< \brief (TC_INTFLAG reset_value) Interrupt Flag Status and Clear */ 373 374 #define TC_INTFLAG_OVF_Pos 0 /**< \brief (TC_INTFLAG) OVF Interrupt Flag */ 375 #define TC_INTFLAG_OVF (_U(0x1) << TC_INTFLAG_OVF_Pos) 376 #define TC_INTFLAG_ERR_Pos 1 /**< \brief (TC_INTFLAG) ERR Interrupt Flag */ 377 #define TC_INTFLAG_ERR (_U(0x1) << TC_INTFLAG_ERR_Pos) 378 #define TC_INTFLAG_MC0_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag 0 */ 379 #define TC_INTFLAG_MC0 (1 << TC_INTFLAG_MC0_Pos) 380 #define TC_INTFLAG_MC1_Pos 5 /**< \brief (TC_INTFLAG) MC Interrupt Flag 1 */ 381 #define TC_INTFLAG_MC1 (1 << TC_INTFLAG_MC1_Pos) 382 #define TC_INTFLAG_MC_Pos 4 /**< \brief (TC_INTFLAG) MC Interrupt Flag x */ 383 #define TC_INTFLAG_MC_Msk (_U(0x3) << TC_INTFLAG_MC_Pos) 384 #define TC_INTFLAG_MC(value) (TC_INTFLAG_MC_Msk & ((value) << TC_INTFLAG_MC_Pos)) 385 #define TC_INTFLAG_MASK _U(0x33) /**< \brief (TC_INTFLAG) MASK Register */ 386 387 /* -------- TC_STATUS : (TC Offset: 0x0B) (R/W 8) Status -------- */ 388 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 389 typedef union { 390 struct { 391 uint8_t STOP:1; /*!< bit: 0 Stop Status Flag */ 392 uint8_t SLAVE:1; /*!< bit: 1 Slave Status Flag */ 393 uint8_t :1; /*!< bit: 2 Reserved */ 394 uint8_t PERBUFV:1; /*!< bit: 3 Synchronization Busy Status */ 395 uint8_t CCBUFV0:1; /*!< bit: 4 Compare channel buffer 0 valid */ 396 uint8_t CCBUFV1:1; /*!< bit: 5 Compare channel buffer 1 valid */ 397 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 398 } bit; /*!< Structure used for bit access */ 399 struct { 400 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 401 uint8_t CCBUFV:2; /*!< bit: 4.. 5 Compare channel buffer x valid */ 402 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 403 } vec; /*!< Structure used for vec access */ 404 uint8_t reg; /*!< Type used for register access */ 405 } TC_STATUS_Type; 406 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 407 408 #define TC_STATUS_OFFSET 0x0B /**< \brief (TC_STATUS offset) Status */ 409 #define TC_STATUS_RESETVALUE _U(0x01) /**< \brief (TC_STATUS reset_value) Status */ 410 411 #define TC_STATUS_STOP_Pos 0 /**< \brief (TC_STATUS) Stop Status Flag */ 412 #define TC_STATUS_STOP (_U(0x1) << TC_STATUS_STOP_Pos) 413 #define TC_STATUS_SLAVE_Pos 1 /**< \brief (TC_STATUS) Slave Status Flag */ 414 #define TC_STATUS_SLAVE (_U(0x1) << TC_STATUS_SLAVE_Pos) 415 #define TC_STATUS_PERBUFV_Pos 3 /**< \brief (TC_STATUS) Synchronization Busy Status */ 416 #define TC_STATUS_PERBUFV (_U(0x1) << TC_STATUS_PERBUFV_Pos) 417 #define TC_STATUS_CCBUFV0_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer 0 valid */ 418 #define TC_STATUS_CCBUFV0 (1 << TC_STATUS_CCBUFV0_Pos) 419 #define TC_STATUS_CCBUFV1_Pos 5 /**< \brief (TC_STATUS) Compare channel buffer 1 valid */ 420 #define TC_STATUS_CCBUFV1 (1 << TC_STATUS_CCBUFV1_Pos) 421 #define TC_STATUS_CCBUFV_Pos 4 /**< \brief (TC_STATUS) Compare channel buffer x valid */ 422 #define TC_STATUS_CCBUFV_Msk (_U(0x3) << TC_STATUS_CCBUFV_Pos) 423 #define TC_STATUS_CCBUFV(value) (TC_STATUS_CCBUFV_Msk & ((value) << TC_STATUS_CCBUFV_Pos)) 424 #define TC_STATUS_MASK _U(0x3B) /**< \brief (TC_STATUS) MASK Register */ 425 426 /* -------- TC_WAVE : (TC Offset: 0x0C) (R/W 8) Waveform Generation Control -------- */ 427 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 428 typedef union { 429 struct { 430 uint8_t WAVEGEN:2; /*!< bit: 0.. 1 Waveform Generation Mode */ 431 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 432 } bit; /*!< Structure used for bit access */ 433 uint8_t reg; /*!< Type used for register access */ 434 } TC_WAVE_Type; 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 #define TC_WAVE_OFFSET 0x0C /**< \brief (TC_WAVE offset) Waveform Generation Control */ 438 #define TC_WAVE_RESETVALUE _U(0x00) /**< \brief (TC_WAVE reset_value) Waveform Generation Control */ 439 440 #define TC_WAVE_WAVEGEN_Pos 0 /**< \brief (TC_WAVE) Waveform Generation Mode */ 441 #define TC_WAVE_WAVEGEN_Msk (_U(0x3) << TC_WAVE_WAVEGEN_Pos) 442 #define TC_WAVE_WAVEGEN(value) (TC_WAVE_WAVEGEN_Msk & ((value) << TC_WAVE_WAVEGEN_Pos)) 443 #define TC_WAVE_WAVEGEN_NFRQ_Val _U(0x0) /**< \brief (TC_WAVE) Normal frequency */ 444 #define TC_WAVE_WAVEGEN_MFRQ_Val _U(0x1) /**< \brief (TC_WAVE) Match frequency */ 445 #define TC_WAVE_WAVEGEN_NPWM_Val _U(0x2) /**< \brief (TC_WAVE) Normal PWM */ 446 #define TC_WAVE_WAVEGEN_MPWM_Val _U(0x3) /**< \brief (TC_WAVE) Match PWM */ 447 #define TC_WAVE_WAVEGEN_NFRQ (TC_WAVE_WAVEGEN_NFRQ_Val << TC_WAVE_WAVEGEN_Pos) 448 #define TC_WAVE_WAVEGEN_MFRQ (TC_WAVE_WAVEGEN_MFRQ_Val << TC_WAVE_WAVEGEN_Pos) 449 #define TC_WAVE_WAVEGEN_NPWM (TC_WAVE_WAVEGEN_NPWM_Val << TC_WAVE_WAVEGEN_Pos) 450 #define TC_WAVE_WAVEGEN_MPWM (TC_WAVE_WAVEGEN_MPWM_Val << TC_WAVE_WAVEGEN_Pos) 451 #define TC_WAVE_MASK _U(0x03) /**< \brief (TC_WAVE) MASK Register */ 452 453 /* -------- TC_DRVCTRL : (TC Offset: 0x0D) (R/W 8) Control C -------- */ 454 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 455 typedef union { 456 struct { 457 uint8_t INVEN0:1; /*!< bit: 0 Output Waveform Invert Enable 0 */ 458 uint8_t INVEN1:1; /*!< bit: 1 Output Waveform Invert Enable 1 */ 459 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 460 } bit; /*!< Structure used for bit access */ 461 struct { 462 uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform Invert Enable x */ 463 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 464 } vec; /*!< Structure used for vec access */ 465 uint8_t reg; /*!< Type used for register access */ 466 } TC_DRVCTRL_Type; 467 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 468 469 #define TC_DRVCTRL_OFFSET 0x0D /**< \brief (TC_DRVCTRL offset) Control C */ 470 #define TC_DRVCTRL_RESETVALUE _U(0x00) /**< \brief (TC_DRVCTRL reset_value) Control C */ 471 472 #define TC_DRVCTRL_INVEN0_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 0 */ 473 #define TC_DRVCTRL_INVEN0 (1 << TC_DRVCTRL_INVEN0_Pos) 474 #define TC_DRVCTRL_INVEN1_Pos 1 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable 1 */ 475 #define TC_DRVCTRL_INVEN1 (1 << TC_DRVCTRL_INVEN1_Pos) 476 #define TC_DRVCTRL_INVEN_Pos 0 /**< \brief (TC_DRVCTRL) Output Waveform Invert Enable x */ 477 #define TC_DRVCTRL_INVEN_Msk (_U(0x3) << TC_DRVCTRL_INVEN_Pos) 478 #define TC_DRVCTRL_INVEN(value) (TC_DRVCTRL_INVEN_Msk & ((value) << TC_DRVCTRL_INVEN_Pos)) 479 #define TC_DRVCTRL_MASK _U(0x03) /**< \brief (TC_DRVCTRL) MASK Register */ 480 481 /* -------- TC_DBGCTRL : (TC Offset: 0x0F) (R/W 8) Debug Control -------- */ 482 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 483 typedef union { 484 struct { 485 uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */ 486 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 487 } bit; /*!< Structure used for bit access */ 488 uint8_t reg; /*!< Type used for register access */ 489 } TC_DBGCTRL_Type; 490 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 491 492 #define TC_DBGCTRL_OFFSET 0x0F /**< \brief (TC_DBGCTRL offset) Debug Control */ 493 #define TC_DBGCTRL_RESETVALUE _U(0x00) /**< \brief (TC_DBGCTRL reset_value) Debug Control */ 494 495 #define TC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (TC_DBGCTRL) Run During Debug */ 496 #define TC_DBGCTRL_DBGRUN (_U(0x1) << TC_DBGCTRL_DBGRUN_Pos) 497 #define TC_DBGCTRL_MASK _U(0x01) /**< \brief (TC_DBGCTRL) MASK Register */ 498 499 /* -------- TC_SYNCBUSY : (TC Offset: 0x10) (R/ 32) Synchronization Status -------- */ 500 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 501 typedef union { 502 struct { 503 uint32_t SWRST:1; /*!< bit: 0 swrst */ 504 uint32_t ENABLE:1; /*!< bit: 1 enable */ 505 uint32_t CTRLB:1; /*!< bit: 2 CTRLB */ 506 uint32_t STATUS:1; /*!< bit: 3 STATUS */ 507 uint32_t COUNT:1; /*!< bit: 4 Counter */ 508 uint32_t PER:1; /*!< bit: 5 Period */ 509 uint32_t CC0:1; /*!< bit: 6 Compare Channel 0 */ 510 uint32_t CC1:1; /*!< bit: 7 Compare Channel 1 */ 511 uint32_t :24; /*!< bit: 8..31 Reserved */ 512 } bit; /*!< Structure used for bit access */ 513 struct { 514 uint32_t :6; /*!< bit: 0.. 5 Reserved */ 515 uint32_t CC:2; /*!< bit: 6.. 7 Compare Channel x */ 516 uint32_t :24; /*!< bit: 8..31 Reserved */ 517 } vec; /*!< Structure used for vec access */ 518 uint32_t reg; /*!< Type used for register access */ 519 } TC_SYNCBUSY_Type; 520 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 521 522 #define TC_SYNCBUSY_OFFSET 0x10 /**< \brief (TC_SYNCBUSY offset) Synchronization Status */ 523 #define TC_SYNCBUSY_RESETVALUE _U(0x00000000) /**< \brief (TC_SYNCBUSY reset_value) Synchronization Status */ 524 525 #define TC_SYNCBUSY_SWRST_Pos 0 /**< \brief (TC_SYNCBUSY) swrst */ 526 #define TC_SYNCBUSY_SWRST (_U(0x1) << TC_SYNCBUSY_SWRST_Pos) 527 #define TC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (TC_SYNCBUSY) enable */ 528 #define TC_SYNCBUSY_ENABLE (_U(0x1) << TC_SYNCBUSY_ENABLE_Pos) 529 #define TC_SYNCBUSY_CTRLB_Pos 2 /**< \brief (TC_SYNCBUSY) CTRLB */ 530 #define TC_SYNCBUSY_CTRLB (_U(0x1) << TC_SYNCBUSY_CTRLB_Pos) 531 #define TC_SYNCBUSY_STATUS_Pos 3 /**< \brief (TC_SYNCBUSY) STATUS */ 532 #define TC_SYNCBUSY_STATUS (_U(0x1) << TC_SYNCBUSY_STATUS_Pos) 533 #define TC_SYNCBUSY_COUNT_Pos 4 /**< \brief (TC_SYNCBUSY) Counter */ 534 #define TC_SYNCBUSY_COUNT (_U(0x1) << TC_SYNCBUSY_COUNT_Pos) 535 #define TC_SYNCBUSY_PER_Pos 5 /**< \brief (TC_SYNCBUSY) Period */ 536 #define TC_SYNCBUSY_PER (_U(0x1) << TC_SYNCBUSY_PER_Pos) 537 #define TC_SYNCBUSY_CC0_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel 0 */ 538 #define TC_SYNCBUSY_CC0 (1 << TC_SYNCBUSY_CC0_Pos) 539 #define TC_SYNCBUSY_CC1_Pos 7 /**< \brief (TC_SYNCBUSY) Compare Channel 1 */ 540 #define TC_SYNCBUSY_CC1 (1 << TC_SYNCBUSY_CC1_Pos) 541 #define TC_SYNCBUSY_CC_Pos 6 /**< \brief (TC_SYNCBUSY) Compare Channel x */ 542 #define TC_SYNCBUSY_CC_Msk (_U(0x3) << TC_SYNCBUSY_CC_Pos) 543 #define TC_SYNCBUSY_CC(value) (TC_SYNCBUSY_CC_Msk & ((value) << TC_SYNCBUSY_CC_Pos)) 544 #define TC_SYNCBUSY_MASK _U(0x000000FF) /**< \brief (TC_SYNCBUSY) MASK Register */ 545 546 /* -------- TC_COUNT16_COUNT : (TC Offset: 0x14) (R/W 16) COUNT16 COUNT16 Count -------- */ 547 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 548 typedef union { 549 struct { 550 uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */ 551 } bit; /*!< Structure used for bit access */ 552 uint16_t reg; /*!< Type used for register access */ 553 } TC_COUNT16_COUNT_Type; 554 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 555 556 #define TC_COUNT16_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT16_COUNT offset) COUNT16 Count */ 557 #define TC_COUNT16_COUNT_RESETVALUE _U(0x0000) /**< \brief (TC_COUNT16_COUNT reset_value) COUNT16 Count */ 558 559 #define TC_COUNT16_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT16_COUNT) Counter Value */ 560 #define TC_COUNT16_COUNT_COUNT_Msk (_U(0xFFFF) << TC_COUNT16_COUNT_COUNT_Pos) 561 #define TC_COUNT16_COUNT_COUNT(value) (TC_COUNT16_COUNT_COUNT_Msk & ((value) << TC_COUNT16_COUNT_COUNT_Pos)) 562 #define TC_COUNT16_COUNT_MASK _U(0xFFFF) /**< \brief (TC_COUNT16_COUNT) MASK Register */ 563 564 /* -------- TC_COUNT32_COUNT : (TC Offset: 0x14) (R/W 32) COUNT32 COUNT32 Count -------- */ 565 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 566 typedef union { 567 struct { 568 uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */ 569 } bit; /*!< Structure used for bit access */ 570 uint32_t reg; /*!< Type used for register access */ 571 } TC_COUNT32_COUNT_Type; 572 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 573 574 #define TC_COUNT32_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT32_COUNT offset) COUNT32 Count */ 575 #define TC_COUNT32_COUNT_RESETVALUE _U(0x00000000) /**< \brief (TC_COUNT32_COUNT reset_value) COUNT32 Count */ 576 577 #define TC_COUNT32_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT32_COUNT) Counter Value */ 578 #define TC_COUNT32_COUNT_COUNT_Msk (_U(0xFFFFFFFF) << TC_COUNT32_COUNT_COUNT_Pos) 579 #define TC_COUNT32_COUNT_COUNT(value) (TC_COUNT32_COUNT_COUNT_Msk & ((value) << TC_COUNT32_COUNT_COUNT_Pos)) 580 #define TC_COUNT32_COUNT_MASK _U(0xFFFFFFFF) /**< \brief (TC_COUNT32_COUNT) MASK Register */ 581 582 /* -------- TC_COUNT8_COUNT : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Count -------- */ 583 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 584 typedef union { 585 struct { 586 uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */ 587 } bit; /*!< Structure used for bit access */ 588 uint8_t reg; /*!< Type used for register access */ 589 } TC_COUNT8_COUNT_Type; 590 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 591 592 #define TC_COUNT8_COUNT_OFFSET 0x14 /**< \brief (TC_COUNT8_COUNT offset) COUNT8 Count */ 593 #define TC_COUNT8_COUNT_RESETVALUE _U(0x00) /**< \brief (TC_COUNT8_COUNT reset_value) COUNT8 Count */ 594 595 #define TC_COUNT8_COUNT_COUNT_Pos 0 /**< \brief (TC_COUNT8_COUNT) Counter Value */ 596 #define TC_COUNT8_COUNT_COUNT_Msk (_U(0xFF) << TC_COUNT8_COUNT_COUNT_Pos) 597 #define TC_COUNT8_COUNT_COUNT(value) (TC_COUNT8_COUNT_COUNT_Msk & ((value) << TC_COUNT8_COUNT_COUNT_Pos)) 598 #define TC_COUNT8_COUNT_MASK _U(0xFF) /**< \brief (TC_COUNT8_COUNT) MASK Register */ 599 600 /* -------- TC_COUNT8_PER : (TC Offset: 0x1B) (R/W 8) COUNT8 COUNT8 Period -------- */ 601 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 602 typedef union { 603 struct { 604 uint8_t PER:8; /*!< bit: 0.. 7 Period Value */ 605 } bit; /*!< Structure used for bit access */ 606 uint8_t reg; /*!< Type used for register access */ 607 } TC_COUNT8_PER_Type; 608 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 609 610 #define TC_COUNT8_PER_OFFSET 0x1B /**< \brief (TC_COUNT8_PER offset) COUNT8 Period */ 611 #define TC_COUNT8_PER_RESETVALUE _U(0xFF) /**< \brief (TC_COUNT8_PER reset_value) COUNT8 Period */ 612 613 #define TC_COUNT8_PER_PER_Pos 0 /**< \brief (TC_COUNT8_PER) Period Value */ 614 #define TC_COUNT8_PER_PER_Msk (_U(0xFF) << TC_COUNT8_PER_PER_Pos) 615 #define TC_COUNT8_PER_PER(value) (TC_COUNT8_PER_PER_Msk & ((value) << TC_COUNT8_PER_PER_Pos)) 616 #define TC_COUNT8_PER_MASK _U(0xFF) /**< \brief (TC_COUNT8_PER) MASK Register */ 617 618 /* -------- TC_COUNT16_CC : (TC Offset: 0x1C) (R/W 16) COUNT16 COUNT16 Compare and Capture -------- */ 619 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 620 typedef union { 621 struct { 622 uint16_t CC:16; /*!< bit: 0..15 Counter/Compare Value */ 623 } bit; /*!< Structure used for bit access */ 624 uint16_t reg; /*!< Type used for register access */ 625 } TC_COUNT16_CC_Type; 626 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 627 628 #define TC_COUNT16_CC_OFFSET 0x1C /**< \brief (TC_COUNT16_CC offset) COUNT16 Compare and Capture */ 629 #define TC_COUNT16_CC_RESETVALUE _U(0x0000) /**< \brief (TC_COUNT16_CC reset_value) COUNT16 Compare and Capture */ 630 631 #define TC_COUNT16_CC_CC_Pos 0 /**< \brief (TC_COUNT16_CC) Counter/Compare Value */ 632 #define TC_COUNT16_CC_CC_Msk (_U(0xFFFF) << TC_COUNT16_CC_CC_Pos) 633 #define TC_COUNT16_CC_CC(value) (TC_COUNT16_CC_CC_Msk & ((value) << TC_COUNT16_CC_CC_Pos)) 634 #define TC_COUNT16_CC_MASK _U(0xFFFF) /**< \brief (TC_COUNT16_CC) MASK Register */ 635 636 /* -------- TC_COUNT32_CC : (TC Offset: 0x1C) (R/W 32) COUNT32 COUNT32 Compare and Capture -------- */ 637 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 638 typedef union { 639 struct { 640 uint32_t CC:32; /*!< bit: 0..31 Counter/Compare Value */ 641 } bit; /*!< Structure used for bit access */ 642 uint32_t reg; /*!< Type used for register access */ 643 } TC_COUNT32_CC_Type; 644 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 645 646 #define TC_COUNT32_CC_OFFSET 0x1C /**< \brief (TC_COUNT32_CC offset) COUNT32 Compare and Capture */ 647 #define TC_COUNT32_CC_RESETVALUE _U(0x00000000) /**< \brief (TC_COUNT32_CC reset_value) COUNT32 Compare and Capture */ 648 649 #define TC_COUNT32_CC_CC_Pos 0 /**< \brief (TC_COUNT32_CC) Counter/Compare Value */ 650 #define TC_COUNT32_CC_CC_Msk (_U(0xFFFFFFFF) << TC_COUNT32_CC_CC_Pos) 651 #define TC_COUNT32_CC_CC(value) (TC_COUNT32_CC_CC_Msk & ((value) << TC_COUNT32_CC_CC_Pos)) 652 #define TC_COUNT32_CC_MASK _U(0xFFFFFFFF) /**< \brief (TC_COUNT32_CC) MASK Register */ 653 654 /* -------- TC_COUNT8_CC : (TC Offset: 0x1C) (R/W 8) COUNT8 COUNT8 Compare and Capture -------- */ 655 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 656 typedef union { 657 struct { 658 uint8_t CC:8; /*!< bit: 0.. 7 Counter/Compare Value */ 659 } bit; /*!< Structure used for bit access */ 660 uint8_t reg; /*!< Type used for register access */ 661 } TC_COUNT8_CC_Type; 662 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 663 664 #define TC_COUNT8_CC_OFFSET 0x1C /**< \brief (TC_COUNT8_CC offset) COUNT8 Compare and Capture */ 665 #define TC_COUNT8_CC_RESETVALUE _U(0x00) /**< \brief (TC_COUNT8_CC reset_value) COUNT8 Compare and Capture */ 666 667 #define TC_COUNT8_CC_CC_Pos 0 /**< \brief (TC_COUNT8_CC) Counter/Compare Value */ 668 #define TC_COUNT8_CC_CC_Msk (_U(0xFF) << TC_COUNT8_CC_CC_Pos) 669 #define TC_COUNT8_CC_CC(value) (TC_COUNT8_CC_CC_Msk & ((value) << TC_COUNT8_CC_CC_Pos)) 670 #define TC_COUNT8_CC_MASK _U(0xFF) /**< \brief (TC_COUNT8_CC) MASK Register */ 671 672 /* -------- TC_COUNT8_PERBUF : (TC Offset: 0x2F) (R/W 8) COUNT8 COUNT8 Period Buffer -------- */ 673 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 674 typedef union { 675 struct { 676 uint8_t PERBUF:8; /*!< bit: 0.. 7 Period Buffer Value */ 677 } bit; /*!< Structure used for bit access */ 678 uint8_t reg; /*!< Type used for register access */ 679 } TC_COUNT8_PERBUF_Type; 680 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 681 682 #define TC_COUNT8_PERBUF_OFFSET 0x2F /**< \brief (TC_COUNT8_PERBUF offset) COUNT8 Period Buffer */ 683 #define TC_COUNT8_PERBUF_RESETVALUE _U(0xFF) /**< \brief (TC_COUNT8_PERBUF reset_value) COUNT8 Period Buffer */ 684 685 #define TC_COUNT8_PERBUF_PERBUF_Pos 0 /**< \brief (TC_COUNT8_PERBUF) Period Buffer Value */ 686 #define TC_COUNT8_PERBUF_PERBUF_Msk (_U(0xFF) << TC_COUNT8_PERBUF_PERBUF_Pos) 687 #define TC_COUNT8_PERBUF_PERBUF(value) (TC_COUNT8_PERBUF_PERBUF_Msk & ((value) << TC_COUNT8_PERBUF_PERBUF_Pos)) 688 #define TC_COUNT8_PERBUF_MASK _U(0xFF) /**< \brief (TC_COUNT8_PERBUF) MASK Register */ 689 690 /* -------- TC_COUNT16_CCBUF : (TC Offset: 0x30) (R/W 16) COUNT16 COUNT16 Compare and Capture Buffer -------- */ 691 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 692 typedef union { 693 struct { 694 uint16_t CCBUF:16; /*!< bit: 0..15 Counter/Compare Buffer Value */ 695 } bit; /*!< Structure used for bit access */ 696 uint16_t reg; /*!< Type used for register access */ 697 } TC_COUNT16_CCBUF_Type; 698 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 699 700 #define TC_COUNT16_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT16_CCBUF offset) COUNT16 Compare and Capture Buffer */ 701 #define TC_COUNT16_CCBUF_RESETVALUE _U(0x0000) /**< \brief (TC_COUNT16_CCBUF reset_value) COUNT16 Compare and Capture Buffer */ 702 703 #define TC_COUNT16_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT16_CCBUF) Counter/Compare Buffer Value */ 704 #define TC_COUNT16_CCBUF_CCBUF_Msk (_U(0xFFFF) << TC_COUNT16_CCBUF_CCBUF_Pos) 705 #define TC_COUNT16_CCBUF_CCBUF(value) (TC_COUNT16_CCBUF_CCBUF_Msk & ((value) << TC_COUNT16_CCBUF_CCBUF_Pos)) 706 #define TC_COUNT16_CCBUF_MASK _U(0xFFFF) /**< \brief (TC_COUNT16_CCBUF) MASK Register */ 707 708 /* -------- TC_COUNT32_CCBUF : (TC Offset: 0x30) (R/W 32) COUNT32 COUNT32 Compare and Capture Buffer -------- */ 709 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 710 typedef union { 711 struct { 712 uint32_t CCBUF:32; /*!< bit: 0..31 Counter/Compare Buffer Value */ 713 } bit; /*!< Structure used for bit access */ 714 uint32_t reg; /*!< Type used for register access */ 715 } TC_COUNT32_CCBUF_Type; 716 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 717 718 #define TC_COUNT32_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT32_CCBUF offset) COUNT32 Compare and Capture Buffer */ 719 #define TC_COUNT32_CCBUF_RESETVALUE _U(0x00000000) /**< \brief (TC_COUNT32_CCBUF reset_value) COUNT32 Compare and Capture Buffer */ 720 721 #define TC_COUNT32_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT32_CCBUF) Counter/Compare Buffer Value */ 722 #define TC_COUNT32_CCBUF_CCBUF_Msk (_U(0xFFFFFFFF) << TC_COUNT32_CCBUF_CCBUF_Pos) 723 #define TC_COUNT32_CCBUF_CCBUF(value) (TC_COUNT32_CCBUF_CCBUF_Msk & ((value) << TC_COUNT32_CCBUF_CCBUF_Pos)) 724 #define TC_COUNT32_CCBUF_MASK _U(0xFFFFFFFF) /**< \brief (TC_COUNT32_CCBUF) MASK Register */ 725 726 /* -------- TC_COUNT8_CCBUF : (TC Offset: 0x30) (R/W 8) COUNT8 COUNT8 Compare and Capture Buffer -------- */ 727 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 728 typedef union { 729 struct { 730 uint8_t CCBUF:8; /*!< bit: 0.. 7 Counter/Compare Buffer Value */ 731 } bit; /*!< Structure used for bit access */ 732 uint8_t reg; /*!< Type used for register access */ 733 } TC_COUNT8_CCBUF_Type; 734 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 735 736 #define TC_COUNT8_CCBUF_OFFSET 0x30 /**< \brief (TC_COUNT8_CCBUF offset) COUNT8 Compare and Capture Buffer */ 737 #define TC_COUNT8_CCBUF_RESETVALUE _U(0x00) /**< \brief (TC_COUNT8_CCBUF reset_value) COUNT8 Compare and Capture Buffer */ 738 739 #define TC_COUNT8_CCBUF_CCBUF_Pos 0 /**< \brief (TC_COUNT8_CCBUF) Counter/Compare Buffer Value */ 740 #define TC_COUNT8_CCBUF_CCBUF_Msk (_U(0xFF) << TC_COUNT8_CCBUF_CCBUF_Pos) 741 #define TC_COUNT8_CCBUF_CCBUF(value) (TC_COUNT8_CCBUF_CCBUF_Msk & ((value) << TC_COUNT8_CCBUF_CCBUF_Pos)) 742 #define TC_COUNT8_CCBUF_MASK _U(0xFF) /**< \brief (TC_COUNT8_CCBUF) MASK Register */ 743 744 /** \brief TC_COUNT8 hardware registers */ 745 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 746 typedef struct { /* 8-bit Counter Mode */ 747 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 748 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 749 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 750 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 751 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 752 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 753 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 754 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 755 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 756 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 757 RoReg8 Reserved1[0x1]; 758 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 759 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 760 __IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Count */ 761 RoReg8 Reserved2[0x6]; 762 __IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x1B (R/W 8) COUNT8 Period */ 763 __IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 8) COUNT8 Compare and Capture */ 764 RoReg8 Reserved3[0x11]; 765 __IO TC_COUNT8_PERBUF_Type PERBUF; /**< \brief Offset: 0x2F (R/W 8) COUNT8 Period Buffer */ 766 __IO TC_COUNT8_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 8) COUNT8 Compare and Capture Buffer */ 767 } TcCount8; 768 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 769 770 /** \brief TC_COUNT16 hardware registers */ 771 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 772 typedef struct { /* 16-bit Counter Mode */ 773 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 774 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 775 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 776 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 777 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 778 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 779 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 780 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 781 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 782 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 783 RoReg8 Reserved1[0x1]; 784 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 785 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 786 __IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 16) COUNT16 Count */ 787 RoReg8 Reserved2[0x6]; 788 __IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 16) COUNT16 Compare and Capture */ 789 RoReg8 Reserved3[0x10]; 790 __IO TC_COUNT16_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 16) COUNT16 Compare and Capture Buffer */ 791 } TcCount16; 792 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 793 794 /** \brief TC_COUNT32 hardware registers */ 795 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 796 typedef struct { /* 32-bit Counter Mode */ 797 __IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 798 __IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 799 __IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 800 __IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 801 __IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 802 __IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 803 __IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 804 __IO TC_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status */ 805 __IO TC_WAVE_Type WAVE; /**< \brief Offset: 0x0C (R/W 8) Waveform Generation Control */ 806 __IO TC_DRVCTRL_Type DRVCTRL; /**< \brief Offset: 0x0D (R/W 8) Control C */ 807 RoReg8 Reserved1[0x1]; 808 __IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 809 __I TC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 810 __IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x14 (R/W 32) COUNT32 Count */ 811 RoReg8 Reserved2[0x4]; 812 __IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x1C (R/W 32) COUNT32 Compare and Capture */ 813 RoReg8 Reserved3[0xC]; 814 __IO TC_COUNT32_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) COUNT32 Compare and Capture Buffer */ 815 } TcCount32; 816 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 817 818 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 819 typedef union { 820 TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */ 821 TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */ 822 TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */ 823 } Tc; 824 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 825 826 /*@}*/ 827 828 #endif /* _SAML21_TC_COMPONENT_ */ 829
