1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file tach.h 28 *MEC1501 Tachometer registers 29 */ 30 /** @defgroup MEC1501 Peripherals TACH 31 */ 32 33 #ifndef _TACH_H 34 #define _TACH_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ TACH =========== */ 43 /* =========================================================================*/ 44 45 #define MCHP_TACH_BASE_ADDR 0x40006000u 46 47 #define MCHP_TACH_MAX_INSTANCES 4u 48 #define MCHP_TACH_INST_SPACING 0x10u 49 #define MCHP_TACH_INST_SPACING_P2 4u 50 51 #define MCHP_TACH_ADDR(n) (MCHP_TACH_BASE_ADDR + \ 52 ((n) << MCHP_TACH_INST_SPACING_P2)) 53 54 /* 55 * TACH interrupts 56 */ 57 #define MCHP_TACH0_GIRQ 17u 58 #define MCHP_TACH1_GIRQ 17u 59 #define MCHP_TACH2_GIRQ 17u 60 #define MCHP_TACH3_GIRQ 17u 61 62 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 63 #define MCHP_TACH0_GIRQ_POS 1u 64 #define MCHP_TACH1_GIRQ_POS 2u 65 #define MCHP_TACH2_GIRQ_POS 3u 66 #define MCHP_TACH3_GIRQ_POS 4u 67 68 #define MCHP_TACH0_GIRQ_VAL (1u << MCHP_TACH0_GIRQ_POS) 69 #define MCHP_TACH1_GIRQ_VAL (1u << MCHP_TACH1_GIRQ_POS) 70 #define MCHP_TACH2_GIRQ_VAL (1u << MCHP_TACH2_GIRQ_POS) 71 #define MCHP_TACH3_GIRQ_VAL (1u << MCHP_TACH3_GIRQ_POS) 72 73 /* TACH GIRQ aggregated NVIC input */ 74 #define MCHP_TACH0_NVIC_AGGR 9u 75 #define MCHP_TACH1_NVIC_AGGR 9u 76 #define MCHP_TACH2_NVIC_AGGR 9u 77 #define MCHP_TACH3_NVIC_AGGR 9u 78 79 /* TACH direct NVIC inputs */ 80 #define MCHP_TACH0_NVIC_DIRECT 71u 81 #define MCHP_TACH1_NVIC_DIRECT 72u 82 #define MCHP_TACH2_NVIC_DIRECT 73u 83 #define MCHP_TACH3_NVIC_DIRECT 159u 84 85 /* 86 * TACH Control register 87 */ 88 #define MCHP_TACH_CONTROL_REG_OFS 0U 89 #define MCHP_TACH_CONTROL_MASK 0xffffdd03u 90 /* Enable exceed high or low limit detection */ 91 #define MCHP_TACH_CTRL_EXCEED_LIM_EN_POS 0 92 #define MCHP_TACH_CTRL_EXCEED_LIM_EN \ 93 (1u << MCHP_TACH_CTRL_EXCEED_LIM_EN_POS) 94 /* Enable TACH operation */ 95 #define MCHP_TACH_CTRL_EN_POS 1 96 #define MCHP_TACH_CTRL_EN (1u << MCHP_TACH_CTRL_EN_POS) 97 /* Enable input filter */ 98 #define MCHP_TACH_CTRL_FILTER_EN_POS 8 99 #define MCHP_TACH_CTRL_FILTER_EN (1u << MCHP_TACH_CTRL_FILTER_EN_POS) 100 /* Select read mode. Latch data on rising edge of selected trigger */ 101 #define MCHP_TACH_CTRL_READ_MODE_SEL_POS 10 102 #define MCHP_TACH_CTRL_READ_MODE_INPUT \ 103 (0u << MCHP_TACH_CTRL_READ_MODE_SEL_POS) 104 #define MCHP_TACH_CTRL_READ_MODE_100K_CLOCK \ 105 (1u << MCHP_TACH_CTRL_READ_MODE_SEL_POS) 106 /* Select TACH edges for counter increment */ 107 #define MCHP_TACH_CTRL_NUM_EDGES_POS 11 108 #define MCHP_TACH_CTRL_NUM_EDGES_MASK0 0x03u 109 #define MCHP_TACH_CTRL_NUM_EDGES_MASK (MCHP_TACH_CTRL_NUM_EDGES_MASK0 \ 110 << MCHP_TACH_CTRL_NUM_EDGES_POS) 111 #define MCHP_TACH_CTRL_EDGES_2 (0u << MCHP_TACH_CTRL_NUM_EDGES_POS) 112 #define MCHP_TACH_CTRL_EDGES_3 (1u << MCHP_TACH_CTRL_NUM_EDGES_POS) 113 #define MCHP_TACH_CTRL_EDGES_5 (2u << MCHP_TACH_CTRL_NUM_EDGES_POS) 114 #define MCHP_TACH_CTRL_EDGES_9 (3u << MCHP_TACH_CTRL_NUM_EDGES_POS) 115 /* Enable count ready interrupt */ 116 #define MCHP_TACH_CTRL_CNT_RDY_INT_EN_POS 14 117 #define MCHP_TACH_CTRL_CNT_RDY_INT_EN \ 118 (1u << MCHP_TACH_CTRL_CNT_RDY_INT_EN_POS) 119 /* Enable input toggle interrupt */ 120 #define MCHP_TACH_CTRL_TOGGLE_INT_EN_POS 15 121 #define MCHP_TACH_CTRL_TOGGLE_INT_EN \ 122 (1u << MCHP_TACH_CTRL_TOGGLE_INT_EN_POS) 123 /* Read-only latched TACH pulse counter */ 124 #define MCHP_TACH_CTRL_COUNTER_POS 16 125 #define MCHP_TACH_CTRL_COUNTER_MASK0 0xffffu 126 #define MCHP_TACH_CTRL_COUNTER_MASK \ 127 (MCHP_TACH_CTRL_COUNTER_MASK0 << MCHP_TACH_CTRL_COUNTER_POS) 128 129 /* 130 * TACH Status register 131 * bits[0, 2-3] are R/W1C 132 * bit[1] is Read-Only 133 */ 134 #define MCHP_TACH_STATUS_REG_OFS 4U 135 #define MCHP_TACH_STATUS_MASK 0x0fu 136 #define MCHP_TACH_STS_EXCEED_LIMIT_POS 0 137 #define MCHP_TACH_STS_EXCEED_LIMIT (1U << MCHP_TACH_STS_EXCEED_LIMIT_POS) 138 #define MCHP_TACH_STS_PIN_STATE_POS 1 139 #define MCHP_TACH_STS_PIN_STATE_HI (1U << MCHP_TACH_STS_PIN_STATE_POS) 140 #define MCHP_TACH_STS_TOGGLE_POS 2 141 #define MCHP_TACH_STS_TOGGLE (1U << MCHP_TACH_STS_TOGGLE_POS) 142 #define MCHP_TACH_STS_CNT_RDY_POS 3 143 #define MCHP_TACH_STS_CNT_RDY (1U << MCHP_TACH_STS_CNT_RDY_POS) 144 145 /* 146 * TACH High Limit Register 147 */ 148 #define MCHP_TACH_HI_LIMIT_REG_OFS 8U 149 #define MCHP_TACH_HI_LIMIT_MASK 0xffffu 150 151 /* 152 * TACH Low Limit Register 153 */ 154 #define MCHP_TACH_LO_LIMIT_REG_OFS 0x0cu 155 #define MCHP_TACH_LO_LIMIT_MASK 0xffffu 156 157 158 /** 159 * @brief Tachometer Registers (TACH) 160 */ 161 typedef struct tach_regs { 162 __IOM uint32_t CONTROL; /*!< (@ 0x0000) TACH Control b[31:0] */ 163 __IOM uint32_t STATUS; /*!< (@ 0x0004) TACH Status b[7:0] */ 164 __IOM uint32_t LIMIT_HI; /*!< (@ 0x0008) TACH High LImit b[15:0] */ 165 __IOM uint32_t LIMIT_LO; /*!< (@ 0x000c) TACH Low Limit b[15:0] */ 166 } TACH_Type; 167 168 #endif /* #ifndef _TACH_H */ 169 /* end tach.h */ 170 /** @} 171 */ 172
