1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file smb.h 28 *MEC1501 SMB register definitions 29 */ 30 /** @defgroup MEC1501 Peripherals SMB 31 */ 32 33 #ifndef _SMB_H 34 #define _SMB_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 #define MCHP_I2C_SMB_MAX_INSTANCES 4u 42 #define MCHP_I2C_SMB_INST_SPACING 0x400u 43 #define MCHP_I2C_SMB_INST_SPACING_P2 10u 44 45 #define MCHP_I2C_SMB0_BASE_ADDR 0x40004000u 46 #define MCHP_I2C_SMB1_BASE_ADDR 0x40004400u 47 #define MCHP_I2C_SMB2_BASE_ADDR 0x40004800u 48 #define MCHP_I2C_SMB3_BASE_ADDR 0x40004c00u 49 #define MCHP_I2C_SMB4_BASE_ADDR 0x40005000u 50 51 /* 0 <= n < MCHP_I2C_SMB_MAX_INSTANCES */ 52 #define MCHP_I2C_SMB_BASE_ADDR(n) \ 53 ((MCHP_I2C_SMB0_BASE_ADDR) +\ 54 ((uint32_t)(n) << (MCHP_I2C_SMB_INST_SPACING_P2))) 55 56 /* 57 * Offset 0x00 58 * Control and Status register 59 * Write to Control 60 * Read from Status 61 * Size 8-bit 62 */ 63 #define MCHP_I2C_SMB_CTRL_OFS 0x00u 64 #define MCHP_I2C_SMB_CTRL_MASK 0xcfu 65 #define MCHP_I2C_SMB_CTRL_ACK (1u << 0) 66 #define MCHP_I2C_SMB_CTRL_STO (1u << 1) 67 #define MCHP_I2C_SMB_CTRL_STA (1u << 2) 68 #define MCHP_I2C_SMB_CTRL_ENI (1u << 3) 69 /* bits [5:4] reserved */ 70 #define MCHP_I2C_SMB_CTRL_ESO (1u << 6) 71 #define MCHP_I2C_SMB_CTRL_PIN (1u << 7) 72 /* Status Read-only */ 73 #define MCHP_I2C_SMB_STS_OFS 0x00u 74 #define MCHP_I2C_SMB_STS_NBB (1u << 0) 75 #define MCHP_I2C_SMB_STS_LAB (1u << 1) 76 #define MCHP_I2C_SMB_STS_AAS (1u << 2) 77 #define MCHP_I2C_SMB_STS_LRB_AD0 (1u << 3) 78 #define MCHP_I2C_SMB_STS_BER (1u << 4) 79 #define MCHP_I2C_SMB_STS_EXT_STOP (1u << 5) 80 #define MCHP_I2C_SMB_STS_SAD (1u << 6) 81 #define MCHP_I2C_SMB_STS_PIN (1u << 7) 82 83 /* 84 * Offset 0x04 85 * Own Address b[7:0] = Slave address 1 86 * b[14:8] = Slave address 2 87 */ 88 #define MCHP_I2C_SMB_OWN_ADDR_OFS 0x04u 89 #define MCHP_I2C_SMB_OWN_ADDR2_OFS 0x05u 90 #define MCHP_I2C_SMB_OWN_ADDR_MASK 0x7f7fu 91 92 /* 93 * Offset 0x08 94 * Data register, 8-bit 95 * Data to be shifted out or shifted in. 96 */ 97 #define MCHP_I2C_SMB_DATA_OFS 0x08u 98 99 /* 100 * Offset 0x0c 101 * Master Command register 102 */ 103 #define MCHP_I2C_SMB_MSTR_CMD_OFS 0x0cu 104 #define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_OFS 0x0fu /* byte 3 */ 105 #define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_OFS 0x0eu /* byte 2 */ 106 #define MCHP_I2C_SMB_MSTR_CMD_OP_OFS 0x0du /* byte 1 */ 107 #define MCHP_I2C_SMB_MSTR_CMD_M_OFS 0x0cu /* byte 0 */ 108 #define MCHP_I2C_SMB_MSTR_CMD_MASK 0xffff3ff3u 109 /* 32-bit definitions */ 110 #define MCHP_I2C_SMB_MSTR_CMD_MRUN (1u << 0) 111 #define MCHP_I2C_SMB_MSTR_CMD_MPROCEED (1u << 1) 112 #define MCHP_I2C_SMB_MSTR_CMD_START0 (1u << 8) 113 #define MCHP_I2C_SMB_MSTR_CMD_STARTN (1u << 9) 114 #define MCHP_I2C_SMB_MSTR_CMD_STOP (1u << 10) 115 #define MCHP_I2C_SMB_MSTR_CMD_PEC_TERM (1u << 11) 116 #define MCHP_I2C_SMB_MSTR_CMD_READM (1u << 12) 117 #define MCHP_I2C_SMB_MSTR_CMD_READ_PEC (1u << 13) 118 #define MCHP_I2C_SMB_MSTR_CMD_RD_CNT_POS 24u 119 #define MCHP_I2C_SMB_MSTR_CMD_WR_CNT_POS 16u 120 /* byte 0 definitions */ 121 #define MCHP_I2C_SMB_MSTR_CMD_B0_MRUN (1u << 0) 122 #define MCHP_I2C_SMB_MSTR_CMD_B0_MPROCEED (1u << 1) 123 /* byte 1 definitions */ 124 #define MCHP_I2C_SMB_MSTR_CMD_B1_START0 (1u << (8-8)) 125 #define MCHP_I2C_SMB_MSTR_CMD_B1_STARTN (1u << (9-8)) 126 #define MCHP_I2C_SMB_MSTR_CMD_B1_STOP (1u << (10-8)) 127 #define MCHP_I2C_SMB_MSTR_CMD_B1_PEC_TERM (1u << (11-8)) 128 #define MCHP_I2C_SMB_MSTR_CMD_B1_READM (1u << (12-8)) 129 #define MCHP_I2C_SMB_MSTR_CMD_B1_READ_PEC (1u << (13-8)) 130 131 /* 132 * Offset 0x10 133 * Slave Command register 134 */ 135 #define MCHP_I2C_SMB_SLV_CMD_OFS 0x10u 136 #define MCHP_I2C_SMB_SLV_CMD_MASK 0x00ffff07u 137 #define MCHP_I2C_SMB_SLV_CMD_SRUN (1u << 0) 138 #define MCHP_I2C_SMB_SLV_CMD_SPROCEED (1u << 1) 139 #define MCHP_I2C_SMB_SLV_CMD_SEND_PEC (1u << 2) 140 #define MCHP_I2C_SMB_SLV_WR_CNT_POS 8u 141 #define MCHP_I2C_SMB_SLV_RD_CNT_POS 16u 142 143 /* 144 * Offset 0x14 145 * PEC CRC register, 8-bit read-write 146 */ 147 #define MCHP_I2C_SMB_PEC_CRC_OFS 0x14u 148 149 /* 150 * Offset 0x18 151 * Repeated Start Hold Time register, 8-bit read-write 152 */ 153 #define MCHP_I2C_SMB_RSHT_OFS 0x18u 154 155 /* 156 * Offset 0x20 157 * Complettion register, 32-bit 158 */ 159 #define MCHP_I2C_SMB_CMPL_OFS 0x20u 160 #define MCHP_I2C_SMB_CMPL_MASK 0xe33b7f7cu 161 #define MCHP_I2C_SMB_CMPL_RW1C_MASK 0xe1397f00u 162 #define MCHP_I2C_SMB_CMPL_DTEN (1u << 2) 163 #define MCHP_I2C_SMB_CMPL_MCEN (1u << 3) 164 #define MCHP_I2C_SMB_CMPL_SCEN (1u << 4) 165 #define MCHP_I2C_SMB_CMPL_BIDEN (1u << 5) 166 #define MCHP_I2C_SMB_CMPL_TIMERR (1u << 6) 167 #define MCHP_I2C_SMB_CMPL_DTO_RWC (1u << 8) 168 #define MCHP_I2C_SMB_CMPL_MCTO_RWC (1u << 9) 169 #define MCHP_I2C_SMB_CMPL_SCTO_RWC (1u << 10) 170 #define MCHP_I2C_SMB_CMPL_CHDL_RWC (1u << 11) 171 #define MCHP_I2C_SMB_CMPL_CHDH_RWC (1u << 12) 172 #define MCHP_I2C_SMB_CMPL_BER_RWC (1u << 13) 173 #define MCHP_I2C_SMB_CMPL_LAB_RWC (1u << 14) 174 #define MCHP_I2C_SMB_CMPL_SNAKR_RWC (1u << 16) 175 #define MCHP_I2C_SMB_CMPL_STR_RO (1u << 17) 176 #define MCHP_I2C_SMB_CMPL_SPROT_RWC (1u << 19) 177 #define MCHP_I2C_SMB_CMPL_RPT_RD_RWC (1u << 20) 178 #define MCHP_I2C_SMB_CMPL_RPT_WR_RWC (1u << 21) 179 #define MCHP_I2C_SMB_CMPL_MNAKX_RWC (1u << 24) 180 #define MCHP_I2C_SMB_CMPL_MTR_RO (1u << 25) 181 #define MCHP_I2C_SMB_CMPL_IDLE_RWC (1u << 29) 182 #define MCHP_I2C_SMB_CMPL_MDONE_RWC (1u << 30) 183 #define MCHP_I2C_SMB_CMPL_SDONE_RWC (1u << 31) 184 185 /* 186 * Offset 0x24 187 * Idle Scaling register 188 */ 189 #define MCHP_I2C_SMB_IDLSC_OFS 0x24u 190 #define MCHP_I2C_SMB_IDLSC_DLY_OFS 0x24u 191 #define MCHP_I2C_SMB_IDLSC_BUS_OFS 0x26u 192 #define MCHP_I2C_SMB_IDLSC_MASK 0x0fff0fffu 193 #define MCHP_I2C_SMB_IDLSC_BUS_MIN_POS 0u 194 #define MCHP_I2C_SMB_IDLSC_DLY_POS 16u 195 196 /* 197 * Offset 0x28 198 * Configure register 199 */ 200 #define MCHP_I2C_SMB_CFG_OFS 0x28u 201 #define MCHP_I2C_SMB_CFG_MASK 0xf00f5fbfu 202 #define MCHP_I2C_SMB_CFG_PORT_SEL_MASK 0x0fu 203 #define MCHP_I2C_SMB_CFG_TCEN (1u << 4) 204 #define MCHP_I2C_SMB_CFG_SLOW_CLK (1u << 5) 205 #define MCHP_I2C_SMB_CFG_PCEN (1u << 7) 206 #define MCHP_I2C_SMB_CFG_FEN (1u << 8) 207 #define MCHP_I2C_SMB_CFG_RESET (1u << 9) 208 #define MCHP_I2C_SMB_CFG_ENAB (1u << 10) 209 #define MCHP_I2C_SMB_CFG_DSA (1u << 11) 210 #define MCHP_I2C_SMB_CFG_FAIR (1u << 12) 211 #define MCHP_I2C_SMB_CFG_GC_EN (1u << 14) 212 #define MCHP_I2C_SMB_CFG_FLUSH_SXBUF_WO (1u << 16) 213 #define MCHP_I2C_SMB_CFG_FLUSH_SRBUF_WO (1u << 17) 214 #define MCHP_I2C_SMB_CFG_FLUSH_MXBUF_WO (1u << 18) 215 #define MCHP_I2C_SMB_CFG_FLUSH_MRBUF_WO (1u << 19) 216 #define MCHP_I2C_SMB_CFG_EN_AAS (1u << 28) 217 #define MCHP_I2C_SMB_CFG_ENIDI (1u << 29) 218 #define MCHP_I2C_SMB_CFG_ENMI (1u << 30) 219 #define MCHP_I2C_SMB_CFG_ENSI (1u << 31) 220 221 /* 222 * Offset 0x2c 223 * Bus Clock register 224 */ 225 #define MCHP_I2C_SMB_BUS_CLK_OFS 0x2cu 226 #define MCHP_I2C_SMB_BUS_CLK_MASK 0x0000ffffu 227 #define MCHP_I2C_SMB_BUS_CLK_LO_POS 0u 228 #define MCHP_I2C_SMB_BUS_CLK_HI_POS 8u 229 230 /* 231 * Offset 0x30 232 * Block ID register, 8-bit read-only 233 */ 234 #define MCHP_I2C_SMB_BLOCK_ID_OFS 0x30u 235 #define MCHP_I2C_SMB_BLOCK_ID_MASK 0xffu 236 237 /* 238 * Offset 0x34 239 * Block Revision register, 8-bit read-only 240 */ 241 #define MCHP_I2C_SMB_BLOCK_REV_OFS 0x34u 242 #define MCHP_I2C_SMB_BLOCK_REV_MASK 0xffu 243 244 /* 245 * Offset 0x38 246 * Bit-Bang Control register, 8-bit read-write 247 */ 248 #define MCHP_I2C_SMB_BB_OFS 0x38u 249 #define MCHP_I2C_SMB_BB_MASK 0x7fu 250 #define MCHP_I2C_SMB_BB_EN (1u << 0) 251 #define MCHP_I2C_SMB_BB_SCL_DIR_IN (0u << 1) 252 #define MCHP_I2C_SMB_BB_SCL_DIR_OUT (1u << 1) 253 #define MCHP_I2C_SMB_BB_SDA_DIR_IN (0u << 2) 254 #define MCHP_I2C_SMB_BB_SDA_DIR_OUT (1u << 2) 255 #define MCHP_I2C_SMB_BB_CL (1u << 3) 256 #define MCHP_I2C_SMB_BB_DAT (1u << 4) 257 #define MCHP_I2C_SMB_BB_IN_POS 5u 258 #define MCHP_I2C_SMB_BB_IN_MASK0 0x03u 259 #define MCHP_I2C_SMB_BB_IN_MASK (0x03u << 5) 260 #define MCHP_I2C_SMB_BB_CLKI_RO (1u << 5) 261 #define MCHP_I2C_SMB_BB_DATI_RO (1u << 6) 262 263 /* 264 * Offset 0x40 265 * Data Timing register 266 */ 267 #define MCHP_I2C_SMB_DATA_TM_OFS 0x40u 268 #define MCHP_I2C_SMB_DATA_TM_MASK 0xffffffffu 269 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_POS 0u 270 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK 0xffu 271 #define MCHP_I2C_SMB_DATA_TM_DATA_HOLD_MASK0 0xffu 272 #define MCHP_I2C_SMB_DATA_TM_RESTART_POS 8u 273 #define MCHP_I2C_SMB_DATA_TM_RESTART_MASK 0xff00u 274 #define MCHP_I2C_SMB_DATA_TM_RESTART_MASK0 0xffu 275 #define MCHP_I2C_SMB_DATA_TM_STOP_POS 16u 276 #define MCHP_I2C_SMB_DATA_TM_STOP_MASK 0xff0000u 277 #define MCHP_I2C_SMB_DATA_TM_STOP_MASK0 0xffu 278 #define MCHP_I2C_SMB_DATA_TM_FSTART_POS 24u 279 #define MCHP_I2C_SMB_DATA_TM_FSTART_MASK 0xff000000u 280 #define MCHP_I2C_SMB_DATA_TM_FSTART_MASK0 0xffu 281 282 /* 283 * Offset 0x44 284 * Time-out Scaling register 285 */ 286 #define MCHP_I2C_SMB_TMTSC_OFS 0x44u 287 #define MCHP_I2C_SMB_TMTSC_MASK 0xffffffffu 288 #define MCHP_I2C_SMB_TMTSC_CLK_HI_POS 0u 289 #define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK 0xffu 290 #define MCHP_I2C_SMB_TMTSC_CLK_HI_MASK0 0xffu 291 #define MCHP_I2C_SMB_TMTSC_SLV_POS 8u 292 #define MCHP_I2C_SMB_TMTSC_SLV_MASK 0xff00u 293 #define MCHP_I2C_SMB_TMTSC_SLV_MASK0 0xffu 294 #define MCHP_I2C_SMB_TMTSC_MSTR_POS 16u 295 #define MCHP_I2C_SMB_TMTSC_MSTR_MASK 0xff0000u 296 #define MCHP_I2C_SMB_TMTSC_MSTR_MASK0 0xffu 297 #define MCHP_I2C_SMB_TMTSC_BUS_POS 24u 298 #define MCHP_I2C_SMB_TMTSC_BUS_MASK 0xff000000u 299 #define MCHP_I2C_SMB_TMTSC_BUS_MASK0 0xffu 300 301 /* 302 * Offset 0x48 303 * Slave Transmit Buffer register 304 * 8-bit read-write 305 */ 306 #define MCHP_I2C_SMB_SLV_TX_BUF_OFS 0x48u 307 308 /* 309 * Offset 0x4c 310 * Slave Receive Buffer register 311 * 8-bit read-write 312 */ 313 #define MCHP_I2C_SMB_SLV_RX_BUF_OFS 0x4cu 314 315 /* 316 * Offset 0x50 317 * Master Transmit Buffer register 318 * 8-bit read-write 319 */ 320 #define MCHP_I2C_SMB_MTR_TX_BUF_OFS 0x50u 321 322 /* 323 * Offset 0x54 324 * Master Receive Buffer register 325 * 8-bit read-write 326 */ 327 #define MCHP_I2C_SMB_MTR_RX_BUF_OFS 0x54u 328 329 /* 330 * Offset 0x58 331 * I2C FSM read-only 332 */ 333 #define MCHP_I2C_SMB_I2C_FSM_OFS 0x58u 334 335 /* 336 * Offset 0x5c 337 * SMB Netork layer FSM read-only 338 */ 339 #define MCHP_I2C_SMB_FSM_OFS 0x5cu 340 341 /* 342 * Offset 0x60 343 * Wake Status register 344 */ 345 #define MCHP_I2C_SMB_WAKE_STS_OFS 0x60u 346 #define MCHP_I2C_SMB_WAKE_STS_START_RWC (1u << 0) 347 348 /* 349 * Offset 0x64 350 * Wake Enable register 351 */ 352 #define MCHP_I2C_SMB_WAKE_EN_OFS 0x64u 353 #define MCHP_I2C_SMB_WAKE_EN (1u << 0) 354 355 /* 356 * Offset 0x68 357 */ 358 #define MCHP_I2C_SMB_WAKE_SYNC_OFS 0x68u 359 #define MCHP_I2C_SMB_WAKE_FAST_RESYNC_EN (1u << 0) 360 361 /* 362 * I2C GIRQ and NVIC mapping 363 */ 364 #define MCHP_I2C_SMB_GIRQ 13u 365 #define MCHP_I2C_SMB_GIRQ_IDX (13u - 8u) 366 #define MCHP_I2C_SMB_NVIC_GIRQ 5u 367 #define MCHP_I2C_SMB0_NVIC_DIRECT 20u 368 #define MCHP_I2C_SMB1_NVIC_DIRECT 21u 369 #define MCHP_I2C_SMB2_NVIC_DIRECT 22u 370 #define MCHP_I2C_SMB3_NVIC_DIRECT 23u 371 #define MCHP_I2C_SMB4_NVIC_DIRECT 158u 372 373 #define MCHP_I2C_SMB_GIRQ_SRC_ADDR 0x4000e064u 374 #define MCHP_I2C_SMB_GIRQ_SET_EN_ADDR 0x4000e068u 375 #define MCHP_I2C_SMB_GIRQ_RESULT_ADDR 0x4000e06cu 376 #define MCHP_I2C_SMB_GIRQ_CLR_EN_ADDR 0x4000e070u 377 378 #define MCHP_I2C_SMB0_GIRQ_POS 0u 379 #define MCHP_I2C_SMB1_GIRQ_POS 1u 380 #define MCHP_I2C_SMB2_GIRQ_POS 2u 381 #define MCHP_I2C_SMB3_GIRQ_POS 3u 382 #define MCHP_I2C_SMB4_GIRQ_POS 4u 383 384 #define MCHP_I2C_SMB0_GIRQ_VAL (1u << 0) 385 #define MCHP_I2C_SMB1_GIRQ_VAL (1u << 1) 386 #define MCHP_I2C_SMB2_GIRQ_VAL (1u << 2) 387 #define MCHP_I2C_SMB3_GIRQ_VAL (1u << 3) 388 #define MCHP_I2C_SMB4_GIRQ_VAL (1u << 4) 389 390 /* 391 * Register access by controller base address 392 */ 393 394 /* I2C Control register, write-only */ 395 #define MCHP_I2C_SMB_CTRL_WO(ba) REG8(ba) 396 /* I2C Status register, read-only */ 397 #define MCHP_I2C_SMB_STS_RO(ba) REG8(ba) 398 399 #define MCHP_I2C_SMB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_CTRL_OFS) 400 401 /* Own Address register (slave addresses) */ 402 #define MCHP_I2C_SMB_OWN_ADDR(ba) \ 403 REG16_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS) 404 /* access bits[7:0] OWN_ADDRESS_1 */ 405 #define MCHP_I2C_SMB_OWN_ADDR1(ba) \ 406 REG8_OFS(ba, MCHP_I2C_SMB_OWN_ADDR_OFS) 407 /* access bits[15:8] OWN_ADDRESS_2 */ 408 #define MCHP_I2C_SMB_OWN_ADDR2(ba) \ 409 REG8_OFS(ba, (MCHP_I2C_SMB_OWN_ADDR_OFS + 1)) 410 411 /* I2C Data register */ 412 #define MCHP_I2C_SMB_DATA(ba) \ 413 REG8_OFS(ba, MCHP_I2C_SMB_DATA_OFS) 414 415 /* Network layer Master Command register */ 416 #define MCHP_I2C_SMB_MCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_MSTR_CMD_OFS) 417 #define MCHP_I2C_SMB_MCMD_MRP(ba) \ 418 REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 0u)) 419 #define MCHP_I2C_SMB_MCMD_CTRL(ba) \ 420 REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 1u)) 421 #define MCHP_I2C_SMB_MCMD_WCNT(ba) \ 422 REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 2u)) 423 #define MCHP_I2C_SMB_MCMD_RCNT(ba) \ 424 REG8_OFS(ba, (MCHP_I2C_SMB_MSTR_CMD_OFS + 3u)) 425 426 /* Network layer Slave Command register */ 427 #define MCHP_I2C_SMB_SCMD(ba) REG32_OFS(ba, MCHP_I2C_SMB_SLV_CMD_OFS) 428 #define MCHP_I2C_SMB_SCMD_SRP(ba) \ 429 REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 0u)) 430 #define MCHP_I2C_SMB_SCMD_WCNT(ba) \ 431 REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 1u)) 432 #define MCHP_I2C_SMB_SCMD_RCNT(ba) \ 433 REG8_OFS(ba, (MCHP_I2C_SMB_SLV_CMD_OFS + 2u)) 434 435 /* PEC register */ 436 #define MCHP_I2C_SMB_PEC(ba) REG8_OFS(ba, MCHP_I2C_SMB_PEC_CRC_OFS) 437 438 /* Repeated Start Hold Time register */ 439 #define MCHP_I2C_SMB_RSHT(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSHT_OFS) 440 441 /* Completion register */ 442 #define MCHP_I2C_SMB_CMPL(ba) REG32_OFS(ba, MCHP_I2C_SMB_CMPL_OFS) 443 /* access only bits[7:0] R/W timeout enables */ 444 #define MCHP_I2C_SMB_CMPL_B0(ba) REG8_OFS(ba, MCHP_I2C_SMB_CMPL_OFS) 445 446 /* Idle Scaling register */ 447 #define MCHP_I2C_SMB_IDLSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_IDLSC_OFS) 448 449 /* Configuration register */ 450 #define MCHP_I2C_SMB_CFG(ba) REG32_OFS(ba, MCHP_I2C_SMB_CFG_OFS) 451 /* access each byte */ 452 #define MCHP_I2C_SMB_CFG_B0(ba) \ 453 REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x00u)) 454 #define MCHP_I2C_SMB_CFG_B1(ba) \ 455 REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x01u)) 456 #define MCHP_I2C_SMB_CFG_B2(ba) \ 457 REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x02u)) 458 #define MCHP_I2C_SMB_CFG_B3(ba) \ 459 REG8_OFS(ba, (MCHP_I2C_SMB_CFG_OFS + 0x03u)) 460 461 /* Bus Clock register */ 462 #define MCHP_I2C_SMB_BUS_CLK(ba) REG32_OFS(ba, MCHP_I2C_SMB_BUS_CLK_OFS) 463 #define MCHP_I2C_SMB_BUS_CLK_LO_PERIOD(ba) \ 464 REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x00u)) 465 #define MCHP_I2C_SMB_BUS_CLK_HI_PERIOD(ba) \ 466 REG8_OFS(ba, (MCHP_I2C_SMB_BUS_CLK_OFS + 0x01u)) 467 468 /* Bit-Bang Control register */ 469 #define MCHP_I2C_SMB_BB_CTRL(ba) REG8_OFS(ba, MCHP_I2C_SMB_BB_OFS) 470 471 /* MCHP Reserved 0x3c register */ 472 #define MCHP_I2C_SMB_RSVD_3C(ba) REG8_OFS(ba, MCHP_I2C_SMB_RSVD_3C) 473 474 /* Data Timing register */ 475 #define MCHP_I2C_SMB_DATA_TM(ba) REG32_OFS(ba, MCHP_I2C_SMB_DATA_TM_OFS) 476 477 /* Timeout Scaling register */ 478 #define MCHP_I2C_SMB_TMTSC(ba) REG32_OFS(ba, MCHP_I2C_SMB_TMTSC_OFS) 479 480 /* Network layer Slave Transmit Buffer register */ 481 #define MCHP_I2C_SMB_SLV_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_TX_BUF_OFS) 482 483 /* Network layer Slave Receive Buffer register */ 484 #define MCHP_I2C_SMB_SLV_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_SLV_RX_BUF_OFS) 485 486 /* Network layer Master Transmit Buffer register */ 487 #define MCHP_I2C_SMB_MTR_TXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_TX_BUF_OFS) 488 489 /* Network layer Master Receive Buffer register */ 490 #define MCHP_I2C_SMB_MTR_RXB(ba) REG8_OFS(ba, MCHP_I2C_SMB_MTR_RX_BUF_OFS) 491 492 /* Wake Status register */ 493 #define MCHP_I2C_SMB_WAKE_STS(ba) REG8_OFS(ba, MCHP_I2C_SMB_WAKE_STS_OFS) 494 495 /* Wake Enable register */ 496 #define MCHP_I2C_SMB_WAKE_ENABLE(ba) REG8_OFS(ba, MCHP_SMB_WAKE_EN_OFS) 497 498 /* =========================================================================*/ 499 /* ================ SMB ================ */ 500 /* =========================================================================*/ 501 502 /** 503 * @brief SMBus Network Layer Block (SMB) 504 */ 505 typedef struct i2c_smb_regs 506 { /*!< (@ 0x40004000) SMB Structure */ 507 __IOM uint8_t CTRLSTS; /*!< (@ 0x00000000) SMB Status(RO), Control(WO) */ 508 uint8_t RSVD1[3]; 509 __IOM uint32_t OWN_ADDR; /*!< (@ 0x00000004) SMB Own address 1 */ 510 __IOM uint8_t I2CDATA; /*!< (@ 0x00000008) SMB I2C Data */ 511 uint8_t RSVD2[3]; 512 __IOM uint32_t MCMD; /*!< (@ 0x0000000c) SMB SMB master command */ 513 __IOM uint32_t SCMD; /*!< (@ 0x00000010) SMB SMB slave command */ 514 __IOM uint8_t PEC; /*!< (@ 0x00000014) SMB PEC value */ 515 uint8_t RSVD3[3]; 516 __IOM uint8_t RSHTM; /*!< (@ 0x00000018) SMB Repeated-Start hold time */ 517 uint8_t RSVD4[7]; 518 __IOM uint32_t COMPL; /*!< (@ 0x00000020) SMB Completion */ 519 __IOM uint32_t IDLSC; /*!< (@ 0x00000024) SMB Idle scaling */ 520 __IOM uint32_t CFG; /*!< (@ 0x00000028) SMB Configuration */ 521 __IOM uint32_t BUSCLK; /*!< (@ 0x0000002c) SMB Bus Clock */ 522 __IOM uint8_t BLKID; /*!< (@ 0x00000030) SMB Block ID */ 523 uint8_t RSVD5[3]; 524 __IOM uint8_t BLKREV; /*!< (@ 0x00000034) SMB Block revision */ 525 uint8_t RSVD6[3]; 526 __IOM uint8_t BBCTRL; /*!< (@ 0x00000038) SMB Bit-Bang control */ 527 uint8_t RSVD7[3]; 528 __IOM uint32_t CLKSYNC; /*!< (@ 0x0000003c) SMB Clock Sync */ 529 __IOM uint32_t DATATM; /*!< (@ 0x00000040) SMB Data timing */ 530 __IOM uint32_t TMOUTSC; /*!< (@ 0x00000044) SMB Time-out scaling */ 531 __IOM uint8_t SLV_TXB; /*!< (@ 0x00000048) SMB SMB slave TX buffer */ 532 uint8_t RSVD8[3]; 533 __IOM uint8_t SLV_RXB; /*!< (@ 0x0000004c) SMB SMB slave RX buffer */ 534 uint8_t RSVD9[3]; 535 __IOM uint8_t MTR_TXB; /*!< (@ 0x00000050) SMB SMB Master TX buffer */ 536 uint8_t RSVD10[3]; 537 __IOM uint8_t MTR_RXB; /*!< (@ 0x00000054) SMB SMB Master RX buffer */ 538 uint8_t RSVD11[3]; 539 __IOM uint32_t FSM; /*!< (@ 0x00000058) SMB FSM (RO) */ 540 __IOM uint32_t FSM_SMB; /*!< (@ 0x0000005c) SMB FSM SMB (RO) */ 541 __IOM uint8_t WAKE_STS; /*!< (@ 0x00000060) SMB Wake status */ 542 uint8_t RSVD12[3]; 543 __IOM uint8_t WAKE_EN; /*!< (@ 0x00000064) SMB Wake enable */ 544 } I2C_SMB_Type; 545 546 #endif // #ifndef _SMB_H 547 /* end smb.h */ 548 /** @} 549 */ 550
