1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_OSCCTRL_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_OSCCTRL_COMPONENT_FIXUP_H_ 9 10 /* -------- OSCCTRL_DPLLCTRLA : (OSCCTRL Offset: 0x30) (R/W 8) DPLL Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t :1; /*!< bit: 0 Reserved */ 15 uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */ 16 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 17 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 18 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 19 } bit; /*!< Structure used for bit access */ 20 uint8_t reg; /*!< Type used for register access */ 21 } OSCCTRL_DPLLCTRLA_Type; 22 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 23 24 /* -------- OSCCTRL_DPLLRATIO : (OSCCTRL Offset: 0x34) (R/W 32) DPLL Ratio Control -------- */ 25 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 26 typedef union { 27 struct { 28 uint32_t LDR:13; /*!< bit: 0..12 Loop Divider Ratio */ 29 uint32_t :3; /*!< bit: 13..15 Reserved */ 30 uint32_t LDRFRAC:5; /*!< bit: 16..20 Loop Divider Ratio Fractional Part */ 31 uint32_t :11; /*!< bit: 21..31 Reserved */ 32 } bit; /*!< Structure used for bit access */ 33 uint32_t reg; /*!< Type used for register access */ 34 } OSCCTRL_DPLLRATIO_Type; 35 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 36 37 /* -------- OSCCTRL_DPLLCTRLB : (OSCCTRL Offset: 0x38) (R/W 32) DPLL Control B -------- */ 38 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 39 typedef union { 40 struct { 41 uint32_t FILTER:4; /*!< bit: 0.. 3 Proportional Integral Filter Selection */ 42 uint32_t WUF:1; /*!< bit: 4 Wake Up Fast */ 43 uint32_t REFCLK:3; /*!< bit: 5.. 7 Reference Clock Selection */ 44 uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */ 45 uint32_t LBYPASS:1; /*!< bit: 11 Lock Bypass */ 46 uint32_t DCOFILTER:3; /*!< bit: 12..14 Sigma-Delta DCO Filter Selection */ 47 uint32_t DCOEN:1; /*!< bit: 15 DCO Filter Enable */ 48 uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */ 49 uint32_t :5; /*!< bit: 27..31 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint32_t reg; /*!< Type used for register access */ 52 } OSCCTRL_DPLLCTRLB_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 /* -------- OSCCTRL_DPLLSYNCBUSY : (OSCCTRL Offset: 0x3C) ( R/ 32) DPLL Synchronization Busy -------- */ 56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 57 typedef union { 58 struct { 59 uint32_t :1; /*!< bit: 0 Reserved */ 60 uint32_t ENABLE:1; /*!< bit: 1 DPLL Enable Synchronization Status */ 61 uint32_t DPLLRATIO:1; /*!< bit: 2 DPLL Loop Divider Ratio Synchronization Status */ 62 uint32_t :29; /*!< bit: 3..31 Reserved */ 63 } bit; /*!< Structure used for bit access */ 64 uint32_t reg; /*!< Type used for register access */ 65 } OSCCTRL_DPLLSYNCBUSY_Type; 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 67 68 /* -------- OSCCTRL_DPLLSTATUS : (OSCCTRL Offset: 0x40) ( R/ 32) DPLL Status -------- */ 69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 70 typedef union { 71 struct { 72 uint32_t LOCK:1; /*!< bit: 0 DPLL Lock Status */ 73 uint32_t CLKRDY:1; /*!< bit: 1 DPLL Clock Ready */ 74 uint32_t :30; /*!< bit: 2..31 Reserved */ 75 } bit; /*!< Structure used for bit access */ 76 uint32_t reg; /*!< Type used for register access */ 77 } OSCCTRL_DPLLSTATUS_Type; 78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* -------- OSCCTRL_EVCTRL : (OSCCTRL Offset: 0x00) (R/W 8) Event Control -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint8_t CFDEO0:1; /*!< bit: 0 Clock 0 Failure Detector Event Output Enable */ 85 uint8_t CFDEO1:1; /*!< bit: 1 Clock 1 Failure Detector Event Output Enable */ 86 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 struct { 89 uint8_t CFDEO:2; /*!< bit: 0.. 1 Clock x Failure Detector Event Output Enable */ 90 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 91 } vec; /*!< Structure used for vec access */ 92 uint8_t reg; /*!< Type used for register access */ 93 } OSCCTRL_EVCTRL_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 /* -------- OSCCTRL_INTENCLR : (OSCCTRL Offset: 0x04) (R/W 32) Interrupt Enable Clear -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */ 101 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */ 102 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */ 103 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */ 104 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 105 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 106 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 107 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 108 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 109 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 110 uint32_t :3; /*!< bit: 13..15 Reserved */ 111 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */ 112 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */ 113 uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */ 114 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 115 uint32_t :4; /*!< bit: 20..23 Reserved */ 116 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */ 117 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */ 118 uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */ 119 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 120 uint32_t :4; /*!< bit: 28..31 Reserved */ 121 } bit; /*!< Structure used for bit access */ 122 struct { 123 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */ 124 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */ 125 uint32_t :28; /*!< bit: 4..31 Reserved */ 126 } vec; /*!< Structure used for vec access */ 127 uint32_t reg; /*!< Type used for register access */ 128 } OSCCTRL_INTENCLR_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 /* -------- OSCCTRL_INTENSET : (OSCCTRL Offset: 0x08) (R/W 32) Interrupt Enable Set -------- */ 131 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 132 typedef union { 133 struct { 134 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready Interrupt Enable */ 135 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready Interrupt Enable */ 136 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector Interrupt Enable */ 137 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector Interrupt Enable */ 138 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 139 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready Interrupt Enable */ 140 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds Interrupt Enable */ 141 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine Interrupt Enable */ 142 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse Interrupt Enable */ 143 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped Interrupt Enable */ 144 uint32_t :3; /*!< bit: 13..15 Reserved */ 145 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise Interrupt Enable */ 146 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall Interrupt Enable */ 147 uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout Interrupt Enable */ 148 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete Interrupt Enable */ 149 uint32_t :4; /*!< bit: 20..23 Reserved */ 150 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise Interrupt Enable */ 151 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall Interrupt Enable */ 152 uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout Interrupt Enable */ 153 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete Interrupt Enable */ 154 uint32_t :4; /*!< bit: 28..31 Reserved */ 155 } bit; /*!< Structure used for bit access */ 156 struct { 157 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready Interrupt Enable */ 158 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector Interrupt Enable */ 159 uint32_t :28; /*!< bit: 4..31 Reserved */ 160 } vec; /*!< Structure used for vec access */ 161 uint32_t reg; /*!< Type used for register access */ 162 } OSCCTRL_INTENSET_Type; 163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 /* -------- OSCCTRL_INTFLAG : (OSCCTRL Offset: 0x0C) (R/W 32) Interrupt Flag Status and Clear -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { // __I to avoid read-modify-write on write-to-clear register 168 struct { 169 __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */ 170 __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */ 171 __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */ 172 __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */ 173 __I uint32_t :4; /*!< bit: 4.. 7 Reserved */ 174 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 175 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 176 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 177 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 178 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 179 __I uint32_t :3; /*!< bit: 13..15 Reserved */ 180 __I uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */ 181 __I uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */ 182 __I uint32_t DPLL0LTO:1; /*!< bit: 18 DPLL0 Lock Timeout */ 183 __I uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */ 184 __I uint32_t :4; /*!< bit: 20..23 Reserved */ 185 __I uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */ 186 __I uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */ 187 __I uint32_t DPLL1LTO:1; /*!< bit: 26 DPLL1 Lock Timeout */ 188 __I uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */ 189 __I uint32_t :4; /*!< bit: 28..31 Reserved */ 190 } bit; /*!< Structure used for bit access */ 191 struct { 192 __I uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */ 193 __I uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */ 194 __I uint32_t :28; /*!< bit: 4..31 Reserved */ 195 } vec; /*!< Structure used for vec access */ 196 uint32_t reg; /*!< Type used for register access */ 197 } OSCCTRL_INTFLAG_Type; 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 199 200 /* -------- OSCCTRL_STATUS : (OSCCTRL Offset: 0x10) ( R/ 32) Status -------- */ 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 202 typedef union { 203 struct { 204 uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */ 205 uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */ 206 uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */ 207 uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */ 208 uint32_t XOSCCKSW0:1; /*!< bit: 4 XOSC 0 Clock Switch */ 209 uint32_t XOSCCKSW1:1; /*!< bit: 5 XOSC 1 Clock Switch */ 210 uint32_t :2; /*!< bit: 6.. 7 Reserved */ 211 uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */ 212 uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */ 213 uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */ 214 uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */ 215 uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */ 216 uint32_t :3; /*!< bit: 13..15 Reserved */ 217 uint32_t DPLL0LCKR:1; /*!< bit: 16 DPLL0 Lock Rise */ 218 uint32_t DPLL0LCKF:1; /*!< bit: 17 DPLL0 Lock Fall */ 219 uint32_t DPLL0TO:1; /*!< bit: 18 DPLL0 Timeout */ 220 uint32_t DPLL0LDRTO:1; /*!< bit: 19 DPLL0 Loop Divider Ratio Update Complete */ 221 uint32_t :4; /*!< bit: 20..23 Reserved */ 222 uint32_t DPLL1LCKR:1; /*!< bit: 24 DPLL1 Lock Rise */ 223 uint32_t DPLL1LCKF:1; /*!< bit: 25 DPLL1 Lock Fall */ 224 uint32_t DPLL1TO:1; /*!< bit: 26 DPLL1 Timeout */ 225 uint32_t DPLL1LDRTO:1; /*!< bit: 27 DPLL1 Loop Divider Ratio Update Complete */ 226 uint32_t :4; /*!< bit: 28..31 Reserved */ 227 } bit; /*!< Structure used for bit access */ 228 struct { 229 uint32_t XOSCRDY:2; /*!< bit: 0.. 1 XOSC x Ready */ 230 uint32_t XOSCFAIL:2; /*!< bit: 2.. 3 XOSC x Clock Failure Detector */ 231 uint32_t XOSCCKSW:2; /*!< bit: 4.. 5 XOSC x Clock Switch */ 232 uint32_t :26; /*!< bit: 6..31 Reserved */ 233 } vec; /*!< Structure used for vec access */ 234 uint32_t reg; /*!< Type used for register access */ 235 } OSCCTRL_STATUS_Type; 236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 /* -------- OSCCTRL_XOSCCTRL : (OSCCTRL Offset: 0x14) (R/W 32) External Multipurpose Crystal Oscillator Control -------- */ 239 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 240 typedef union { 241 struct { 242 uint32_t :1; /*!< bit: 0 Reserved */ 243 uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 244 uint32_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 245 uint32_t :3; /*!< bit: 3.. 5 Reserved */ 246 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 247 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 248 uint32_t LOWBUFGAIN:1; /*!< bit: 8 Low Buffer Gain Enable */ 249 uint32_t IPTAT:2; /*!< bit: 9..10 Oscillator Current Reference */ 250 uint32_t IMULT:4; /*!< bit: 11..14 Oscillator Current Multiplier */ 251 uint32_t ENALC:1; /*!< bit: 15 Automatic Loop Control Enable */ 252 uint32_t CFDEN:1; /*!< bit: 16 Clock Failure Detector Enable */ 253 uint32_t SWBEN:1; /*!< bit: 17 Xosc Clock Switch Enable */ 254 uint32_t :2; /*!< bit: 18..19 Reserved */ 255 uint32_t STARTUP:4; /*!< bit: 20..23 Start-Up Time */ 256 uint32_t CFDPRESC:4; /*!< bit: 24..27 Clock Failure Detector Prescaler */ 257 uint32_t :4; /*!< bit: 28..31 Reserved */ 258 } bit; /*!< Structure used for bit access */ 259 uint32_t reg; /*!< Type used for register access */ 260 } OSCCTRL_XOSCCTRL_Type; 261 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 262 263 /* -------- OSCCTRL_DFLLCTRLA : (OSCCTRL Offset: 0x1C) (R/W 8) DFLL48M Control A -------- */ 264 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 265 typedef union { 266 struct { 267 uint8_t :1; /*!< bit: 0 Reserved */ 268 uint8_t ENABLE:1; /*!< bit: 1 DFLL Enable */ 269 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 270 uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 271 uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 272 } bit; /*!< Structure used for bit access */ 273 uint8_t reg; /*!< Type used for register access */ 274 } OSCCTRL_DFLLCTRLA_Type; 275 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 276 277 /* -------- OSCCTRL_DFLLCTRLB : (OSCCTRL Offset: 0x20) (R/W 8) DFLL48M Control B -------- */ 278 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 279 typedef union { 280 struct { 281 uint8_t MODE:1; /*!< bit: 0 Operating Mode Selection */ 282 uint8_t STABLE:1; /*!< bit: 1 Stable DFLL Frequency */ 283 uint8_t LLAW:1; /*!< bit: 2 Lose Lock After Wake */ 284 uint8_t USBCRM:1; /*!< bit: 3 USB Clock Recovery Mode */ 285 uint8_t CCDIS:1; /*!< bit: 4 Chill Cycle Disable */ 286 uint8_t QLDIS:1; /*!< bit: 5 Quick Lock Disable */ 287 uint8_t BPLCKC:1; /*!< bit: 6 Bypass Coarse Lock */ 288 uint8_t WAITLOCK:1; /*!< bit: 7 Wait Lock */ 289 } bit; /*!< Structure used for bit access */ 290 uint8_t reg; /*!< Type used for register access */ 291 } OSCCTRL_DFLLCTRLB_Type; 292 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 293 294 /* -------- OSCCTRL_DFLLVAL : (OSCCTRL Offset: 0x24) (R/W 32) DFLL48M Value -------- */ 295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 296 typedef union { 297 struct { 298 uint32_t FINE:8; /*!< bit: 0.. 7 Fine Value */ 299 uint32_t :2; /*!< bit: 8.. 9 Reserved */ 300 uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */ 301 uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */ 302 } bit; /*!< Structure used for bit access */ 303 uint32_t reg; /*!< Type used for register access */ 304 } OSCCTRL_DFLLVAL_Type; 305 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 306 307 /* -------- OSCCTRL_DFLLMUL : (OSCCTRL Offset: 0x28) (R/W 32) DFLL48M Multiplier -------- */ 308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 309 typedef union { 310 struct { 311 uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */ 312 uint32_t FSTEP:8; /*!< bit: 16..23 Fine Maximum Step */ 313 uint32_t :2; /*!< bit: 24..25 Reserved */ 314 uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */ 315 } bit; /*!< Structure used for bit access */ 316 uint32_t reg; /*!< Type used for register access */ 317 } OSCCTRL_DFLLMUL_Type; 318 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 319 320 /* -------- OSCCTRL_DFLLSYNC : (OSCCTRL Offset: 0x2C) (R/W 8) DFLL48M Synchronization -------- */ 321 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 322 typedef union { 323 struct { 324 uint8_t :1; /*!< bit: 0 Reserved */ 325 uint8_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ 326 uint8_t DFLLCTRLB:1; /*!< bit: 2 DFLLCTRLB Synchronization Busy */ 327 uint8_t DFLLVAL:1; /*!< bit: 3 DFLLVAL Synchronization Busy */ 328 uint8_t DFLLMUL:1; /*!< bit: 4 DFLLMUL Synchronization Busy */ 329 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 330 } bit; /*!< Structure used for bit access */ 331 uint8_t reg; /*!< Type used for register access */ 332 } OSCCTRL_DFLLSYNC_Type; 333 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 334 335 /** \brief OscctrlDpll hardware registers */ 336 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 337 typedef struct { 338 __IO OSCCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x00 (R/W 8) DPLL Control A */ 339 RoReg8 Reserved1[0x3]; 340 __IO OSCCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x04 (R/W 32) DPLL Ratio Control */ 341 __IO OSCCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x08 (R/W 32) DPLL Control B */ 342 __I OSCCTRL_DPLLSYNCBUSY_Type DPLLSYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) DPLL Synchronization Busy */ 343 __I OSCCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x10 (R/ 32) DPLL Status */ 344 } OscctrlDpll; 345 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 346 347 /** \brief OSCCTRL hardware registers */ 348 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 349 typedef struct { 350 __IO OSCCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x00 (R/W 8) Event Control */ 351 RoReg8 Reserved1[0x3]; 352 __IO OSCCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Clear */ 353 __IO OSCCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Set */ 354 __IO OSCCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0C (R/W 32) Interrupt Flag Status and Clear */ 355 __I OSCCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x10 (R/ 32) Status */ 356 __IO OSCCTRL_XOSCCTRL_Type XOSCCTRL[2]; /**< \brief Offset: 0x14 (R/W 32) External Multipurpose Crystal Oscillator Control */ 357 __IO OSCCTRL_DFLLCTRLA_Type DFLLCTRLA; /**< \brief Offset: 0x1C (R/W 8) DFLL48M Control A */ 358 RoReg8 Reserved2[0x3]; 359 __IO OSCCTRL_DFLLCTRLB_Type DFLLCTRLB; /**< \brief Offset: 0x20 (R/W 8) DFLL48M Control B */ 360 RoReg8 Reserved3[0x3]; 361 __IO OSCCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x24 (R/W 32) DFLL48M Value */ 362 __IO OSCCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Multiplier */ 363 __IO OSCCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x2C (R/W 8) DFLL48M Synchronization */ 364 RoReg8 Reserved4[0x3]; 365 OscctrlDpll Dpll[OSCCTRL_DPLL_NUMBER]; /**< \brief Offset: 0x30 OscctrlDpll groups [DPLLS_NUM] */ 366 } Oscctrl; 367 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 368 369 #endif /* _MICROCHIP_PIC32CXSG_OSCCTRL_COMPONENT_FIXUP_H_ */ 370
