1 /** 2 * \file 3 * 4 * \brief Component description for OPAMP 5 * 6 * Copyright (c) 2018 Microchip Technology Inc. 7 * 8 * \asf_license_start 9 * 10 * \page License 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); you may 15 * not use this file except in compliance with the License. 16 * You may obtain a copy of the Licence at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 22 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 * 26 * \asf_license_stop 27 * 28 */ 29 30 #ifndef _SAML21_OPAMP_COMPONENT_ 31 #define _SAML21_OPAMP_COMPONENT_ 32 33 /* ========================================================================== */ 34 /** SOFTWARE API DEFINITION FOR OPAMP */ 35 /* ========================================================================== */ 36 /** \addtogroup SAML21_OPAMP Operational Amplifier */ 37 /*@{*/ 38 39 #define OPAMP_U2237 40 #define REV_OPAMP 0x110 41 42 /* -------- OPAMP_CTRLA : (OPAMP Offset: 0x00) (R/W 8) Control A -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 47 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 48 uint8_t :5; /*!< bit: 2.. 6 Reserved */ 49 uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } OPAMP_CTRLA_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define OPAMP_CTRLA_OFFSET 0x00 /**< \brief (OPAMP_CTRLA offset) Control A */ 56 #define OPAMP_CTRLA_RESETVALUE _U_(0x00) /**< \brief (OPAMP_CTRLA reset_value) Control A */ 57 58 #define OPAMP_CTRLA_SWRST_Pos 0 /**< \brief (OPAMP_CTRLA) Software Reset */ 59 #define OPAMP_CTRLA_SWRST (_U_(0x1) << OPAMP_CTRLA_SWRST_Pos) 60 #define OPAMP_CTRLA_ENABLE_Pos 1 /**< \brief (OPAMP_CTRLA) Enable */ 61 #define OPAMP_CTRLA_ENABLE (_U_(0x1) << OPAMP_CTRLA_ENABLE_Pos) 62 #define OPAMP_CTRLA_LPMUX_Pos 7 /**< \brief (OPAMP_CTRLA) Low-Power Mux */ 63 #define OPAMP_CTRLA_LPMUX (_U_(0x1) << OPAMP_CTRLA_LPMUX_Pos) 64 #define OPAMP_CTRLA_MASK _U_(0x83) /**< \brief (OPAMP_CTRLA) MASK Register */ 65 66 /* -------- OPAMP_STATUS : (OPAMP Offset: 0x02) (R/ 8) Status -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t READY0:1; /*!< bit: 0 OPAMP 0 Ready */ 71 uint8_t READY1:1; /*!< bit: 1 OPAMP 1 Ready */ 72 uint8_t READY2:1; /*!< bit: 2 OPAMP 2 Ready */ 73 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 74 } bit; /*!< Structure used for bit access */ 75 struct { 76 uint8_t READY:3; /*!< bit: 0.. 2 OPAMP x Ready */ 77 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 78 } vec; /*!< Structure used for vec access */ 79 uint8_t reg; /*!< Type used for register access */ 80 } OPAMP_STATUS_Type; 81 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 82 83 #define OPAMP_STATUS_OFFSET 0x02 /**< \brief (OPAMP_STATUS offset) Status */ 84 #define OPAMP_STATUS_RESETVALUE _U_(0x00) /**< \brief (OPAMP_STATUS reset_value) Status */ 85 86 #define OPAMP_STATUS_READY0_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP 0 Ready */ 87 #define OPAMP_STATUS_READY0 (_U_(1) << OPAMP_STATUS_READY0_Pos) 88 #define OPAMP_STATUS_READY1_Pos 1 /**< \brief (OPAMP_STATUS) OPAMP 1 Ready */ 89 #define OPAMP_STATUS_READY1 (_U_(1) << OPAMP_STATUS_READY1_Pos) 90 #define OPAMP_STATUS_READY2_Pos 2 /**< \brief (OPAMP_STATUS) OPAMP 2 Ready */ 91 #define OPAMP_STATUS_READY2 (_U_(1) << OPAMP_STATUS_READY2_Pos) 92 #define OPAMP_STATUS_READY_Pos 0 /**< \brief (OPAMP_STATUS) OPAMP x Ready */ 93 #define OPAMP_STATUS_READY_Msk (_U_(0x7) << OPAMP_STATUS_READY_Pos) 94 #define OPAMP_STATUS_READY(value) (OPAMP_STATUS_READY_Msk & ((value) << OPAMP_STATUS_READY_Pos)) 95 #define OPAMP_STATUS_MASK _U_(0x07) /**< \brief (OPAMP_STATUS) MASK Register */ 96 97 /* -------- OPAMP_OPAMPCTRL : (OPAMP Offset: 0x04) (R/W 32) OPAMP n Control -------- */ 98 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 99 typedef union { 100 struct { 101 uint32_t :1; /*!< bit: 0 Reserved */ 102 uint32_t ENABLE:1; /*!< bit: 1 Operational Amplifier Enable */ 103 uint32_t ANAOUT:1; /*!< bit: 2 Analog Output */ 104 uint32_t BIAS:2; /*!< bit: 3.. 4 Bias Selection */ 105 uint32_t :1; /*!< bit: 5 Reserved */ 106 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 107 uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 108 uint32_t RES2OUT:1; /*!< bit: 8 Resistor ladder To Output */ 109 uint32_t RES2VCC:1; /*!< bit: 9 Resistor ladder To VCC */ 110 uint32_t RES1EN:1; /*!< bit: 10 Resistor 1 Enable */ 111 uint32_t RES1MUX:2; /*!< bit: 11..12 Resistor 1 Mux */ 112 uint32_t POTMUX:3; /*!< bit: 13..15 Potentiometer Selection */ 113 uint32_t MUXPOS:3; /*!< bit: 16..18 Positive Input Mux Selection */ 114 uint32_t :1; /*!< bit: 19 Reserved */ 115 uint32_t MUXNEG:3; /*!< bit: 20..22 Negative Input Mux Selection */ 116 uint32_t :9; /*!< bit: 23..31 Reserved */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } OPAMP_OPAMPCTRL_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 #define OPAMP_OPAMPCTRL_OFFSET 0x04 /**< \brief (OPAMP_OPAMPCTRL offset) OPAMP n Control */ 123 #define OPAMP_OPAMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (OPAMP_OPAMPCTRL reset_value) OPAMP n Control */ 124 125 #define OPAMP_OPAMPCTRL_ENABLE_Pos 1 /**< \brief (OPAMP_OPAMPCTRL) Operational Amplifier Enable */ 126 #define OPAMP_OPAMPCTRL_ENABLE (_U_(0x1) << OPAMP_OPAMPCTRL_ENABLE_Pos) 127 #define OPAMP_OPAMPCTRL_ANAOUT_Pos 2 /**< \brief (OPAMP_OPAMPCTRL) Analog Output */ 128 #define OPAMP_OPAMPCTRL_ANAOUT (_U_(0x1) << OPAMP_OPAMPCTRL_ANAOUT_Pos) 129 #define OPAMP_OPAMPCTRL_BIAS_Pos 3 /**< \brief (OPAMP_OPAMPCTRL) Bias Selection */ 130 #define OPAMP_OPAMPCTRL_BIAS_Msk (_U_(0x3) << OPAMP_OPAMPCTRL_BIAS_Pos) 131 #define OPAMP_OPAMPCTRL_BIAS(value) (OPAMP_OPAMPCTRL_BIAS_Msk & ((value) << OPAMP_OPAMPCTRL_BIAS_Pos)) 132 #define OPAMP_OPAMPCTRL_RUNSTDBY_Pos 6 /**< \brief (OPAMP_OPAMPCTRL) Run in Standby */ 133 #define OPAMP_OPAMPCTRL_RUNSTDBY (_U_(0x1) << OPAMP_OPAMPCTRL_RUNSTDBY_Pos) 134 #define OPAMP_OPAMPCTRL_ONDEMAND_Pos 7 /**< \brief (OPAMP_OPAMPCTRL) On Demand Control */ 135 #define OPAMP_OPAMPCTRL_ONDEMAND (_U_(0x1) << OPAMP_OPAMPCTRL_ONDEMAND_Pos) 136 #define OPAMP_OPAMPCTRL_RES2OUT_Pos 8 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To Output */ 137 #define OPAMP_OPAMPCTRL_RES2OUT (_U_(0x1) << OPAMP_OPAMPCTRL_RES2OUT_Pos) 138 #define OPAMP_OPAMPCTRL_RES2VCC_Pos 9 /**< \brief (OPAMP_OPAMPCTRL) Resistor ladder To VCC */ 139 #define OPAMP_OPAMPCTRL_RES2VCC (_U_(0x1) << OPAMP_OPAMPCTRL_RES2VCC_Pos) 140 #define OPAMP_OPAMPCTRL_RES1EN_Pos 10 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Enable */ 141 #define OPAMP_OPAMPCTRL_RES1EN (_U_(0x1) << OPAMP_OPAMPCTRL_RES1EN_Pos) 142 #define OPAMP_OPAMPCTRL_RES1MUX_Pos 11 /**< \brief (OPAMP_OPAMPCTRL) Resistor 1 Mux */ 143 #define OPAMP_OPAMPCTRL_RES1MUX_Msk (_U_(0x3) << OPAMP_OPAMPCTRL_RES1MUX_Pos) 144 #define OPAMP_OPAMPCTRL_RES1MUX(value) (OPAMP_OPAMPCTRL_RES1MUX_Msk & ((value) << OPAMP_OPAMPCTRL_RES1MUX_Pos)) 145 #define OPAMP_OPAMPCTRL_POTMUX_Pos 13 /**< \brief (OPAMP_OPAMPCTRL) Potentiometer Selection */ 146 #define OPAMP_OPAMPCTRL_POTMUX_Msk (_U_(0x7) << OPAMP_OPAMPCTRL_POTMUX_Pos) 147 #define OPAMP_OPAMPCTRL_POTMUX(value) (OPAMP_OPAMPCTRL_POTMUX_Msk & ((value) << OPAMP_OPAMPCTRL_POTMUX_Pos)) 148 #define OPAMP_OPAMPCTRL_MUXPOS_Pos 16 /**< \brief (OPAMP_OPAMPCTRL) Positive Input Mux Selection */ 149 #define OPAMP_OPAMPCTRL_MUXPOS_Msk (_U_(0x7) << OPAMP_OPAMPCTRL_MUXPOS_Pos) 150 #define OPAMP_OPAMPCTRL_MUXPOS(value) (OPAMP_OPAMPCTRL_MUXPOS_Msk & ((value) << OPAMP_OPAMPCTRL_MUXPOS_Pos)) 151 #define OPAMP_OPAMPCTRL_MUXNEG_Pos 20 /**< \brief (OPAMP_OPAMPCTRL) Negative Input Mux Selection */ 152 #define OPAMP_OPAMPCTRL_MUXNEG_Msk (_U_(0x7) << OPAMP_OPAMPCTRL_MUXNEG_Pos) 153 #define OPAMP_OPAMPCTRL_MUXNEG(value) (OPAMP_OPAMPCTRL_MUXNEG_Msk & ((value) << OPAMP_OPAMPCTRL_MUXNEG_Pos)) 154 #define OPAMP_OPAMPCTRL_MASK _U_(0x0077FFDE) /**< \brief (OPAMP_OPAMPCTRL) MASK Register */ 155 156 /** \brief OPAMP hardware registers */ 157 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 158 typedef struct { 159 __IO OPAMP_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 160 RoReg8 Reserved1[0x1]; 161 __I OPAMP_STATUS_Type STATUS; /**< \brief Offset: 0x02 (R/ 8) Status */ 162 RoReg8 Reserved2[0x1]; 163 __IO OPAMP_OPAMPCTRL_Type OPAMPCTRL[3]; /**< \brief Offset: 0x04 (R/W 32) OPAMP n Control */ 164 } Opamp; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 /*@}*/ 168 169 #endif /* _SAML21_OPAMP_COMPONENT_ */ 170
