1 /** 2 * \file 3 * 4 * \brief Component description for MTB 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_MTB_COMPONENT_ 30 #define _SAML21_MTB_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR MTB */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_MTB Cortex-M0+ Micro-Trace Buffer */ 36 /*@{*/ 37 38 #define MTB_U2002 39 #define REV_MTB 0x100 40 41 /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 46 uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ 47 uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ 48 } bit; /*!< Structure used for bit access */ 49 uint32_t reg; /*!< Type used for register access */ 50 } MTB_POSITION_Type; 51 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 52 53 #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ 54 55 #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ 56 #define MTB_POSITION_WRAP (_U(0x1) << MTB_POSITION_WRAP_Pos) 57 #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ 58 #define MTB_POSITION_POINTER_Msk (_U(0x1FFFFFFF) << MTB_POSITION_POINTER_Pos) 59 #define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos)) 60 #define MTB_POSITION_MASK _U(0xFFFFFFFC) /**< \brief (MTB_POSITION) MASK Register */ 61 62 /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ 63 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 64 typedef union { 65 struct { 66 uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ 67 uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ 68 uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ 69 uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ 70 uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ 71 uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ 72 uint32_t :21; /*!< bit: 10..30 Reserved */ 73 uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ 74 } bit; /*!< Structure used for bit access */ 75 uint32_t reg; /*!< Type used for register access */ 76 } MTB_MASTER_Type; 77 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 78 79 #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ 80 #define MTB_MASTER_RESETVALUE _U(0x00000000) /**< \brief (MTB_MASTER reset_value) MTB Master */ 81 82 #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ 83 #define MTB_MASTER_MASK_Msk (_U(0x1F) << MTB_MASTER_MASK_Pos) 84 #define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos)) 85 #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ 86 #define MTB_MASTER_TSTARTEN (_U(0x1) << MTB_MASTER_TSTARTEN_Pos) 87 #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ 88 #define MTB_MASTER_TSTOPEN (_U(0x1) << MTB_MASTER_TSTOPEN_Pos) 89 #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ 90 #define MTB_MASTER_SFRWPRIV (_U(0x1) << MTB_MASTER_SFRWPRIV_Pos) 91 #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ 92 #define MTB_MASTER_RAMPRIV (_U(0x1) << MTB_MASTER_RAMPRIV_Pos) 93 #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ 94 #define MTB_MASTER_HALTREQ (_U(0x1) << MTB_MASTER_HALTREQ_Pos) 95 #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ 96 #define MTB_MASTER_EN (_U(0x1) << MTB_MASTER_EN_Pos) 97 #define MTB_MASTER_MASK_ _U(0x800003FF) /**< \brief (MTB_MASTER) MASK Register */ 98 99 /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ 104 uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ 105 uint32_t :1; /*!< bit: 2 Reserved */ 106 uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ 107 } bit; /*!< Structure used for bit access */ 108 uint32_t reg; /*!< Type used for register access */ 109 } MTB_FLOW_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ 113 #define MTB_FLOW_RESETVALUE _U(0x00000000) /**< \brief (MTB_FLOW reset_value) MTB Flow */ 114 115 #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ 116 #define MTB_FLOW_AUTOSTOP (_U(0x1) << MTB_FLOW_AUTOSTOP_Pos) 117 #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ 118 #define MTB_FLOW_AUTOHALT (_U(0x1) << MTB_FLOW_AUTOHALT_Pos) 119 #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ 120 #define MTB_FLOW_WATERMARK_Msk (_U(0x1FFFFFFF) << MTB_FLOW_WATERMARK_Pos) 121 #define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos)) 122 #define MTB_FLOW_MASK _U(0xFFFFFFFB) /**< \brief (MTB_FLOW) MASK Register */ 123 124 /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ 125 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 126 typedef union { 127 uint32_t reg; /*!< Type used for register access */ 128 } MTB_BASE_Type; 129 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 130 131 #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ 132 #define MTB_BASE_MASK _U(0xFFFFFFFF) /**< \brief (MTB_BASE) MASK Register */ 133 134 /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 136 typedef union { 137 uint32_t reg; /*!< Type used for register access */ 138 } MTB_ITCTRL_Type; 139 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 140 141 #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ 142 #define MTB_ITCTRL_MASK _U(0xFFFFFFFF) /**< \brief (MTB_ITCTRL) MASK Register */ 143 144 /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ 145 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 146 typedef union { 147 uint32_t reg; /*!< Type used for register access */ 148 } MTB_CLAIMSET_Type; 149 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 150 151 #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ 152 #define MTB_CLAIMSET_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMSET) MASK Register */ 153 154 /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ 155 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 156 typedef union { 157 uint32_t reg; /*!< Type used for register access */ 158 } MTB_CLAIMCLR_Type; 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 160 161 #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ 162 #define MTB_CLAIMCLR_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CLAIMCLR) MASK Register */ 163 164 /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ 165 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 166 typedef union { 167 uint32_t reg; /*!< Type used for register access */ 168 } MTB_LOCKACCESS_Type; 169 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 170 171 #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ 172 #define MTB_LOCKACCESS_MASK _U(0xFFFFFFFF) /**< \brief (MTB_LOCKACCESS) MASK Register */ 173 174 /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef union { 177 uint32_t reg; /*!< Type used for register access */ 178 } MTB_LOCKSTATUS_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ 182 #define MTB_LOCKSTATUS_MASK _U(0xFFFFFFFF) /**< \brief (MTB_LOCKSTATUS) MASK Register */ 183 184 /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ 185 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 186 typedef union { 187 uint32_t reg; /*!< Type used for register access */ 188 } MTB_AUTHSTATUS_Type; 189 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 190 191 #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ 192 #define MTB_AUTHSTATUS_MASK _U(0xFFFFFFFF) /**< \brief (MTB_AUTHSTATUS) MASK Register */ 193 194 /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 196 typedef union { 197 uint32_t reg; /*!< Type used for register access */ 198 } MTB_DEVARCH_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ 202 #define MTB_DEVARCH_MASK _U(0xFFFFFFFF) /**< \brief (MTB_DEVARCH) MASK Register */ 203 204 /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 uint32_t reg; /*!< Type used for register access */ 208 } MTB_DEVID_Type; 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 210 211 #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ 212 #define MTB_DEVID_MASK _U(0xFFFFFFFF) /**< \brief (MTB_DEVID) MASK Register */ 213 214 /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ 215 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 216 typedef union { 217 uint32_t reg; /*!< Type used for register access */ 218 } MTB_DEVTYPE_Type; 219 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 220 221 #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ 222 #define MTB_DEVTYPE_MASK _U(0xFFFFFFFF) /**< \brief (MTB_DEVTYPE) MASK Register */ 223 224 /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) Peripheral Identification 4 -------- */ 225 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 226 typedef union { 227 uint32_t reg; /*!< Type used for register access */ 228 } MTB_PID4_Type; 229 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 230 231 #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) Peripheral Identification 4 */ 232 #define MTB_PID4_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID4) MASK Register */ 233 234 /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) Peripheral Identification 5 -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 uint32_t reg; /*!< Type used for register access */ 238 } MTB_PID5_Type; 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 240 241 #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) Peripheral Identification 5 */ 242 #define MTB_PID5_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID5) MASK Register */ 243 244 /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) Peripheral Identification 6 -------- */ 245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 246 typedef union { 247 uint32_t reg; /*!< Type used for register access */ 248 } MTB_PID6_Type; 249 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 250 251 #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) Peripheral Identification 6 */ 252 #define MTB_PID6_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID6) MASK Register */ 253 254 /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) Peripheral Identification 7 -------- */ 255 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 256 typedef union { 257 uint32_t reg; /*!< Type used for register access */ 258 } MTB_PID7_Type; 259 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 260 261 #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) Peripheral Identification 7 */ 262 #define MTB_PID7_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID7) MASK Register */ 263 264 /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) Peripheral Identification 0 -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 uint32_t reg; /*!< Type used for register access */ 268 } MTB_PID0_Type; 269 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 270 271 #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) Peripheral Identification 0 */ 272 #define MTB_PID0_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID0) MASK Register */ 273 274 /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) Peripheral Identification 1 -------- */ 275 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 276 typedef union { 277 uint32_t reg; /*!< Type used for register access */ 278 } MTB_PID1_Type; 279 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 280 281 #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) Peripheral Identification 1 */ 282 #define MTB_PID1_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID1) MASK Register */ 283 284 /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) Peripheral Identification 2 -------- */ 285 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 286 typedef union { 287 uint32_t reg; /*!< Type used for register access */ 288 } MTB_PID2_Type; 289 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 290 291 #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) Peripheral Identification 2 */ 292 #define MTB_PID2_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID2) MASK Register */ 293 294 /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) Peripheral Identification 3 -------- */ 295 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 296 typedef union { 297 uint32_t reg; /*!< Type used for register access */ 298 } MTB_PID3_Type; 299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 300 301 #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) Peripheral Identification 3 */ 302 #define MTB_PID3_MASK _U(0xFFFFFFFF) /**< \brief (MTB_PID3) MASK Register */ 303 304 /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) Component Identification 0 -------- */ 305 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 306 typedef union { 307 uint32_t reg; /*!< Type used for register access */ 308 } MTB_CID0_Type; 309 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 310 311 #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) Component Identification 0 */ 312 #define MTB_CID0_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CID0) MASK Register */ 313 314 /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) Component Identification 1 -------- */ 315 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 316 typedef union { 317 uint32_t reg; /*!< Type used for register access */ 318 } MTB_CID1_Type; 319 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 320 321 #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) Component Identification 1 */ 322 #define MTB_CID1_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CID1) MASK Register */ 323 324 /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) Component Identification 2 -------- */ 325 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 326 typedef union { 327 uint32_t reg; /*!< Type used for register access */ 328 } MTB_CID2_Type; 329 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 330 331 #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) Component Identification 2 */ 332 #define MTB_CID2_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CID2) MASK Register */ 333 334 /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) Component Identification 3 -------- */ 335 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 336 typedef union { 337 uint32_t reg; /*!< Type used for register access */ 338 } MTB_CID3_Type; 339 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 340 341 #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) Component Identification 3 */ 342 #define MTB_CID3_MASK _U(0xFFFFFFFF) /**< \brief (MTB_CID3) MASK Register */ 343 344 /** \brief MTB hardware registers */ 345 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 346 typedef struct { 347 __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ 348 __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ 349 __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ 350 __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ 351 RoReg8 Reserved1[0xEF0]; 352 __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ 353 RoReg8 Reserved2[0x9C]; 354 __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ 355 __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ 356 RoReg8 Reserved3[0x8]; 357 __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ 358 __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ 359 __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ 360 __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ 361 RoReg8 Reserved4[0x8]; 362 __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ 363 __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ 364 __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) Peripheral Identification 4 */ 365 __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) Peripheral Identification 5 */ 366 __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) Peripheral Identification 6 */ 367 __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) Peripheral Identification 7 */ 368 __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) Peripheral Identification 0 */ 369 __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) Peripheral Identification 1 */ 370 __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) Peripheral Identification 2 */ 371 __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) Peripheral Identification 3 */ 372 __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) Component Identification 0 */ 373 __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) Component Identification 1 */ 374 __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) Component Identification 2 */ 375 __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) Component Identification 3 */ 376 } Mtb; 377 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 378 379 /*@}*/ 380 381 #endif /* _SAML21_MTB_COMPONENT_ */ 382
