1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file hdmi_cec.h 28 *MEC1501 HDMI CEC registers 29 */ 30 /** @defgroup MEC1501 Peripherals HDMI-CEC 31 */ 32 33 #ifndef _HDMI_CEC_H 34 #define _HDMI_CEC_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ HDMI CEC =========== */ 43 /* =========================================================================*/ 44 45 #define MCHP_HDMI_CEC_BASE_ADDR 0x40006800u 46 47 /* 48 * HDMI_CEC interrupts 49 */ 50 #define MCHP_HDMI_CEC_GIRQ 17u 51 52 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 53 #define MCHP_HDMI_CEC_GIRQ_POS 5u 54 55 #define MCHP_HDMI_CEC_GIRQ_VAL (1u << MCHP_HDMI_CEC_GIRQ_POS) 56 57 /* HDMI_CEC GIRQ aggregated NVIC input */ 58 #define MCHP_HDMI_CEC_NVIC_AGGR 9u 59 60 /* HDMI_CEC direct NVIC inputs */ 61 #define MCHP_HDMI_CEC_NVIC_DIRECT 160u 62 63 /* HDMI_CEC Control register */ 64 #define MCHP_HDMI_CEC_CTRL_REG_OFS 0U 65 #define MCHP_HDMI_CEC_CTRL_MASK 0x0fu 66 #define MCHP_HDMI_CEC_CTRL_ACT_POS 0 67 #define MCHP_HDMI_CEC_CTRL_ACT (1u << 0) 68 #define MCHP_HDMI_CEC_CTRL_RST_POS 1 69 #define MCHP_HDMI_CEC_CTRL_RST (1u << 1) 70 #define MCHP_HDMI_CEC_CTRL_FILT_EN_POS 2 71 #define MCHP_HDMI_CEC_CTRL_FILT_EN (1u << 2) 72 #define MCHP_HDMI_CEC_CTRL_SFT5_POS 3 73 #define MCHP_HDMI_CEC_CTRL_SFT5_EN (1u << 3) 74 75 /* HDMI_CEC Claimed Logic Address register */ 76 #define MCHP_HDMI_CEC_CLA_REG_OFS 4U 77 #define MCHP_HDMI_CEC_CLA_MASK 0xffffu 78 79 /* HDMI_CEC Initiator Data Register */ 80 #define MCHP_HDMI_CEC_IDATA_REG_OFS 8U 81 #define MCHP_HDMI_CEC_IDATA_REG_MASK 0x01ffu 82 #define MCHP_HDMI_CEC_IDATA_POS 0 83 #define MCHP_HDMI_CEC_IDATA_MASK 0xffu 84 #define MCHP_HDMI_CEC_IDATA_EOM_POS 8 85 #define MCHP_HDMI_CEC_IDATA_EOM (1u << 8) 86 87 /* HDMI_CEC Follower Data Register */ 88 #define MCHP_HDMI_CEC_FDATA_REG_OFS 0x0cu 89 #define MCHP_HDMI_CEC_FDATA_REG_MASK 0x01ffu 90 #define MCHP_HDMI_CEC_FDATA_POS 0 91 #define MCHP_HDMI_CEC_FDATA_MASK 0xffu 92 #define MCHP_HDMI_CEC_FDATA_EOM_POS 8 93 #define MCHP_HDMI_CEC_FDATA_EOM (1u << 8) 94 95 /* HDMI_CEC Initiator/Follower Status Register */ 96 #define MCHP_HDMI_CEC_IFSTS_REG_OFS 0x10u 97 #define MCHP_HDMI_CEC_IFSTS_REG_MASK 0x007f007fu 98 #define MCHP_HDMI_CEC_ISTS_POS 0 99 #define MCHP_HDMI_CEC_ISTS_IDLE (1u << 0) 100 #define MCHP_HDMI_CEC_ISTS_LAB (1u << 1) 101 #define MCHP_HDMI_CEC_ISTS_UNDRN (1u << 2) 102 #define MCHP_HDMI_CEC_ISTS_ACKERR (1u << 3) 103 #define MCHP_HDMI_CEC_ISTS_CE (1u << 4) 104 #define MCHP_HDMI_CEC_ISTS_IFE (1u << 5) 105 #define MCHP_HDMI_CEC_ISTS_IFDONE (1u << 6) 106 /* follower status */ 107 #define MCHP_HDMI_CEC_FSTS_POS 16 108 #define MCHP_HDMI_CEC_FSTS_OVRN (1u << 16) 109 #define MCHP_HDMI_CEC_FSTS_BERR (1u << 17) 110 #define MCHP_HDMI_CEC_FSTS_BTO (1u << 18) 111 #define MCHP_HDMI_CEC_FSTS_FFNE (1u << 19) 112 #define MCHP_HDMI_CEC_FSTS_FFF (1u << 20) 113 #define MCHP_HDMI_CEC_FSTS_FDR (1u << 21) 114 #define MCHP_HDMI_CEC_FSTS_FFDONE (1u << 22) 115 116 /* HDMI_CEC Initiator Control Register */ 117 #define MCHP_HDMI_CEC_ICTRL_REG_OFS 0x18u 118 #define MCHP_HDMI_CEC_ICTRL_REG_MASK 0xe3u 119 #define MCHP_HDMI_CEC_ICTRL_FLUSH_POS 0 120 #define MCHP_HDMI_CEC_ICTRL_FLUSH (1u << 0) 121 #define MCHP_HDMI_CEC_ICTRL_START_POS 1 122 #define MCHP_HDMI_CEC_ICTRL_START (1u << 1) 123 #define MCHP_HDMI_CEC_ICTRL_IFE_EN_POS 5 124 #define MCHP_HDMI_CEC_ICTRL_IFE_EN (1u << 5) 125 #define MCHP_HDMI_CEC_ICTRL_IFDONE_EN_POS 6 126 #define MCHP_HDMI_CEC_ICTRL_IFDONE_EN (1u << 6) 127 128 /* HDMI_CEC Follower Control Register */ 129 #define MCHP_HDMI_CEC_FCTRL_REG_OFS 0x1cu 130 #define MCHP_HDMI_CEC_FCTRL_REG_MASK 0x71u 131 #define MCHP_HDMI_CEC_FCTRL_FLUSH_POS 0 132 #define MCHP_HDMI_CEC_FCTRL_FLUSH (1u << 0) 133 #define MCHP_HDMI_CEC_FCTRL_FFF_EN_POS 4 134 #define MCHP_HDMI_CEC_FCTRL_FFF_EN (1u << 4) 135 #define MCHP_HDMI_CEC_FCTRL_FDR_EN_POS 5 136 #define MCHP_HDMI_CEC_FCTRL_FDR_EN (1u << 5) 137 #define MCHP_HDMI_CEC_FCTRL_FFDONE_EN_POS 6 138 #define MCHP_HDMI_CEC_FCTRL_FFDONE_EN (1u << 6) 139 140 /** 141 * @brief HDMI CEC (HDMI_CEC) 142 */ 143 typedef struct hdmi_cec_regs { 144 __IOM uint32_t CEC_CONTROL; /*!< (@ 0x0000) HDMI_CEC Control */ 145 __IOM uint32_t CL_ADDR; /*!< (@ 0x0004) HDMI_CEC Claimed Logic Address */ 146 __IOM uint32_t IDATA; /*!< (@ 0x0008) HDMI_CEC Initiator Data */ 147 __IOM uint32_t FDATA; /*!< (@ 0x000c) HDMI_CEC Follower Data */ 148 __IOM uint32_t IFSTATUS; /*!< (@ 0x0010) HDMI_CEC Initiator/Follower Status */ 149 uint8_t RSVD1[4]; 150 __IOM uint32_t ICTRL; /*!< (@ 0x0018) HDMI_CEC Initiator Control */ 151 __IOM uint32_t FCTRL; /*!< (@ 0x001c) HDMI_CEC Follower Control */ 152 } HDMI_CEC_Type; 153 154 #endif /* #ifndef _HDMI_CEC_H */ 155 /* end hdmi_cec.h */ 156 /** @} 157 */ 158
