1 /** 2 * \file 3 * 4 * \brief Component description for EVSYS 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_EVSYS_COMPONENT_ 30 #define _SAML21_EVSYS_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR EVSYS */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_EVSYS Event System Interface */ 36 /*@{*/ 37 38 #define EVSYS_U2256 39 #define REV_EVSYS 0x101 40 41 /* -------- EVSYS_CTRLA : (EVSYS Offset: 0x00) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 47 } bit; /*!< Structure used for bit access */ 48 uint8_t reg; /*!< Type used for register access */ 49 } EVSYS_CTRLA_Type; 50 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 51 52 #define EVSYS_CTRLA_OFFSET 0x00 /**< \brief (EVSYS_CTRLA offset) Control */ 53 #define EVSYS_CTRLA_RESETVALUE _U(0x00) /**< \brief (EVSYS_CTRLA reset_value) Control */ 54 55 #define EVSYS_CTRLA_SWRST_Pos 0 /**< \brief (EVSYS_CTRLA) Software Reset */ 56 #define EVSYS_CTRLA_SWRST (_U(0x1) << EVSYS_CTRLA_SWRST_Pos) 57 #define EVSYS_CTRLA_MASK _U(0x01) /**< \brief (EVSYS_CTRLA) MASK Register */ 58 59 /* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */ 64 uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */ 65 uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */ 66 uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */ 67 uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */ 68 uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */ 69 uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */ 70 uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */ 71 uint32_t USRRDY8:1; /*!< bit: 8 Channel 8 User Ready */ 72 uint32_t USRRDY9:1; /*!< bit: 9 Channel 9 User Ready */ 73 uint32_t USRRDY10:1; /*!< bit: 10 Channel 10 User Ready */ 74 uint32_t USRRDY11:1; /*!< bit: 11 Channel 11 User Ready */ 75 uint32_t :4; /*!< bit: 12..15 Reserved */ 76 uint32_t CHBUSY0:1; /*!< bit: 16 Channel 0 Busy */ 77 uint32_t CHBUSY1:1; /*!< bit: 17 Channel 1 Busy */ 78 uint32_t CHBUSY2:1; /*!< bit: 18 Channel 2 Busy */ 79 uint32_t CHBUSY3:1; /*!< bit: 19 Channel 3 Busy */ 80 uint32_t CHBUSY4:1; /*!< bit: 20 Channel 4 Busy */ 81 uint32_t CHBUSY5:1; /*!< bit: 21 Channel 5 Busy */ 82 uint32_t CHBUSY6:1; /*!< bit: 22 Channel 6 Busy */ 83 uint32_t CHBUSY7:1; /*!< bit: 23 Channel 7 Busy */ 84 uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */ 85 uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */ 86 uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */ 87 uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */ 88 uint32_t :4; /*!< bit: 28..31 Reserved */ 89 } bit; /*!< Structure used for bit access */ 90 struct { 91 uint32_t USRRDY:12; /*!< bit: 0..11 Channel x User Ready */ 92 uint32_t :4; /*!< bit: 12..15 Reserved */ 93 uint32_t CHBUSY:12; /*!< bit: 16..27 Channel x Busy */ 94 uint32_t :4; /*!< bit: 28..31 Reserved */ 95 } vec; /*!< Structure used for vec access */ 96 uint32_t reg; /*!< Type used for register access */ 97 } EVSYS_CHSTATUS_Type; 98 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 99 100 #define EVSYS_CHSTATUS_OFFSET 0x0C /**< \brief (EVSYS_CHSTATUS offset) Channel Status */ 101 #define EVSYS_CHSTATUS_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_CHSTATUS reset_value) Channel Status */ 102 103 #define EVSYS_CHSTATUS_USRRDY0_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel 0 User Ready */ 104 #define EVSYS_CHSTATUS_USRRDY0 (1 << EVSYS_CHSTATUS_USRRDY0_Pos) 105 #define EVSYS_CHSTATUS_USRRDY1_Pos 1 /**< \brief (EVSYS_CHSTATUS) Channel 1 User Ready */ 106 #define EVSYS_CHSTATUS_USRRDY1 (1 << EVSYS_CHSTATUS_USRRDY1_Pos) 107 #define EVSYS_CHSTATUS_USRRDY2_Pos 2 /**< \brief (EVSYS_CHSTATUS) Channel 2 User Ready */ 108 #define EVSYS_CHSTATUS_USRRDY2 (1 << EVSYS_CHSTATUS_USRRDY2_Pos) 109 #define EVSYS_CHSTATUS_USRRDY3_Pos 3 /**< \brief (EVSYS_CHSTATUS) Channel 3 User Ready */ 110 #define EVSYS_CHSTATUS_USRRDY3 (1 << EVSYS_CHSTATUS_USRRDY3_Pos) 111 #define EVSYS_CHSTATUS_USRRDY4_Pos 4 /**< \brief (EVSYS_CHSTATUS) Channel 4 User Ready */ 112 #define EVSYS_CHSTATUS_USRRDY4 (1 << EVSYS_CHSTATUS_USRRDY4_Pos) 113 #define EVSYS_CHSTATUS_USRRDY5_Pos 5 /**< \brief (EVSYS_CHSTATUS) Channel 5 User Ready */ 114 #define EVSYS_CHSTATUS_USRRDY5 (1 << EVSYS_CHSTATUS_USRRDY5_Pos) 115 #define EVSYS_CHSTATUS_USRRDY6_Pos 6 /**< \brief (EVSYS_CHSTATUS) Channel 6 User Ready */ 116 #define EVSYS_CHSTATUS_USRRDY6 (1 << EVSYS_CHSTATUS_USRRDY6_Pos) 117 #define EVSYS_CHSTATUS_USRRDY7_Pos 7 /**< \brief (EVSYS_CHSTATUS) Channel 7 User Ready */ 118 #define EVSYS_CHSTATUS_USRRDY7 (1 << EVSYS_CHSTATUS_USRRDY7_Pos) 119 #define EVSYS_CHSTATUS_USRRDY8_Pos 8 /**< \brief (EVSYS_CHSTATUS) Channel 8 User Ready */ 120 #define EVSYS_CHSTATUS_USRRDY8 (1 << EVSYS_CHSTATUS_USRRDY8_Pos) 121 #define EVSYS_CHSTATUS_USRRDY9_Pos 9 /**< \brief (EVSYS_CHSTATUS) Channel 9 User Ready */ 122 #define EVSYS_CHSTATUS_USRRDY9 (1 << EVSYS_CHSTATUS_USRRDY9_Pos) 123 #define EVSYS_CHSTATUS_USRRDY10_Pos 10 /**< \brief (EVSYS_CHSTATUS) Channel 10 User Ready */ 124 #define EVSYS_CHSTATUS_USRRDY10 (1 << EVSYS_CHSTATUS_USRRDY10_Pos) 125 #define EVSYS_CHSTATUS_USRRDY11_Pos 11 /**< \brief (EVSYS_CHSTATUS) Channel 11 User Ready */ 126 #define EVSYS_CHSTATUS_USRRDY11 (1 << EVSYS_CHSTATUS_USRRDY11_Pos) 127 #define EVSYS_CHSTATUS_USRRDY_Pos 0 /**< \brief (EVSYS_CHSTATUS) Channel x User Ready */ 128 #define EVSYS_CHSTATUS_USRRDY_Msk (_U(0xFFF) << EVSYS_CHSTATUS_USRRDY_Pos) 129 #define EVSYS_CHSTATUS_USRRDY(value) (EVSYS_CHSTATUS_USRRDY_Msk & ((value) << EVSYS_CHSTATUS_USRRDY_Pos)) 130 #define EVSYS_CHSTATUS_CHBUSY0_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel 0 Busy */ 131 #define EVSYS_CHSTATUS_CHBUSY0 (1 << EVSYS_CHSTATUS_CHBUSY0_Pos) 132 #define EVSYS_CHSTATUS_CHBUSY1_Pos 17 /**< \brief (EVSYS_CHSTATUS) Channel 1 Busy */ 133 #define EVSYS_CHSTATUS_CHBUSY1 (1 << EVSYS_CHSTATUS_CHBUSY1_Pos) 134 #define EVSYS_CHSTATUS_CHBUSY2_Pos 18 /**< \brief (EVSYS_CHSTATUS) Channel 2 Busy */ 135 #define EVSYS_CHSTATUS_CHBUSY2 (1 << EVSYS_CHSTATUS_CHBUSY2_Pos) 136 #define EVSYS_CHSTATUS_CHBUSY3_Pos 19 /**< \brief (EVSYS_CHSTATUS) Channel 3 Busy */ 137 #define EVSYS_CHSTATUS_CHBUSY3 (1 << EVSYS_CHSTATUS_CHBUSY3_Pos) 138 #define EVSYS_CHSTATUS_CHBUSY4_Pos 20 /**< \brief (EVSYS_CHSTATUS) Channel 4 Busy */ 139 #define EVSYS_CHSTATUS_CHBUSY4 (1 << EVSYS_CHSTATUS_CHBUSY4_Pos) 140 #define EVSYS_CHSTATUS_CHBUSY5_Pos 21 /**< \brief (EVSYS_CHSTATUS) Channel 5 Busy */ 141 #define EVSYS_CHSTATUS_CHBUSY5 (1 << EVSYS_CHSTATUS_CHBUSY5_Pos) 142 #define EVSYS_CHSTATUS_CHBUSY6_Pos 22 /**< \brief (EVSYS_CHSTATUS) Channel 6 Busy */ 143 #define EVSYS_CHSTATUS_CHBUSY6 (1 << EVSYS_CHSTATUS_CHBUSY6_Pos) 144 #define EVSYS_CHSTATUS_CHBUSY7_Pos 23 /**< \brief (EVSYS_CHSTATUS) Channel 7 Busy */ 145 #define EVSYS_CHSTATUS_CHBUSY7 (1 << EVSYS_CHSTATUS_CHBUSY7_Pos) 146 #define EVSYS_CHSTATUS_CHBUSY8_Pos 24 /**< \brief (EVSYS_CHSTATUS) Channel 8 Busy */ 147 #define EVSYS_CHSTATUS_CHBUSY8 (1 << EVSYS_CHSTATUS_CHBUSY8_Pos) 148 #define EVSYS_CHSTATUS_CHBUSY9_Pos 25 /**< \brief (EVSYS_CHSTATUS) Channel 9 Busy */ 149 #define EVSYS_CHSTATUS_CHBUSY9 (1 << EVSYS_CHSTATUS_CHBUSY9_Pos) 150 #define EVSYS_CHSTATUS_CHBUSY10_Pos 26 /**< \brief (EVSYS_CHSTATUS) Channel 10 Busy */ 151 #define EVSYS_CHSTATUS_CHBUSY10 (1 << EVSYS_CHSTATUS_CHBUSY10_Pos) 152 #define EVSYS_CHSTATUS_CHBUSY11_Pos 27 /**< \brief (EVSYS_CHSTATUS) Channel 11 Busy */ 153 #define EVSYS_CHSTATUS_CHBUSY11 (1 << EVSYS_CHSTATUS_CHBUSY11_Pos) 154 #define EVSYS_CHSTATUS_CHBUSY_Pos 16 /**< \brief (EVSYS_CHSTATUS) Channel x Busy */ 155 #define EVSYS_CHSTATUS_CHBUSY_Msk (_U(0xFFF) << EVSYS_CHSTATUS_CHBUSY_Pos) 156 #define EVSYS_CHSTATUS_CHBUSY(value) (EVSYS_CHSTATUS_CHBUSY_Msk & ((value) << EVSYS_CHSTATUS_CHBUSY_Pos)) 157 #define EVSYS_CHSTATUS_MASK _U(0x0FFF0FFF) /**< \brief (EVSYS_CHSTATUS) MASK Register */ 158 159 /* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */ 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 161 typedef union { 162 struct { 163 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ 164 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ 165 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ 166 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ 167 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ 168 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ 169 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ 170 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ 171 uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ 172 uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ 173 uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ 174 uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ 175 uint32_t :4; /*!< bit: 12..15 Reserved */ 176 uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ 177 uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ 178 uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ 179 uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ 180 uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ 181 uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ 182 uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ 183 uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ 184 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ 185 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ 186 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ 187 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ 188 uint32_t :4; /*!< bit: 28..31 Reserved */ 189 } bit; /*!< Structure used for bit access */ 190 struct { 191 uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ 192 uint32_t :4; /*!< bit: 12..15 Reserved */ 193 uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ 194 uint32_t :4; /*!< bit: 28..31 Reserved */ 195 } vec; /*!< Structure used for vec access */ 196 uint32_t reg; /*!< Type used for register access */ 197 } EVSYS_INTENCLR_Type; 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 199 200 #define EVSYS_INTENCLR_OFFSET 0x10 /**< \brief (EVSYS_INTENCLR offset) Interrupt Enable Clear */ 201 #define EVSYS_INTENCLR_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_INTENCLR reset_value) Interrupt Enable Clear */ 202 203 #define EVSYS_INTENCLR_OVR0_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel 0 Overrun Interrupt Enable */ 204 #define EVSYS_INTENCLR_OVR0 (1 << EVSYS_INTENCLR_OVR0_Pos) 205 #define EVSYS_INTENCLR_OVR1_Pos 1 /**< \brief (EVSYS_INTENCLR) Channel 1 Overrun Interrupt Enable */ 206 #define EVSYS_INTENCLR_OVR1 (1 << EVSYS_INTENCLR_OVR1_Pos) 207 #define EVSYS_INTENCLR_OVR2_Pos 2 /**< \brief (EVSYS_INTENCLR) Channel 2 Overrun Interrupt Enable */ 208 #define EVSYS_INTENCLR_OVR2 (1 << EVSYS_INTENCLR_OVR2_Pos) 209 #define EVSYS_INTENCLR_OVR3_Pos 3 /**< \brief (EVSYS_INTENCLR) Channel 3 Overrun Interrupt Enable */ 210 #define EVSYS_INTENCLR_OVR3 (1 << EVSYS_INTENCLR_OVR3_Pos) 211 #define EVSYS_INTENCLR_OVR4_Pos 4 /**< \brief (EVSYS_INTENCLR) Channel 4 Overrun Interrupt Enable */ 212 #define EVSYS_INTENCLR_OVR4 (1 << EVSYS_INTENCLR_OVR4_Pos) 213 #define EVSYS_INTENCLR_OVR5_Pos 5 /**< \brief (EVSYS_INTENCLR) Channel 5 Overrun Interrupt Enable */ 214 #define EVSYS_INTENCLR_OVR5 (1 << EVSYS_INTENCLR_OVR5_Pos) 215 #define EVSYS_INTENCLR_OVR6_Pos 6 /**< \brief (EVSYS_INTENCLR) Channel 6 Overrun Interrupt Enable */ 216 #define EVSYS_INTENCLR_OVR6 (1 << EVSYS_INTENCLR_OVR6_Pos) 217 #define EVSYS_INTENCLR_OVR7_Pos 7 /**< \brief (EVSYS_INTENCLR) Channel 7 Overrun Interrupt Enable */ 218 #define EVSYS_INTENCLR_OVR7 (1 << EVSYS_INTENCLR_OVR7_Pos) 219 #define EVSYS_INTENCLR_OVR8_Pos 8 /**< \brief (EVSYS_INTENCLR) Channel 8 Overrun Interrupt Enable */ 220 #define EVSYS_INTENCLR_OVR8 (1 << EVSYS_INTENCLR_OVR8_Pos) 221 #define EVSYS_INTENCLR_OVR9_Pos 9 /**< \brief (EVSYS_INTENCLR) Channel 9 Overrun Interrupt Enable */ 222 #define EVSYS_INTENCLR_OVR9 (1 << EVSYS_INTENCLR_OVR9_Pos) 223 #define EVSYS_INTENCLR_OVR10_Pos 10 /**< \brief (EVSYS_INTENCLR) Channel 10 Overrun Interrupt Enable */ 224 #define EVSYS_INTENCLR_OVR10 (1 << EVSYS_INTENCLR_OVR10_Pos) 225 #define EVSYS_INTENCLR_OVR11_Pos 11 /**< \brief (EVSYS_INTENCLR) Channel 11 Overrun Interrupt Enable */ 226 #define EVSYS_INTENCLR_OVR11 (1 << EVSYS_INTENCLR_OVR11_Pos) 227 #define EVSYS_INTENCLR_OVR_Pos 0 /**< \brief (EVSYS_INTENCLR) Channel x Overrun Interrupt Enable */ 228 #define EVSYS_INTENCLR_OVR_Msk (_U(0xFFF) << EVSYS_INTENCLR_OVR_Pos) 229 #define EVSYS_INTENCLR_OVR(value) (EVSYS_INTENCLR_OVR_Msk & ((value) << EVSYS_INTENCLR_OVR_Pos)) 230 #define EVSYS_INTENCLR_EVD0_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel 0 Event Detection Interrupt Enable */ 231 #define EVSYS_INTENCLR_EVD0 (1 << EVSYS_INTENCLR_EVD0_Pos) 232 #define EVSYS_INTENCLR_EVD1_Pos 17 /**< \brief (EVSYS_INTENCLR) Channel 1 Event Detection Interrupt Enable */ 233 #define EVSYS_INTENCLR_EVD1 (1 << EVSYS_INTENCLR_EVD1_Pos) 234 #define EVSYS_INTENCLR_EVD2_Pos 18 /**< \brief (EVSYS_INTENCLR) Channel 2 Event Detection Interrupt Enable */ 235 #define EVSYS_INTENCLR_EVD2 (1 << EVSYS_INTENCLR_EVD2_Pos) 236 #define EVSYS_INTENCLR_EVD3_Pos 19 /**< \brief (EVSYS_INTENCLR) Channel 3 Event Detection Interrupt Enable */ 237 #define EVSYS_INTENCLR_EVD3 (1 << EVSYS_INTENCLR_EVD3_Pos) 238 #define EVSYS_INTENCLR_EVD4_Pos 20 /**< \brief (EVSYS_INTENCLR) Channel 4 Event Detection Interrupt Enable */ 239 #define EVSYS_INTENCLR_EVD4 (1 << EVSYS_INTENCLR_EVD4_Pos) 240 #define EVSYS_INTENCLR_EVD5_Pos 21 /**< \brief (EVSYS_INTENCLR) Channel 5 Event Detection Interrupt Enable */ 241 #define EVSYS_INTENCLR_EVD5 (1 << EVSYS_INTENCLR_EVD5_Pos) 242 #define EVSYS_INTENCLR_EVD6_Pos 22 /**< \brief (EVSYS_INTENCLR) Channel 6 Event Detection Interrupt Enable */ 243 #define EVSYS_INTENCLR_EVD6 (1 << EVSYS_INTENCLR_EVD6_Pos) 244 #define EVSYS_INTENCLR_EVD7_Pos 23 /**< \brief (EVSYS_INTENCLR) Channel 7 Event Detection Interrupt Enable */ 245 #define EVSYS_INTENCLR_EVD7 (1 << EVSYS_INTENCLR_EVD7_Pos) 246 #define EVSYS_INTENCLR_EVD8_Pos 24 /**< \brief (EVSYS_INTENCLR) Channel 8 Event Detection Interrupt Enable */ 247 #define EVSYS_INTENCLR_EVD8 (1 << EVSYS_INTENCLR_EVD8_Pos) 248 #define EVSYS_INTENCLR_EVD9_Pos 25 /**< \brief (EVSYS_INTENCLR) Channel 9 Event Detection Interrupt Enable */ 249 #define EVSYS_INTENCLR_EVD9 (1 << EVSYS_INTENCLR_EVD9_Pos) 250 #define EVSYS_INTENCLR_EVD10_Pos 26 /**< \brief (EVSYS_INTENCLR) Channel 10 Event Detection Interrupt Enable */ 251 #define EVSYS_INTENCLR_EVD10 (1 << EVSYS_INTENCLR_EVD10_Pos) 252 #define EVSYS_INTENCLR_EVD11_Pos 27 /**< \brief (EVSYS_INTENCLR) Channel 11 Event Detection Interrupt Enable */ 253 #define EVSYS_INTENCLR_EVD11 (1 << EVSYS_INTENCLR_EVD11_Pos) 254 #define EVSYS_INTENCLR_EVD_Pos 16 /**< \brief (EVSYS_INTENCLR) Channel x Event Detection Interrupt Enable */ 255 #define EVSYS_INTENCLR_EVD_Msk (_U(0xFFF) << EVSYS_INTENCLR_EVD_Pos) 256 #define EVSYS_INTENCLR_EVD(value) (EVSYS_INTENCLR_EVD_Msk & ((value) << EVSYS_INTENCLR_EVD_Pos)) 257 #define EVSYS_INTENCLR_MASK _U(0x0FFF0FFF) /**< \brief (EVSYS_INTENCLR) MASK Register */ 258 259 /* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */ 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 261 typedef union { 262 struct { 263 uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */ 264 uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */ 265 uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */ 266 uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */ 267 uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */ 268 uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */ 269 uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */ 270 uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */ 271 uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun Interrupt Enable */ 272 uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun Interrupt Enable */ 273 uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun Interrupt Enable */ 274 uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun Interrupt Enable */ 275 uint32_t :4; /*!< bit: 12..15 Reserved */ 276 uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection Interrupt Enable */ 277 uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection Interrupt Enable */ 278 uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection Interrupt Enable */ 279 uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection Interrupt Enable */ 280 uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection Interrupt Enable */ 281 uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection Interrupt Enable */ 282 uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection Interrupt Enable */ 283 uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection Interrupt Enable */ 284 uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */ 285 uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */ 286 uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */ 287 uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */ 288 uint32_t :4; /*!< bit: 28..31 Reserved */ 289 } bit; /*!< Structure used for bit access */ 290 struct { 291 uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun Interrupt Enable */ 292 uint32_t :4; /*!< bit: 12..15 Reserved */ 293 uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection Interrupt Enable */ 294 uint32_t :4; /*!< bit: 28..31 Reserved */ 295 } vec; /*!< Structure used for vec access */ 296 uint32_t reg; /*!< Type used for register access */ 297 } EVSYS_INTENSET_Type; 298 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 299 300 #define EVSYS_INTENSET_OFFSET 0x14 /**< \brief (EVSYS_INTENSET offset) Interrupt Enable Set */ 301 #define EVSYS_INTENSET_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_INTENSET reset_value) Interrupt Enable Set */ 302 303 #define EVSYS_INTENSET_OVR0_Pos 0 /**< \brief (EVSYS_INTENSET) Channel 0 Overrun Interrupt Enable */ 304 #define EVSYS_INTENSET_OVR0 (1 << EVSYS_INTENSET_OVR0_Pos) 305 #define EVSYS_INTENSET_OVR1_Pos 1 /**< \brief (EVSYS_INTENSET) Channel 1 Overrun Interrupt Enable */ 306 #define EVSYS_INTENSET_OVR1 (1 << EVSYS_INTENSET_OVR1_Pos) 307 #define EVSYS_INTENSET_OVR2_Pos 2 /**< \brief (EVSYS_INTENSET) Channel 2 Overrun Interrupt Enable */ 308 #define EVSYS_INTENSET_OVR2 (1 << EVSYS_INTENSET_OVR2_Pos) 309 #define EVSYS_INTENSET_OVR3_Pos 3 /**< \brief (EVSYS_INTENSET) Channel 3 Overrun Interrupt Enable */ 310 #define EVSYS_INTENSET_OVR3 (1 << EVSYS_INTENSET_OVR3_Pos) 311 #define EVSYS_INTENSET_OVR4_Pos 4 /**< \brief (EVSYS_INTENSET) Channel 4 Overrun Interrupt Enable */ 312 #define EVSYS_INTENSET_OVR4 (1 << EVSYS_INTENSET_OVR4_Pos) 313 #define EVSYS_INTENSET_OVR5_Pos 5 /**< \brief (EVSYS_INTENSET) Channel 5 Overrun Interrupt Enable */ 314 #define EVSYS_INTENSET_OVR5 (1 << EVSYS_INTENSET_OVR5_Pos) 315 #define EVSYS_INTENSET_OVR6_Pos 6 /**< \brief (EVSYS_INTENSET) Channel 6 Overrun Interrupt Enable */ 316 #define EVSYS_INTENSET_OVR6 (1 << EVSYS_INTENSET_OVR6_Pos) 317 #define EVSYS_INTENSET_OVR7_Pos 7 /**< \brief (EVSYS_INTENSET) Channel 7 Overrun Interrupt Enable */ 318 #define EVSYS_INTENSET_OVR7 (1 << EVSYS_INTENSET_OVR7_Pos) 319 #define EVSYS_INTENSET_OVR8_Pos 8 /**< \brief (EVSYS_INTENSET) Channel 8 Overrun Interrupt Enable */ 320 #define EVSYS_INTENSET_OVR8 (1 << EVSYS_INTENSET_OVR8_Pos) 321 #define EVSYS_INTENSET_OVR9_Pos 9 /**< \brief (EVSYS_INTENSET) Channel 9 Overrun Interrupt Enable */ 322 #define EVSYS_INTENSET_OVR9 (1 << EVSYS_INTENSET_OVR9_Pos) 323 #define EVSYS_INTENSET_OVR10_Pos 10 /**< \brief (EVSYS_INTENSET) Channel 10 Overrun Interrupt Enable */ 324 #define EVSYS_INTENSET_OVR10 (1 << EVSYS_INTENSET_OVR10_Pos) 325 #define EVSYS_INTENSET_OVR11_Pos 11 /**< \brief (EVSYS_INTENSET) Channel 11 Overrun Interrupt Enable */ 326 #define EVSYS_INTENSET_OVR11 (1 << EVSYS_INTENSET_OVR11_Pos) 327 #define EVSYS_INTENSET_OVR_Pos 0 /**< \brief (EVSYS_INTENSET) Channel x Overrun Interrupt Enable */ 328 #define EVSYS_INTENSET_OVR_Msk (_U(0xFFF) << EVSYS_INTENSET_OVR_Pos) 329 #define EVSYS_INTENSET_OVR(value) (EVSYS_INTENSET_OVR_Msk & ((value) << EVSYS_INTENSET_OVR_Pos)) 330 #define EVSYS_INTENSET_EVD0_Pos 16 /**< \brief (EVSYS_INTENSET) Channel 0 Event Detection Interrupt Enable */ 331 #define EVSYS_INTENSET_EVD0 (1 << EVSYS_INTENSET_EVD0_Pos) 332 #define EVSYS_INTENSET_EVD1_Pos 17 /**< \brief (EVSYS_INTENSET) Channel 1 Event Detection Interrupt Enable */ 333 #define EVSYS_INTENSET_EVD1 (1 << EVSYS_INTENSET_EVD1_Pos) 334 #define EVSYS_INTENSET_EVD2_Pos 18 /**< \brief (EVSYS_INTENSET) Channel 2 Event Detection Interrupt Enable */ 335 #define EVSYS_INTENSET_EVD2 (1 << EVSYS_INTENSET_EVD2_Pos) 336 #define EVSYS_INTENSET_EVD3_Pos 19 /**< \brief (EVSYS_INTENSET) Channel 3 Event Detection Interrupt Enable */ 337 #define EVSYS_INTENSET_EVD3 (1 << EVSYS_INTENSET_EVD3_Pos) 338 #define EVSYS_INTENSET_EVD4_Pos 20 /**< \brief (EVSYS_INTENSET) Channel 4 Event Detection Interrupt Enable */ 339 #define EVSYS_INTENSET_EVD4 (1 << EVSYS_INTENSET_EVD4_Pos) 340 #define EVSYS_INTENSET_EVD5_Pos 21 /**< \brief (EVSYS_INTENSET) Channel 5 Event Detection Interrupt Enable */ 341 #define EVSYS_INTENSET_EVD5 (1 << EVSYS_INTENSET_EVD5_Pos) 342 #define EVSYS_INTENSET_EVD6_Pos 22 /**< \brief (EVSYS_INTENSET) Channel 6 Event Detection Interrupt Enable */ 343 #define EVSYS_INTENSET_EVD6 (1 << EVSYS_INTENSET_EVD6_Pos) 344 #define EVSYS_INTENSET_EVD7_Pos 23 /**< \brief (EVSYS_INTENSET) Channel 7 Event Detection Interrupt Enable */ 345 #define EVSYS_INTENSET_EVD7 (1 << EVSYS_INTENSET_EVD7_Pos) 346 #define EVSYS_INTENSET_EVD8_Pos 24 /**< \brief (EVSYS_INTENSET) Channel 8 Event Detection Interrupt Enable */ 347 #define EVSYS_INTENSET_EVD8 (1 << EVSYS_INTENSET_EVD8_Pos) 348 #define EVSYS_INTENSET_EVD9_Pos 25 /**< \brief (EVSYS_INTENSET) Channel 9 Event Detection Interrupt Enable */ 349 #define EVSYS_INTENSET_EVD9 (1 << EVSYS_INTENSET_EVD9_Pos) 350 #define EVSYS_INTENSET_EVD10_Pos 26 /**< \brief (EVSYS_INTENSET) Channel 10 Event Detection Interrupt Enable */ 351 #define EVSYS_INTENSET_EVD10 (1 << EVSYS_INTENSET_EVD10_Pos) 352 #define EVSYS_INTENSET_EVD11_Pos 27 /**< \brief (EVSYS_INTENSET) Channel 11 Event Detection Interrupt Enable */ 353 #define EVSYS_INTENSET_EVD11 (1 << EVSYS_INTENSET_EVD11_Pos) 354 #define EVSYS_INTENSET_EVD_Pos 16 /**< \brief (EVSYS_INTENSET) Channel x Event Detection Interrupt Enable */ 355 #define EVSYS_INTENSET_EVD_Msk (_U(0xFFF) << EVSYS_INTENSET_EVD_Pos) 356 #define EVSYS_INTENSET_EVD(value) (EVSYS_INTENSET_EVD_Msk & ((value) << EVSYS_INTENSET_EVD_Pos)) 357 #define EVSYS_INTENSET_MASK _U(0x0FFF0FFF) /**< \brief (EVSYS_INTENSET) MASK Register */ 358 359 /* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */ 360 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 361 typedef union { // __I to avoid read-modify-write on write-to-clear register 362 struct { 363 __I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */ 364 __I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */ 365 __I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */ 366 __I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */ 367 __I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */ 368 __I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */ 369 __I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */ 370 __I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */ 371 __I uint32_t OVR8:1; /*!< bit: 8 Channel 8 Overrun */ 372 __I uint32_t OVR9:1; /*!< bit: 9 Channel 9 Overrun */ 373 __I uint32_t OVR10:1; /*!< bit: 10 Channel 10 Overrun */ 374 __I uint32_t OVR11:1; /*!< bit: 11 Channel 11 Overrun */ 375 __I uint32_t :4; /*!< bit: 12..15 Reserved */ 376 __I uint32_t EVD0:1; /*!< bit: 16 Channel 0 Event Detection */ 377 __I uint32_t EVD1:1; /*!< bit: 17 Channel 1 Event Detection */ 378 __I uint32_t EVD2:1; /*!< bit: 18 Channel 2 Event Detection */ 379 __I uint32_t EVD3:1; /*!< bit: 19 Channel 3 Event Detection */ 380 __I uint32_t EVD4:1; /*!< bit: 20 Channel 4 Event Detection */ 381 __I uint32_t EVD5:1; /*!< bit: 21 Channel 5 Event Detection */ 382 __I uint32_t EVD6:1; /*!< bit: 22 Channel 6 Event Detection */ 383 __I uint32_t EVD7:1; /*!< bit: 23 Channel 7 Event Detection */ 384 __I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */ 385 __I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */ 386 __I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */ 387 __I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */ 388 __I uint32_t :4; /*!< bit: 28..31 Reserved */ 389 } bit; /*!< Structure used for bit access */ 390 struct { 391 __I uint32_t OVR:12; /*!< bit: 0..11 Channel x Overrun */ 392 __I uint32_t :4; /*!< bit: 12..15 Reserved */ 393 __I uint32_t EVD:12; /*!< bit: 16..27 Channel x Event Detection */ 394 __I uint32_t :4; /*!< bit: 28..31 Reserved */ 395 } vec; /*!< Structure used for vec access */ 396 uint32_t reg; /*!< Type used for register access */ 397 } EVSYS_INTFLAG_Type; 398 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 399 400 #define EVSYS_INTFLAG_OFFSET 0x18 /**< \brief (EVSYS_INTFLAG offset) Interrupt Flag Status and Clear */ 401 #define EVSYS_INTFLAG_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_INTFLAG reset_value) Interrupt Flag Status and Clear */ 402 403 #define EVSYS_INTFLAG_OVR0_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel 0 Overrun */ 404 #define EVSYS_INTFLAG_OVR0 (1 << EVSYS_INTFLAG_OVR0_Pos) 405 #define EVSYS_INTFLAG_OVR1_Pos 1 /**< \brief (EVSYS_INTFLAG) Channel 1 Overrun */ 406 #define EVSYS_INTFLAG_OVR1 (1 << EVSYS_INTFLAG_OVR1_Pos) 407 #define EVSYS_INTFLAG_OVR2_Pos 2 /**< \brief (EVSYS_INTFLAG) Channel 2 Overrun */ 408 #define EVSYS_INTFLAG_OVR2 (1 << EVSYS_INTFLAG_OVR2_Pos) 409 #define EVSYS_INTFLAG_OVR3_Pos 3 /**< \brief (EVSYS_INTFLAG) Channel 3 Overrun */ 410 #define EVSYS_INTFLAG_OVR3 (1 << EVSYS_INTFLAG_OVR3_Pos) 411 #define EVSYS_INTFLAG_OVR4_Pos 4 /**< \brief (EVSYS_INTFLAG) Channel 4 Overrun */ 412 #define EVSYS_INTFLAG_OVR4 (1 << EVSYS_INTFLAG_OVR4_Pos) 413 #define EVSYS_INTFLAG_OVR5_Pos 5 /**< \brief (EVSYS_INTFLAG) Channel 5 Overrun */ 414 #define EVSYS_INTFLAG_OVR5 (1 << EVSYS_INTFLAG_OVR5_Pos) 415 #define EVSYS_INTFLAG_OVR6_Pos 6 /**< \brief (EVSYS_INTFLAG) Channel 6 Overrun */ 416 #define EVSYS_INTFLAG_OVR6 (1 << EVSYS_INTFLAG_OVR6_Pos) 417 #define EVSYS_INTFLAG_OVR7_Pos 7 /**< \brief (EVSYS_INTFLAG) Channel 7 Overrun */ 418 #define EVSYS_INTFLAG_OVR7 (1 << EVSYS_INTFLAG_OVR7_Pos) 419 #define EVSYS_INTFLAG_OVR8_Pos 8 /**< \brief (EVSYS_INTFLAG) Channel 8 Overrun */ 420 #define EVSYS_INTFLAG_OVR8 (1 << EVSYS_INTFLAG_OVR8_Pos) 421 #define EVSYS_INTFLAG_OVR9_Pos 9 /**< \brief (EVSYS_INTFLAG) Channel 9 Overrun */ 422 #define EVSYS_INTFLAG_OVR9 (1 << EVSYS_INTFLAG_OVR9_Pos) 423 #define EVSYS_INTFLAG_OVR10_Pos 10 /**< \brief (EVSYS_INTFLAG) Channel 10 Overrun */ 424 #define EVSYS_INTFLAG_OVR10 (1 << EVSYS_INTFLAG_OVR10_Pos) 425 #define EVSYS_INTFLAG_OVR11_Pos 11 /**< \brief (EVSYS_INTFLAG) Channel 11 Overrun */ 426 #define EVSYS_INTFLAG_OVR11 (1 << EVSYS_INTFLAG_OVR11_Pos) 427 #define EVSYS_INTFLAG_OVR_Pos 0 /**< \brief (EVSYS_INTFLAG) Channel x Overrun */ 428 #define EVSYS_INTFLAG_OVR_Msk (_U(0xFFF) << EVSYS_INTFLAG_OVR_Pos) 429 #define EVSYS_INTFLAG_OVR(value) (EVSYS_INTFLAG_OVR_Msk & ((value) << EVSYS_INTFLAG_OVR_Pos)) 430 #define EVSYS_INTFLAG_EVD0_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel 0 Event Detection */ 431 #define EVSYS_INTFLAG_EVD0 (1 << EVSYS_INTFLAG_EVD0_Pos) 432 #define EVSYS_INTFLAG_EVD1_Pos 17 /**< \brief (EVSYS_INTFLAG) Channel 1 Event Detection */ 433 #define EVSYS_INTFLAG_EVD1 (1 << EVSYS_INTFLAG_EVD1_Pos) 434 #define EVSYS_INTFLAG_EVD2_Pos 18 /**< \brief (EVSYS_INTFLAG) Channel 2 Event Detection */ 435 #define EVSYS_INTFLAG_EVD2 (1 << EVSYS_INTFLAG_EVD2_Pos) 436 #define EVSYS_INTFLAG_EVD3_Pos 19 /**< \brief (EVSYS_INTFLAG) Channel 3 Event Detection */ 437 #define EVSYS_INTFLAG_EVD3 (1 << EVSYS_INTFLAG_EVD3_Pos) 438 #define EVSYS_INTFLAG_EVD4_Pos 20 /**< \brief (EVSYS_INTFLAG) Channel 4 Event Detection */ 439 #define EVSYS_INTFLAG_EVD4 (1 << EVSYS_INTFLAG_EVD4_Pos) 440 #define EVSYS_INTFLAG_EVD5_Pos 21 /**< \brief (EVSYS_INTFLAG) Channel 5 Event Detection */ 441 #define EVSYS_INTFLAG_EVD5 (1 << EVSYS_INTFLAG_EVD5_Pos) 442 #define EVSYS_INTFLAG_EVD6_Pos 22 /**< \brief (EVSYS_INTFLAG) Channel 6 Event Detection */ 443 #define EVSYS_INTFLAG_EVD6 (1 << EVSYS_INTFLAG_EVD6_Pos) 444 #define EVSYS_INTFLAG_EVD7_Pos 23 /**< \brief (EVSYS_INTFLAG) Channel 7 Event Detection */ 445 #define EVSYS_INTFLAG_EVD7 (1 << EVSYS_INTFLAG_EVD7_Pos) 446 #define EVSYS_INTFLAG_EVD8_Pos 24 /**< \brief (EVSYS_INTFLAG) Channel 8 Event Detection */ 447 #define EVSYS_INTFLAG_EVD8 (1 << EVSYS_INTFLAG_EVD8_Pos) 448 #define EVSYS_INTFLAG_EVD9_Pos 25 /**< \brief (EVSYS_INTFLAG) Channel 9 Event Detection */ 449 #define EVSYS_INTFLAG_EVD9 (1 << EVSYS_INTFLAG_EVD9_Pos) 450 #define EVSYS_INTFLAG_EVD10_Pos 26 /**< \brief (EVSYS_INTFLAG) Channel 10 Event Detection */ 451 #define EVSYS_INTFLAG_EVD10 (1 << EVSYS_INTFLAG_EVD10_Pos) 452 #define EVSYS_INTFLAG_EVD11_Pos 27 /**< \brief (EVSYS_INTFLAG) Channel 11 Event Detection */ 453 #define EVSYS_INTFLAG_EVD11 (1 << EVSYS_INTFLAG_EVD11_Pos) 454 #define EVSYS_INTFLAG_EVD_Pos 16 /**< \brief (EVSYS_INTFLAG) Channel x Event Detection */ 455 #define EVSYS_INTFLAG_EVD_Msk (_U(0xFFF) << EVSYS_INTFLAG_EVD_Pos) 456 #define EVSYS_INTFLAG_EVD(value) (EVSYS_INTFLAG_EVD_Msk & ((value) << EVSYS_INTFLAG_EVD_Pos)) 457 #define EVSYS_INTFLAG_MASK _U(0x0FFF0FFF) /**< \brief (EVSYS_INTFLAG) MASK Register */ 458 459 /* -------- EVSYS_SWEVT : (EVSYS Offset: 0x1C) ( /W 32) Software Event -------- */ 460 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 461 typedef union { 462 struct { 463 uint32_t CHANNEL0:1; /*!< bit: 0 Channel 0 Software Selection */ 464 uint32_t CHANNEL1:1; /*!< bit: 1 Channel 1 Software Selection */ 465 uint32_t CHANNEL2:1; /*!< bit: 2 Channel 2 Software Selection */ 466 uint32_t CHANNEL3:1; /*!< bit: 3 Channel 3 Software Selection */ 467 uint32_t CHANNEL4:1; /*!< bit: 4 Channel 4 Software Selection */ 468 uint32_t CHANNEL5:1; /*!< bit: 5 Channel 5 Software Selection */ 469 uint32_t CHANNEL6:1; /*!< bit: 6 Channel 6 Software Selection */ 470 uint32_t CHANNEL7:1; /*!< bit: 7 Channel 7 Software Selection */ 471 uint32_t CHANNEL8:1; /*!< bit: 8 Channel 8 Software Selection */ 472 uint32_t CHANNEL9:1; /*!< bit: 9 Channel 9 Software Selection */ 473 uint32_t CHANNEL10:1; /*!< bit: 10 Channel 10 Software Selection */ 474 uint32_t CHANNEL11:1; /*!< bit: 11 Channel 11 Software Selection */ 475 uint32_t :20; /*!< bit: 12..31 Reserved */ 476 } bit; /*!< Structure used for bit access */ 477 struct { 478 uint32_t CHANNEL:12; /*!< bit: 0..11 Channel x Software Selection */ 479 uint32_t :20; /*!< bit: 12..31 Reserved */ 480 } vec; /*!< Structure used for vec access */ 481 uint32_t reg; /*!< Type used for register access */ 482 } EVSYS_SWEVT_Type; 483 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 484 485 #define EVSYS_SWEVT_OFFSET 0x1C /**< \brief (EVSYS_SWEVT offset) Software Event */ 486 #define EVSYS_SWEVT_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_SWEVT reset_value) Software Event */ 487 488 #define EVSYS_SWEVT_CHANNEL0_Pos 0 /**< \brief (EVSYS_SWEVT) Channel 0 Software Selection */ 489 #define EVSYS_SWEVT_CHANNEL0 (1 << EVSYS_SWEVT_CHANNEL0_Pos) 490 #define EVSYS_SWEVT_CHANNEL1_Pos 1 /**< \brief (EVSYS_SWEVT) Channel 1 Software Selection */ 491 #define EVSYS_SWEVT_CHANNEL1 (1 << EVSYS_SWEVT_CHANNEL1_Pos) 492 #define EVSYS_SWEVT_CHANNEL2_Pos 2 /**< \brief (EVSYS_SWEVT) Channel 2 Software Selection */ 493 #define EVSYS_SWEVT_CHANNEL2 (1 << EVSYS_SWEVT_CHANNEL2_Pos) 494 #define EVSYS_SWEVT_CHANNEL3_Pos 3 /**< \brief (EVSYS_SWEVT) Channel 3 Software Selection */ 495 #define EVSYS_SWEVT_CHANNEL3 (1 << EVSYS_SWEVT_CHANNEL3_Pos) 496 #define EVSYS_SWEVT_CHANNEL4_Pos 4 /**< \brief (EVSYS_SWEVT) Channel 4 Software Selection */ 497 #define EVSYS_SWEVT_CHANNEL4 (1 << EVSYS_SWEVT_CHANNEL4_Pos) 498 #define EVSYS_SWEVT_CHANNEL5_Pos 5 /**< \brief (EVSYS_SWEVT) Channel 5 Software Selection */ 499 #define EVSYS_SWEVT_CHANNEL5 (1 << EVSYS_SWEVT_CHANNEL5_Pos) 500 #define EVSYS_SWEVT_CHANNEL6_Pos 6 /**< \brief (EVSYS_SWEVT) Channel 6 Software Selection */ 501 #define EVSYS_SWEVT_CHANNEL6 (1 << EVSYS_SWEVT_CHANNEL6_Pos) 502 #define EVSYS_SWEVT_CHANNEL7_Pos 7 /**< \brief (EVSYS_SWEVT) Channel 7 Software Selection */ 503 #define EVSYS_SWEVT_CHANNEL7 (1 << EVSYS_SWEVT_CHANNEL7_Pos) 504 #define EVSYS_SWEVT_CHANNEL8_Pos 8 /**< \brief (EVSYS_SWEVT) Channel 8 Software Selection */ 505 #define EVSYS_SWEVT_CHANNEL8 (1 << EVSYS_SWEVT_CHANNEL8_Pos) 506 #define EVSYS_SWEVT_CHANNEL9_Pos 9 /**< \brief (EVSYS_SWEVT) Channel 9 Software Selection */ 507 #define EVSYS_SWEVT_CHANNEL9 (1 << EVSYS_SWEVT_CHANNEL9_Pos) 508 #define EVSYS_SWEVT_CHANNEL10_Pos 10 /**< \brief (EVSYS_SWEVT) Channel 10 Software Selection */ 509 #define EVSYS_SWEVT_CHANNEL10 (1 << EVSYS_SWEVT_CHANNEL10_Pos) 510 #define EVSYS_SWEVT_CHANNEL11_Pos 11 /**< \brief (EVSYS_SWEVT) Channel 11 Software Selection */ 511 #define EVSYS_SWEVT_CHANNEL11 (1 << EVSYS_SWEVT_CHANNEL11_Pos) 512 #define EVSYS_SWEVT_CHANNEL_Pos 0 /**< \brief (EVSYS_SWEVT) Channel x Software Selection */ 513 #define EVSYS_SWEVT_CHANNEL_Msk (_U(0xFFF) << EVSYS_SWEVT_CHANNEL_Pos) 514 #define EVSYS_SWEVT_CHANNEL(value) (EVSYS_SWEVT_CHANNEL_Msk & ((value) << EVSYS_SWEVT_CHANNEL_Pos)) 515 #define EVSYS_SWEVT_MASK _U(0x00000FFF) /**< \brief (EVSYS_SWEVT) MASK Register */ 516 517 /* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x20) (R/W 32) Channel n -------- */ 518 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 519 typedef union { 520 struct { 521 uint32_t EVGEN:7; /*!< bit: 0.. 6 Event Generator Selection */ 522 uint32_t :1; /*!< bit: 7 Reserved */ 523 uint32_t PATH:2; /*!< bit: 8.. 9 Path Selection */ 524 uint32_t EDGSEL:2; /*!< bit: 10..11 Edge Detection Selection */ 525 uint32_t :2; /*!< bit: 12..13 Reserved */ 526 uint32_t RUNSTDBY:1; /*!< bit: 14 Run in standby */ 527 uint32_t ONDEMAND:1; /*!< bit: 15 Generic Clock On Demand */ 528 uint32_t :16; /*!< bit: 16..31 Reserved */ 529 } bit; /*!< Structure used for bit access */ 530 uint32_t reg; /*!< Type used for register access */ 531 } EVSYS_CHANNEL_Type; 532 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 533 534 #define EVSYS_CHANNEL_OFFSET 0x20 /**< \brief (EVSYS_CHANNEL offset) Channel n */ 535 #define EVSYS_CHANNEL_RESETVALUE _U(0x00008000) /**< \brief (EVSYS_CHANNEL reset_value) Channel n */ 536 537 #define EVSYS_CHANNEL_EVGEN_Pos 0 /**< \brief (EVSYS_CHANNEL) Event Generator Selection */ 538 #define EVSYS_CHANNEL_EVGEN_Msk (_U(0x7F) << EVSYS_CHANNEL_EVGEN_Pos) 539 #define EVSYS_CHANNEL_EVGEN(value) (EVSYS_CHANNEL_EVGEN_Msk & ((value) << EVSYS_CHANNEL_EVGEN_Pos)) 540 #define EVSYS_CHANNEL_PATH_Pos 8 /**< \brief (EVSYS_CHANNEL) Path Selection */ 541 #define EVSYS_CHANNEL_PATH_Msk (_U(0x3) << EVSYS_CHANNEL_PATH_Pos) 542 #define EVSYS_CHANNEL_PATH(value) (EVSYS_CHANNEL_PATH_Msk & ((value) << EVSYS_CHANNEL_PATH_Pos)) 543 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val _U(0x0) /**< \brief (EVSYS_CHANNEL) Synchronous path */ 544 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val _U(0x1) /**< \brief (EVSYS_CHANNEL) Resynchronized path */ 545 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val _U(0x2) /**< \brief (EVSYS_CHANNEL) Asynchronous path */ 546 #define EVSYS_CHANNEL_PATH_SYNCHRONOUS (EVSYS_CHANNEL_PATH_SYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) 547 #define EVSYS_CHANNEL_PATH_RESYNCHRONIZED (EVSYS_CHANNEL_PATH_RESYNCHRONIZED_Val << EVSYS_CHANNEL_PATH_Pos) 548 #define EVSYS_CHANNEL_PATH_ASYNCHRONOUS (EVSYS_CHANNEL_PATH_ASYNCHRONOUS_Val << EVSYS_CHANNEL_PATH_Pos) 549 #define EVSYS_CHANNEL_EDGSEL_Pos 10 /**< \brief (EVSYS_CHANNEL) Edge Detection Selection */ 550 #define EVSYS_CHANNEL_EDGSEL_Msk (_U(0x3) << EVSYS_CHANNEL_EDGSEL_Pos) 551 #define EVSYS_CHANNEL_EDGSEL(value) (EVSYS_CHANNEL_EDGSEL_Msk & ((value) << EVSYS_CHANNEL_EDGSEL_Pos)) 552 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val _U(0x0) /**< \brief (EVSYS_CHANNEL) No event output when using the resynchronized or synchronous path */ 553 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val _U(0x1) /**< \brief (EVSYS_CHANNEL) Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path */ 554 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val _U(0x2) /**< \brief (EVSYS_CHANNEL) Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path */ 555 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val _U(0x3) /**< \brief (EVSYS_CHANNEL) Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path */ 556 #define EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT (EVSYS_CHANNEL_EDGSEL_NO_EVT_OUTPUT_Val << EVSYS_CHANNEL_EDGSEL_Pos) 557 #define EVSYS_CHANNEL_EDGSEL_RISING_EDGE (EVSYS_CHANNEL_EDGSEL_RISING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) 558 #define EVSYS_CHANNEL_EDGSEL_FALLING_EDGE (EVSYS_CHANNEL_EDGSEL_FALLING_EDGE_Val << EVSYS_CHANNEL_EDGSEL_Pos) 559 #define EVSYS_CHANNEL_EDGSEL_BOTH_EDGES (EVSYS_CHANNEL_EDGSEL_BOTH_EDGES_Val << EVSYS_CHANNEL_EDGSEL_Pos) 560 #define EVSYS_CHANNEL_RUNSTDBY_Pos 14 /**< \brief (EVSYS_CHANNEL) Run in standby */ 561 #define EVSYS_CHANNEL_RUNSTDBY (_U(0x1) << EVSYS_CHANNEL_RUNSTDBY_Pos) 562 #define EVSYS_CHANNEL_ONDEMAND_Pos 15 /**< \brief (EVSYS_CHANNEL) Generic Clock On Demand */ 563 #define EVSYS_CHANNEL_ONDEMAND (_U(0x1) << EVSYS_CHANNEL_ONDEMAND_Pos) 564 #define EVSYS_CHANNEL_MASK _U(0x0000CF7F) /**< \brief (EVSYS_CHANNEL) MASK Register */ 565 566 /* -------- EVSYS_USER : (EVSYS Offset: 0x80) (R/W 32) User Multiplexer n -------- */ 567 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 568 typedef union { 569 struct { 570 uint32_t CHANNEL:5; /*!< bit: 0.. 4 Channel Event Selection */ 571 uint32_t :27; /*!< bit: 5..31 Reserved */ 572 } bit; /*!< Structure used for bit access */ 573 uint32_t reg; /*!< Type used for register access */ 574 } EVSYS_USER_Type; 575 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 576 577 #define EVSYS_USER_OFFSET 0x80 /**< \brief (EVSYS_USER offset) User Multiplexer n */ 578 #define EVSYS_USER_RESETVALUE _U(0x00000000) /**< \brief (EVSYS_USER reset_value) User Multiplexer n */ 579 580 #define EVSYS_USER_CHANNEL_Pos 0 /**< \brief (EVSYS_USER) Channel Event Selection */ 581 #define EVSYS_USER_CHANNEL_Msk (_U(0x1F) << EVSYS_USER_CHANNEL_Pos) 582 #define EVSYS_USER_CHANNEL(value) (EVSYS_USER_CHANNEL_Msk & ((value) << EVSYS_USER_CHANNEL_Pos)) 583 #define EVSYS_USER_MASK _U(0x0000001F) /**< \brief (EVSYS_USER) MASK Register */ 584 585 /** \brief EVSYS hardware registers */ 586 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 587 typedef struct { 588 __IO EVSYS_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 589 RoReg8 Reserved1[0xB]; 590 __I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */ 591 __IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */ 592 __IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */ 593 __IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */ 594 __O EVSYS_SWEVT_Type SWEVT; /**< \brief Offset: 0x1C ( /W 32) Software Event */ 595 __IO EVSYS_CHANNEL_Type CHANNEL[12]; /**< \brief Offset: 0x20 (R/W 32) Channel n */ 596 RoReg8 Reserved2[0x30]; 597 __IO EVSYS_USER_Type USER[45]; /**< \brief Offset: 0x80 (R/W 32) User Multiplexer n */ 598 } Evsys; 599 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 600 601 /*@}*/ 602 603 #endif /* _SAML21_EVSYS_COMPONENT_ */ 604
