1 /**
2 *
3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
4 *
5 * \asf_license_start
6 *
7 * \page License
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License"); you may
12 * not use this file except in compliance with the License.
13 * You may obtain a copy of the Licence at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 *
23 * \asf_license_stop
24 *
25 */
26
27 /** @file espi_vw.h
28 *MEC1501 eSPI Virtual Wire definitions
29 */
30 /** @defgroup MEC1501 Peripherals eSPI VW
31 */
32
33 #include <stdint.h>
34 #include <stddef.h>
35
36 #ifndef _ESPI_VW_H
37 #define _ESPI_VW_H
38
39 /*------------------------------------------------------------------*/
40
41 /* Host to Device VW register: 96-bit (3 32 bit registers) */
42 /* 32-bit word 0 (bits[31:0]) */
43 #define ESPI_M2SW0_OFS 0u
44 #define ESPI_M2SW0_IDX_POS 0
45 #define ESPI_M2SW0_IDX_MASK 0xffu
46 #define ESPI_M2SW0_MTOS_SRC_POS 8u
47 #define ESPI_M2SW0_MTOS_SRC_MASK0 0x03u
48 #define ESPI_M2SW0_MTOS_SRC_MASK ((ESPI_VW_M2S_MTOS_SRC_MASK0) << (ESPI_VW_M2S_MTOS_SRC_POS))
49 #define ESPI_M2SW0_MTOS_SRC_ESPI_RST ((0u) << (ESPI_VW_M2S_MTOS_SRC_POS))
50 #define ESPI_M2SW0_MTOS_SRC_SYS_RST ((1u) << (ESPI_VW_M2S_MTOS_SRC_POS))
51 #define ESPI_M2SW0_MTOS_SRC_SIO_RST ((2u) << (ESPI_VW_M2S_MTOS_SRC_POS))
52 #define ESPI_M2SW0_MTOS_SRC_PLTRST ((3u) << (ESPI_VW_M2S_MTOS_SRC_POS))
53 #define ESPI_M2SW0_MTOS_STATE_POS 12u
54 #define ESPI_M2SW0_MTOS_STATE_MASK0 0x0fu
55 #define ESPI_M2SW0_MTOS_STATE_MASK ((ESPI_VW_M2S_MTOS_STATE_MASK0) << (ESPI_VW_M2S_MTOS_STATE_POS))
56 /* 32-bit word 1 (bits[63:32]) */
57 #define ESPI_M2SW1_OFS 4u
58 #define ESPI_M2SW1_SRC0_SEL_POS 0
59 #define ESPI_M2SW1_SRC_SEL_MASK0 0x0fu
60 #define ESPI_M2SW1_SRC0_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC0_SEL_POS))
61 #define ESPI_M2SW1_SRC1_SEL_POS 8
62 #define ESPI_M2SW1_SRC1_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC1_SEL_POS))
63 #define ESPI_M2SW1_SRC2_SEL_POS 16
64 #define ESPI_M2SW1_SRC2_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC2_SEL_POS))
65 #define ESPI_M2SW1_SRC3_SEL_POS 24
66 #define ESPI_M2SW1_SRC3_SEL_MASK ((ESPI_M2SW1_SRC_SEL_MASK0) << (ESPI_M2SW1_SRC3_SEL_POS))
67 /* 0 <= n < 4 */
68 #define ESPI_M2SW1_SRC_SEL_POS(n) ((n) << 3)
69 #define ESPI_M2SW1_SRC_SEL_MASK(n) ((0x0fu) << (ESPI_M2SW1_SRC_SEL_POS(n)))
70 #define ESPI_M2SW1_SRC_SEL_VAL(n, v) (((uint32_t)(v) & 0x0fu) << (ESPI_M2SW1_SRC_SEL_POS(n)))
71 /* 32-bit word 2 (bits[95:64]) */
72 #define ESPI_M2SW2_OFS 8u
73 #define ESPI_M2SW2_SRC_MASK0 0x0fu
74 #define ESPI_M2SW2_SRC0_POS 0
75 #define ESPI_M2SW2_SRC0_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW1_SRC0_POS))
76 #define ESPI_M2SW2_SRC1_POS 8u
77 #define ESPI_M2SW2_SRC1_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW1_SRC1_POS))
78 #define ESPI_M2SW2_SRC2_POS 16u
79 #define ESPI_M2SW2_SRC2_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW2_SRC1_POS))
80 #define ESPI_M2SW2_SRC3_POS 24u
81 #define ESPI_M2SW2_SRC3_MASK ((ESPI_M2SW1_SRC_MASK0) << (ESPI_M2SW2_SRC3_POS))
82 /* 0 <= n < 4 */
83 #define ESPI_M2SW2_SRC_POS(n) ((n) << 3)
84 #define ESPI_M2SW2_SRC_MASK(n) ((ESPI_M2SW2_SRC_MASK0) << (ESPI_M2SW2_SRC_POS(n)))
85 #define ESPI_M2SW2_SRC_VAL(n, v) (((uint32_t)(v) & 0x0fu) << (ESPI_M2SW2_SRC_POS(n)))
86
87 /*
88 * Zero based values used for above SRC_SEL fields.
89 * These values select the interrupt sensitivity for the VWire.
90 * Example: Set SRC1 to Level High
91 *
92 * r = read MSVW1 register
93 * r &= ESPI_M2SW1_SRC_SEL_MASK(1)
94 * r |= ESPI_MSVW1_SRC_SEL_VAL(1, ESPI_IRQ_SEL_LVL_HI)
95 * write r to MSVW1 register
96 */
97 #define ESPI_IRQ_SEL_LVL_LO 0
98 #define ESPI_IRQ_SEL_LVL_HI 1
99 #define ESPI_IRQ_SEL_DIS 4
100 /* NOTE: Edge trigger modes allow VWires to wake MEC1501 from deep sleep */
101 #define ESPI_IRQ_SEL_REDGE 0x0d
102 #define ESPI_IRQ_SEL_FEDGE 0x0e
103 #define ESPI_IRQ_SEL_BEDGE 0x0f
104
105 /* Device to Host VW register: 64-bit (2 32 bit registers) */
106 /* 32-bit word 0 (bits[31:0]) */
107 #define ESPI_S2MW0_OFS 0
108 #define ESPI_S2MW0_IDX_POS 0
109 #define ESPI_S2MW0_IDX_MASK 0xffu
110 #define ESPI_S2MW0_STOM_POS 8u
111 #define ESPI_S2MW0_STOM_SRC_POS 8u
112 #define ESPI_S2MW0_STOM_MASK0 0xf3u
113 #define ESPI_S2MW0_STOM_MASK ((ESPI_S2MW0_STOM_MASK0) << (ESPI_S2MW0_STOM_SRC_POS))
114 #define ESPI_S2MW0_STOM_SRC_MASK0 0x03u
115 #define ESPI_S2MW0_STOM_SRC_MASK ((ESPI_S2MW0_STOM_SRC_MASK0) << (ESPI_S2MW0_STOM_SRC_POS))
116 #define ESPI_S2MW0_STOM_SRC_ESPI_RST ((0u) << (ESPI_S2MW0_STOM_SRC_POS))
117 #define ESPI_S2MW0_STOM_SRC_SYS_RST ((1u) << (ESPI_S2MW0_STOM_SRC_POS))
118 #define ESPI_S2MW0_STOM_SRC_SIO_RST ((2u) << (ESPI_S2MW0_STOM_SRC_POS))
119 #define ESPI_S2MW0_STOM_SRC_PLTRST ((3u) << (ESPI_S2MW0_STOM_SRC_POS))
120 #define ESPI_S2MW0_STOM_STATE_POS 12u
121 #define ESPI_S2MW0_STOM_STATE_MASK0 0x0fu
122 #define ESPI_S2MW0_STOM_STATE_MASK ((ESPI_S2MW0_STOM_STATE_MASK0) << (ESPI_S2MW0_STOM_STATE_POS))
123 #define ESPI_S2MW0_CHG0_POS 16u
124 #define ESPI_S2MW0_CHG0 (1u << (ESPI_S2MW0_CHG0_POS))
125 #define ESPI_S2MW0_CHG1_POS 17u
126 #define ESPI_S2MW0_CHG1 (1u << (ESPI_S2MW0_CHG1_POS))
127 #define ESPI_S2MW0_CHG2_POS 18u
128 #define ESPI_S2MW0_CHG2 (1u << (ESPI_S2MW0_CHG2_POS))
129 #define ESPI_S2MW0_CHG3_POS 19u
130 #define ESPI_S2MW0_CHG3 (1u << (ESPI_S2MW0_CHG3_POS))
131 #define ESPI_S2MW0_CHG_ALL_POS 16u
132 #define ESPI_S2MW0_CHG_ALL_MASK0 0x0fu
133 #define ESPI_S2MW0_CHG_ALL_MASK ((ESPI_S2MW0_CHG_ALL_MASK0) << (ESPI_S2MW0_CHG0_POS))
134 /* 0 <= n < 4 */
135 #define ESPI_S2MW1_CHG_POS(n) ((n) + 16u)
136 #define ESPI_S2MW1_CHG(v, n) (((uint32_t)(v) >> ESPI_S2MW1_CHG_POS(n)) & 0x01)
137
138 /* 32-bit word 1 (bits[63:32]) */
139 #define ESPI_S2MW1_OFS 4u
140 #define ESPI_S2MW1_SRC0_POS 0u
141 #define ESPI_S2MW1_SRC0 (1u << (ESPI_S2MW1_SRC0_POS))
142 #define ESPI_S2MW1_SRC1_POS 8u
143 #define ESPI_S2MW1_SRC1 (1u << (ESPI_S2MW1_SRC1_POS))
144 #define ESPI_S2MW1_SRC2_POS 16u
145 #define ESPI_S2MW1_SRC2 (1u << (ESPI_S2MW1_SRC2_POS))
146 #define ESPI_S2MW1_SRC3_POS 24u
147 #define ESPI_S2MW1_SRC3 (1u << (ESPI_S2MW1_SRC3_POS))
148 /* 0 <= n < 4 */
149 #define ESPI_S2MW1_SRC_POS(n) ((n) << 3)
150 #define ESPI_S2MW1_SRC(v, n) (((uint32_t)(v) & 0x01) << (ESPI_S2MW1_SRC_POS(n)))
151
152 /* =========================================================================*/
153 /* ================ ESPI_VW ================ */
154 /* =========================================================================*/
155
156 /**
157 * @brief eSPI Virtual Wires (ESPI_VW)
158 */
159
160 #define ESPI_MSVW_IDX_MAX 10u
161 #define ESPI_SMVW_IDX_MAX 10u
162
163 #define ESPI_NUM_MSVW 11u
164 #define ESPI_NUM_SMVW 11u
165
166 /*
167 * ESPI MSVW interrupts
168 * GIRQ24 contains MSVW 0 - 6
169 * GIRQ25 contains MSVW 7 - 10
170 */
171 #define MEC_ESPI_MSVW_NUM_GIRQS 2u
172
173 #define MEC_ESPI_MSVW_00_06_GIRQ 24u
174 #define MEC_ESPI_MSVW_00_06_NVIC 15u
175
176 #define MEC_ESPI_MSVW00_SRC0_POS 0u
177 #define MEC_ESPI_MSVW00_SRC1_POS 1u
178 #define MEC_ESPI_MSVW00_SRC2_POS 2u
179 #define MEC_ESPI_MSVW00_SRC3_POS 3u
180 #define MEC_ESPI_MSVW01_SRC0_POS 4u
181 #define MEC_ESPI_MSVW01_SRC1_POS 5u
182 #define MEC_ESPI_MSVW01_SRC2_POS 6u
183 #define MEC_ESPI_MSVW01_SRC3_POS 7u
184 #define MEC_ESPI_MSVW02_SRC0_POS 8u
185 #define MEC_ESPI_MSVW02_SRC1_POS 9u
186 #define MEC_ESPI_MSVW02_SRC2_POS 10u
187 #define MEC_ESPI_MSVW02_SRC3_POS 11u
188 #define MEC_ESPI_MSVW03_SRC0_POS 12u
189 #define MEC_ESPI_MSVW03_SRC1_POS 13u
190 #define MEC_ESPI_MSVW03_SRC2_POS 14u
191 #define MEC_ESPI_MSVW03_SRC3_POS 15u
192 #define MEC_ESPI_MSVW04_SRC0_POS 16u
193 #define MEC_ESPI_MSVW04_SRC1_POS 17u
194 #define MEC_ESPI_MSVW04_SRC2_POS 16u
195 #define MEC_ESPI_MSVW04_SRC3_POS 19u
196 #define MEC_ESPI_MSVW05_SRC0_POS 20u
197 #define MEC_ESPI_MSVW05_SRC1_POS 21u
198 #define MEC_ESPI_MSVW05_SRC2_POS 22u
199 #define MEC_ESPI_MSVW05_SRC3_POS 23u
200 #define MEC_ESPI_MSVW06_SRC0_POS 24u
201 #define MEC_ESPI_MSVW06_SRC1_POS 25u
202 #define MEC_ESPI_MSVW06_SRC2_POS 26u
203 #define MEC_ESPI_MSVW06_SRC3_POS 27u
204
205 #define MEC_ESPI_MSVW00_SRC0_VAL (1 << MEC_ESPI_MSVW00_SRC0_POS)
206 #define MEC_ESPI_MSVW00_SRC1_VAL (1 << MEC_ESPI_MSVW00_SRC1_POS)
207 #define MEC_ESPI_MSVW00_SRC2_VAL (1 << MEC_ESPI_MSVW00_SRC2_POS)
208 #define MEC_ESPI_MSVW00_SRC3_VAL (1 << MEC_ESPI_MSVW00_SRC3_POS)
209 #define MEC_ESPI_MSVW01_SRC0_VAL (1 << MEC_ESPI_MSVW01_SRC0_POS)
210 #define MEC_ESPI_MSVW01_SRC1_VAL (1 << MEC_ESPI_MSVW01_SRC1_POS)
211 #define MEC_ESPI_MSVW01_SRC2_VAL (1 << MEC_ESPI_MSVW01_SRC2_POS)
212 #define MEC_ESPI_MSVW01_SRC3_VAL (1 << MEC_ESPI_MSVW01_SRC3_POS)
213 #define MEC_ESPI_MSVW02_SRC0_VAL (1 << MEC_ESPI_MSVW02_SRC0_POS)
214 #define MEC_ESPI_MSVW02_SRC1_VAL (1 << MEC_ESPI_MSVW02_SRC1_POS)
215 #define MEC_ESPI_MSVW02_SRC2_VAL (1 << MEC_ESPI_MSVW02_SRC2_POS)
216 #define MEC_ESPI_MSVW02_SRC3_VAL (1 << MEC_ESPI_MSVW02_SRC3_POS)
217 #define MEC_ESPI_MSVW03_SRC0_VAL (1 << MEC_ESPI_MSVW03_SRC0_POS)
218 #define MEC_ESPI_MSVW03_SRC1_VAL (1 << MEC_ESPI_MSVW03_SRC1_POS)
219 #define MEC_ESPI_MSVW03_SRC2_VAL (1 << MEC_ESPI_MSVW03_SRC2_POS)
220 #define MEC_ESPI_MSVW03_SRC3_VAL (1 << MEC_ESPI_MSVW03_SRC3_POS)
221 #define MEC_ESPI_MSVW04_SRC0_VAL (1 << MEC_ESPI_MSVW04_SRC0_POS)
222 #define MEC_ESPI_MSVW04_SRC1_VAL (1 << MEC_ESPI_MSVW04_SRC1_POS)
223 #define MEC_ESPI_MSVW04_SRC2_VAL (1 << MEC_ESPI_MSVW04_SRC2_POS)
224 #define MEC_ESPI_MSVW04_SRC3_VAL (1 << MEC_ESPI_MSVW04_SRC3_POS)
225 #define MEC_ESPI_MSVW05_SRC0_VAL (1 << MEC_ESPI_MSVW05_SRC0_POS)
226 #define MEC_ESPI_MSVW05_SRC1_VAL (1 << MEC_ESPI_MSVW05_SRC1_POS)
227 #define MEC_ESPI_MSVW05_SRC2_VAL (1 << MEC_ESPI_MSVW05_SRC2_POS)
228 #define MEC_ESPI_MSVW05_SRC3_VAL (1 << MEC_ESPI_MSVW05_SRC3_POS)
229 #define MEC_ESPI_MSVW06_SRC0_VAL (1 << MEC_ESPI_MSVW06_SRC0_POS)
230 #define MEC_ESPI_MSVW06_SRC1_VAL (1 << MEC_ESPI_MSVW06_SRC1_POS)
231 #define MEC_ESPI_MSVW06_SRC2_VAL (1 << MEC_ESPI_MSVW06_SRC2_POS)
232 #define MEC_ESPI_MSVW06_SRC3_VAL (1 << MEC_ESPI_MSVW06_SRC3_POS)
233
234 #define MEC_ESPI_VSVW_07_10_GIRQ 25u
235 #define MEC_ESPI_VSVW_07_10_NVIC 16u
236
237 #define MEC_ESPI_MSVW07_SRC0_POS 0u
238 #define MEC_ESPI_MSVW07_SRC1_POS 1u
239 #define MEC_ESPI_MSVW07_SRC2_POS 2u
240 #define MEC_ESPI_MSVW07_SRC3_POS 3u
241 #define MEC_ESPI_MSVW08_SRC0_POS 4u
242 #define MEC_ESPI_MSVW08_SRC1_POS 5u
243 #define MEC_ESPI_MSVW08_SRC2_POS 6u
244 #define MEC_ESPI_MSVW08_SRC3_POS 7u
245 #define MEC_ESPI_MSVW09_SRC0_POS 8u
246 #define MEC_ESPI_MSVW09_SRC1_POS 9u
247 #define MEC_ESPI_MSVW09_SRC2_POS 10u
248 #define MEC_ESPI_MSVW09_SRC3_POS 11u
249 #define MEC_ESPI_MSVW10_SRC0_POS 12u
250 #define MEC_ESPI_MSVW10_SRC1_POS 13u
251 #define MEC_ESPI_MSVW10_SRC2_POS 14u
252 #define MEC_ESPI_MSVW10_SRC3_POS 15u
253
254 #define MEC_ESPI_MSVW07_SRC0_VAL (1U << MEC_ESPI_MSVW07_SRC0_POS)
255 #define MEC_ESPI_MSVW07_SRC1_VAL (1U << MEC_ESPI_MSVW07_SRC1_POS)
256 #define MEC_ESPI_MSVW07_SRC2_VAL (1U << MEC_ESPI_MSVW07_SRC2_POS)
257 #define MEC_ESPI_MSVW07_SRC3_VAL (1U << MEC_ESPI_MSVW07_SRC3_POS)
258 #define MEC_ESPI_MSVW08_SRC0_VAL (1U << MEC_ESPI_MSVW08_SRC0_POS)
259 #define MEC_ESPI_MSVW08_SRC1_VAL (1U << MEC_ESPI_MSVW08_SRC1_POS)
260 #define MEC_ESPI_MSVW08_SRC2_VAL (1U << MEC_ESPI_MSVW08_SRC2_POS)
261 #define MEC_ESPI_MSVW08_SRC3_VAL (1U << MEC_ESPI_MSVW08_SRC3_POS)
262 #define MEC_ESPI_MSVW09_SRC0_VAL (1U << MEC_ESPI_MSVW09_SRC0_POS)
263 #define MEC_ESPI_MSVW09_SRC1_VAL (1U << MEC_ESPI_MSVW09_SRC1_POS)
264 #define MEC_ESPI_MSVW09_SRC2_VAL (1U << MEC_ESPI_MSVW09_SRC2_POS)
265 #define MEC_ESPI_MSVW09_SRC3_VAL (1U << MEC_ESPI_MSVW09_SRC3_POS)
266 #define MEC_ESPI_MSVW10_SRC0_VAL (1U << MEC_ESPI_MSVW10_SRC0_POS)
267 #define MEC_ESPI_MSVW10_SRC1_VAL (1U << MEC_ESPI_MSVW10_SRC1_POS)
268 #define MEC_ESPI_MSVW10_SRC2_VAL (1U << MEC_ESPI_MSVW10_SRC2_POS)
269 #define MEC_ESPI_MSVW10_SRC3_VAL (1U << MEC_ESPI_MSVW10_SRC3_POS)
270
271 /* Host-to-Device VW byte indices(offsets) */
272 #define MSVW_INDEX_OFS 0u
273 #define MSVW_MTOS_OFS 1u
274 #define MSVW_SRC0_ISEL_OFS 4u
275 #define MSVW_SRC1_ISEL_OFS 5u
276 #define MSVW_SRC2_ISEL_OFS 6u
277 #define MSVW_SRC3_ISEL_OFS 7u
278 #define MSVW_SRC0_OFS 8u
279 #define MSVW_SRC1_OFS 9u
280 #define MSVW_SRC2_OFS 10u
281 #define MSVW_SRC3_OFS 11u
282
283 /* Device-to-Host VW byte indices(offsets) */
284 #define SMVW_INDEX_OFS 0u
285 #define SMVW_STOM_OFS 1u
286 #define SMVW_CHANGED_OFS 2u
287 #define SMVW_SRC0_OFS 4u
288 #define SMVW_SRC1_OFS 5u
289 #define SMVW_SRC2_OFS 6u
290 #define SMVW_SRC3_OFS 7u
291
292 /*
293 * ESPI_IO_VW - eSPI IO component registers related to VW channel @ 0x400f36b0
294 */
295 typedef struct espi_io_vw_en {
296 __IOM uint32_t VW_EN_STS; /*! (@ 0x0000) Virtual Wire Enable Status */
297 uint8_t RSVD1[0x30];
298 __IOM uint8_t VW_CAP; /*! (@ 0x0034) Virtual Wire Chan Capabilities */
299 uint8_t RSVD2[8];
300 __IOM uint8_t VW_RDY; /*! (@ 0x003d) VW ready */
301 uint8_t RSVD3[0x102];
302 __IOM uint32_t VW_ERR_STS; /*! (@ 0x0140) IO Virtual Wire Error */
303 } ESPI_IO_VW_Type;
304
305 /* Host-to-Device Virtual Wire 96-bit register */
306
307 #define MEC_MSVW_SRC0_IRQ_SEL_POS 0u
308 #define MEC_MSVW_SRC1_IRQ_SEL_POS 8u
309 #define MEC_MSVW_SRC2_IRQ_SEL_POS 16u
310 #define MEC_MSVW_SRC3_IRQ_SEL_POS 24u
311
312 #define MEC_MSVW_SRC_IRQ_SEL_MASK0 0x0fu
313 #define MEC_MSVW_SRC0_IRQ_SEL_MASK (0x0fu << 8)
314 #define MEC_MSVW_SRC1_IRQ_SEL_MASK (0x0fu << 16)
315 #define MEC_MSVW_SRC2_IRQ_SEL_MASK (0x0fu << 16)
316 #define MEC_MSVW_SRC3_IRQ_SEL_MASK (0x0fu << 24)
317
318 #define MEC_MSVW_SRC_IRQ_SEL_LVL_LO 0x00u
319 #define MEC_MSVW_SRC_IRQ_SEL_LVL_HI 0x01u
320 #define MEC_MSVW_SRC_IRQ_SEL_DIS 0x04u
321 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_FALL 0x0du
322 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_RISE 0x0eu
323 #define MEC_MSVW_SRC_IRQ_SEL_EDGE_BOTH 0x0fu
324
325 /*
326 * 0 <= src <= 3
327 * isel = MEC_MSVW_SRC_IRQ_SEL_LVL_LO, ...
328 */
329 #define MEC_MSVW_SRC_IRQ_SEL_VAL(src, isel) ((uint32_t)(isel) << ((src) << 3))
330
331 #define MEC_MSVW_SRC0_POS 0u
332 #define MEC_MSVW_SRC1_POS 8u
333 #define MEC_MSVW_SRC2_POS 16u
334 #define MEC_MSVW_SRC3_POS 24u
335
336 #define MEC_MSVW_SRC_MASK0 0x01u
337
338 #define MEC_MSVW_SRC0_MASK (0x01u << 0)
339 #define MEC_MSVW_SRC1_MASK (0x01u << 8)
340 #define MEC_MSVW_SRC2_MASK (0x01u << 16)
341 #define MEC_MSVW_SRC3_MASK (0x01u << 24)
342
343 /*
344 * 0 <= src <= 3
345 * val = 0 or 1
346 */
347 #define MEC_MSVW_SRC_VAL(src, val) ((uint32_t)(val & 0x01u) << ((src) << 3))
348
349 typedef struct espi_msvw_reg {
350 __IOM uint8_t INDEX;
351 __IOM uint8_t MTOS;
352 uint8_t RSVD1[2];
353 __IOM uint32_t SRC_IRQ_SEL;
354 __IOM uint32_t SRC;
355 } ESPI_MSVW_REG;
356
357 typedef struct espi_msvw_named_regs {
358 ESPI_MSVW_REG MSVW00;
359 ESPI_MSVW_REG MSVW01;
360 ESPI_MSVW_REG MSVW02;
361 ESPI_MSVW_REG MSVW03;
362 ESPI_MSVW_REG MSVW04;
363 ESPI_MSVW_REG MSVW05;
364 ESPI_MSVW_REG MSVW06;
365 ESPI_MSVW_REG MSVW07;
366 ESPI_MSVW_REG MSVW08;
367 ESPI_MSVW_REG MSVW09;
368 ESPI_MSVW_REG MSVW10;
369 } ESPI_M2S_VW_Type;
370
371 /* Device-to-Host Virtual Wire 64-bit register */
372
373 typedef struct espi_smvw_reg {
374 __IOM uint8_t INDEX;
375 __IOM uint8_t STOM;
376 __IM uint8_t SRC_CHG;
377 uint8_t RSVD1[1];
378 __IOM uint32_t SRC;
379 } ESPI_SMVW_REG;
380
381 typedef struct espi_smvw_named_regs {
382 ESPI_SMVW_REG SMVW00;
383 ESPI_SMVW_REG SMVW01;
384 ESPI_SMVW_REG SMVW02;
385 ESPI_SMVW_REG SMVW03;
386 ESPI_SMVW_REG SMVW04;
387 ESPI_SMVW_REG SMVW05;
388 ESPI_SMVW_REG SMVW06;
389 ESPI_SMVW_REG SMVW07;
390 ESPI_SMVW_REG SMVW08;
391 ESPI_SMVW_REG SMVW09;
392 ESPI_SMVW_REG SMVW10;
393 } ESPI_S2M_VW_Type;
394
395 /* Virtual Wire registers all-in-one register structures */
396 enum espi_h2d_vw_id { /* each ID controls 4 Virtual Wires */
397 MCHP_H2D_VW00 = 0,
398 MCHP_H2D_VW01,
399 MCHP_H2D_VW02,
400 MCHP_H2D_VW03,
401 MCHP_H2D_VW04,
402 MCHP_H2D_VW05,
403 MCHP_H2D_VW06,
404 MCHP_H2D_VW07,
405 MCHP_H2D_VW08,
406 MCHP_H2D_VW09,
407 MCHP_H2D_VW10,
408 MCHP_H2D_VW_MAX,
409 };
410
411 enum espi_d2h_vw_id { /* each ID controls 4 Virtual Wires */
412 MCHP_D2H_VW00 = 0,
413 MCHP_D2H_VW01,
414 MCHP_D2H_VW02,
415 MCHP_D2H_VW03,
416 MCHP_D2H_VW04,
417 MCHP_D2H_VW05,
418 MCHP_D2H_VW06,
419 MCHP_D2H_VW07,
420 MCHP_D2H_VW08,
421 MCHP_D2H_VW09,
422 MCHP_D2H_VW10,
423 MCHP_D2H_VW_MAX,
424 };
425
426 /** @brief eSPI Host to Device 96-bit register: controls 4 Virtual Wires */
427 struct espi_vw_h2d_reg {
428 volatile uint32_t IRSS;
429 volatile uint32_t IRQ_SELECT;
430 volatile uint32_t SRC;
431 }; /* Size = 12 (0xc) */
432
433 /** @brief Device to eSPI Host 64-bit register: controls 4 Virtual Wires */
434 struct espi_vw_d2h_reg {
435 volatile uint32_t IRSCH;
436 volatile uint32_t SRC;
437 }; /* Size = 8 (0x8) */
438
439 struct espi_vw_regs { /* @ 0x400f9c00 */
440 struct espi_vw_h2d_reg HDVW[11]; /* @ 0x0000 Host-to-Device VW */
441 uint32_t RESERVED[95];
442 struct espi_vw_d2h_reg DHVW[11]; /* @ 0x0200 Device-to-Host VW */
443 }; /* Size = 600 (0x258) */
444
445 /* MSVW helper inline functions */
446
447 enum espi_msvw_src {
448 MSVW_SRC0 = 0u,
449 MSVW_SRC1,
450 MSVW_SRC2,
451 MSVW_SRC3
452 };
453
454 enum espi_smvw_src {
455 SMVW_SRC0 = 0u,
456 SMVW_SRC1,
457 SMVW_SRC2,
458 SMVW_SRC3
459 };
460
461 enum espi_msvw_irq_sel {
462 MSVW_IRQ_SEL_LVL_LO = 0x00u,
463 MSVW_IRQ_SEL_LVL_HI = 0x01u,
464 MSVW_IRQ_SEL_DIS = 0x04u,
465 MSVW_IRQ_SEL_EDGE_FALL = 0x0du,
466 MSVW_IRQ_SEL_EDGE_RISE = 0x0eu,
467 MSVW_IRQ_SEL_EDGE_BOTH = 0x0fu
468 };
469
470 /* Used for both MSVW MTOS and SMVW STOM fields */
471 enum espi_vw_rst_src {
472 VW_RST_SRC_ESPI_RESET = 0u,
473 VW_RST_SRC_SYS_RESET,
474 VW_RST_SRC_SIO_RESET,
475 VW_RST_SRC_PLTRST,
476 };
477
478 /*
479 * Set the Host VWire index this MSVW implements.
480 */
481 static __attribute__ ((always_inline))
mec_espi_msvw_index_set(ESPI_MSVW_REG * p,uint8_t host_vw_index)482 inline void mec_espi_msvw_index_set(ESPI_MSVW_REG * p, uint8_t host_vw_index)
483 {
484 p->INDEX = host_vw_index;
485 }
486
487 static __attribute__ ((always_inline))
mec_espi_msvw_index_get(ESPI_MSVW_REG * p)488 inline uint8_t mec_espi_msvw_index_get(ESPI_MSVW_REG * p)
489 {
490 return p->INDEX;
491 }
492
493 /*
494 * This functions sets the two MTOS fields in a MSVW
495 * Reset source
496 * Reset value of SRC[3:0]
497 */
498 static __attribute__ ((always_inline))
499 inline void
mec_espi_msvw_mtos_set(ESPI_MSVW_REG * p,enum espi_vw_rst_src rst_src,uint8_t rst_val)500 mec_espi_msvw_mtos_set(ESPI_MSVW_REG * p, enum espi_vw_rst_src rst_src,
501 uint8_t rst_val)
502 {
503 p->MTOS = (rst_src & 0x03u) | ((rst_val & 0x0fu) << 4);
504 }
505
506 /*
507 * Set the specified Host-to-Device VWire's interrupt select field for
508 * the specified edge, level, or disabled.
509 * MSVW IRQ_SELECT is a 32-bit register where the four VWire's
510 * interrupt select fields are located on byte boundaries.
511 * Param p is a pointer to the 96-bit MSVW register.
512 * Param src is in [0:3] specifying one of the four VWire's.
513 * Param isel is the new value for the specified VWire's interrupt
514 * select field. IRQ_SELECT is the 32-bit word at bits[63:32] in the
515 * 96-bit MSVW register.
516 * IRQ_SELECT[3:0] = SRC0_IRQ_SELECT
517 * IRQ_SELECT[11:8] = SRC1_IRQ_SELECT
518 * IRQ_SELECT[19:16] = SRC1_IRQ_SELECT
519 * IRQ_SELECT[27:24] = SRC1_IRQ_SELECT
520 * The MSVW registers are byte accessible allowing us to avoid a
521 * read-modify-write.
522 */
523 static __attribute__ ((always_inline))
524 inline void
mec_espi_msvw_irq_sel_set(ESPI_MSVW_REG * p,enum espi_msvw_src src,enum espi_msvw_irq_sel isel)525 mec_espi_msvw_irq_sel_set(ESPI_MSVW_REG * p, enum espi_msvw_src src,
526 enum espi_msvw_irq_sel isel)
527 {
528 volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC_IRQ_SEL;
529
530 *(psrc + (uintptr_t) src) = isel;
531 }
532
533 /*
534 * Set all IRQ_SEL fields in a MSVW.
535 * Parameter isel_all must have IRQ_SEL fields at
536 * b[3:0], b[11:8], b[19:16], b[27:24].
537 */
538 static __attribute__ ((always_inline))
mec_espi_msvw_irq_sel_set_all(ESPI_MSVW_REG * p,uint32_t isel_all)539 inline void mec_espi_msvw_irq_sel_set_all(ESPI_MSVW_REG * p, uint32_t isel_all)
540 {
541 p->SRC_IRQ_SEL = isel_all;
542 }
543
544 /*
545 * Set the specified Host-to-Device VWire state.
546 * MSVW.SRC is a 32-bit component at bits[95:64] where states of the
547 * four VWire's it controls are located on byte boundaries.
548 * Param p is a pointer to the 96-bit MSVW register.
549 * Param src is in [0:3] specifying one of the four VWire's.
550 * Param src_val is the new VWire state.
551 * SRC member is the 32-bit word at bits[95:64] in the MSVW structure.
552 * SRC[3:0] = SRC0 VWire state
553 * SRC[11:8] = SRC1 VWire state
554 * SRC[19:16] = SRC1 VWire state
555 * SRC[27:24] = SRC1 VWire state
556 * The MSVW registers are byte accessible allowing us to avoid a
557 * read-modify-write.
558 */
559 static __attribute__ ((always_inline))
560 inline void
mec_espi_msvw_set(ESPI_MSVW_REG * p,enum espi_msvw_src src,uint8_t src_val)561 mec_espi_msvw_set(ESPI_MSVW_REG * p, enum espi_msvw_src src, uint8_t src_val)
562 {
563 volatile uint8_t *psrc = (volatile uint8_t *)&p->SRC;
564
565 *(psrc + (uintptr_t) src) = src_val;
566 }
567
568 static __attribute__ ((always_inline))
mec_espi_msvw_get(ESPI_MSVW_REG * p,enum espi_msvw_src src)569 inline uint8_t mec_espi_msvw_get(ESPI_MSVW_REG * p, enum espi_msvw_src src)
570 {
571 return (uint8_t) ((p->SRC >> (src << 3)) & 0x01u);
572 }
573
574 /*
575 * Return 32-bit unsigned word containing all 4 MSVW SRC bits in
576 * bit positions 0, 8, 16, and 24.
577 */
578 static __attribute__ ((always_inline))
mec_espi_msvw_get_all(ESPI_MSVW_REG * p)579 inline uint32_t mec_espi_msvw_get_all(ESPI_MSVW_REG * p)
580 {
581 return p->SRC;
582 }
583
584 /*
585 * Write 32-bit unsigned word containing all 4 MSVW SRC bits in
586 * bit positions 0, 8, 16, and 24.
587 * NOTE: eSPI host will only see changes to Host-to-Device VWires
588 * if it requests reading them.
589 */
590 static __attribute__ ((always_inline))
mec_espi_msvw_set_all(ESPI_MSVW_REG * p,uint32_t val)591 inline void mec_espi_msvw_set_all(ESPI_MSVW_REG * p, uint32_t val)
592 {
593 p->SRC = val;
594 }
595
596 /* SMVW helper inline functions */
597
598 /*
599 * Set the Host VWire index this SMVW implements.
600 */
601 static __attribute__ ((always_inline))
mec_espi_smvw_index_set(ESPI_SMVW_REG * p,uint8_t host_vw_index)602 inline void mec_espi_smvw_index_set(ESPI_SMVW_REG * p, uint8_t host_vw_index)
603 {
604 p->INDEX = host_vw_index;
605 }
606
607 /*
608 * Set the Host VWire index this SMVW implements.
609 */
610 static __attribute__ ((always_inline))
mec_espi_smvw_index_get(ESPI_SMVW_REG * p)611 inline uint8_t mec_espi_smvw_index_get(ESPI_SMVW_REG * p)
612 {
613 return p->INDEX;
614 }
615
616 /*
617 * This functions sets the two STOM fields in a SMVW
618 * Reset source
619 * Reset value of SRC[3:0]
620 */
621 static __attribute__ ((always_inline))
622 inline void
mec_espi_msvw_stom_set(ESPI_SMVW_REG * p,enum espi_vw_rst_src rst_src,uint8_t rst_bitmap)623 mec_espi_msvw_stom_set(ESPI_SMVW_REG * p, enum espi_vw_rst_src rst_src,
624 uint8_t rst_bitmap)
625 {
626 p->STOM = (rst_src & 0x03u) | ((rst_bitmap & 0x0fu) << 4);
627 }
628
629 /*
630 * Return SMVW source change bitmap
631 * b[3:0] = SRC[3:0] change where 1=change, 0=no change
632 * A SRC change bit == 1 indicates the EC has updated the corresponding
633 * SRC bit with a new value. HW will transmit all 4 SMVW bits when the
634 * eSPI bus becomes available. Once transmitted HW will clear SRC CHG bit(s).
635 */
636 static __attribute__ ((always_inline))
mec_espi_smvw_get_chg(ESPI_SMVW_REG * p)637 inline uint8_t mec_espi_smvw_get_chg(ESPI_SMVW_REG * p)
638 {
639 return p->SRC_CHG;
640 }
641
642 /*
643 * Return 32-bit unsigned word containing all 4 SMVW SRC bits in
644 * bit positions 0, 8, 16, and 24.
645 */
646 static __attribute__ ((always_inline))
mec_espi_smvw_get_all(ESPI_SMVW_REG * p)647 inline uint32_t mec_espi_smvw_get_all(ESPI_SMVW_REG * p)
648 {
649 return p->SRC;
650 }
651
652 /*
653 * Write 32-bit unsigned word containing all 4 SMVW SRC bits in
654 * bit positions 0, 8, 16, and 24.
655 */
656 static __attribute__ ((always_inline))
mec_espi_smvw_set_all(ESPI_SMVW_REG * p,uint32_t new_srcs)657 inline void mec_espi_smvw_set_all(ESPI_SMVW_REG * p, uint32_t new_srcs)
658 {
659 p->SRC = new_srcs;
660 }
661
662 /*
663 * Write 32-bit unsigned word containing all 4 SMVW SRC bits in
664 * bit positions 0, 8, 16, and 24 from bitmap where
665 * bitmap[0] -> SRC bit[0]
666 * bitmap[1] -> SRC bit[8]
667 * bitmap[2] -> SRC bit[16]
668 * bitmap[3] -> SRC bit[24]
669 */
670 static __attribute__ ((always_inline))
mec_espi_smvw_set_all_bitmap(ESPI_SMVW_REG * p,uint8_t src_bitmap)671 inline void mec_espi_smvw_set_all_bitmap(ESPI_SMVW_REG * p, uint8_t src_bitmap)
672 {
673 uint32_t i, srcs;
674
675 srcs = 0u;
676 for (i = 0; i < 4u; i++) {
677 if (src_bitmap & (1u << i)) {
678 srcs |= (1u << (i << 3));
679 }
680 }
681
682 p->SRC = srcs;
683 }
684
685 /*
686 * Get the specified Device-to-Host VWire state.
687 * SMVW.SRC is a 32-bit register located at bits[63:32] where the four
688 * VWire's it controls are located on byte boundaries.
689 * Param p is a pointer to the 64-bit SMVW register.
690 * Param src is in [0:3] specifying one of the four VWire's.
691 * Param src_val is the new VWire state.
692 * SRC member is the 32-bit word at bits[63:32] in the SMVW structure.
693 * SRC[3:0] = SRC0 VWire state
694 * SRC[11:8] = SRC1 VWire state
695 * SRC[19:16] = SRC1 VWire state
696 * SRC[27:24] = SRC1 VWire state
697 */
698 static __attribute__ ((always_inline))
mec_espi_smvw_get(ESPI_SMVW_REG * p,enum espi_smvw_src src)699 inline uint8_t mec_espi_smvw_get(ESPI_SMVW_REG * p, enum espi_smvw_src src)
700 {
701 return (uint8_t) ((p->SRC >> (src << 3)) & 0x01u);
702 }
703
704 /*
705 * Set the specified Device-to-Host VWire state.
706 * SMVW.SRC is a 32-bit register located at bits[63:32] where the four
707 * VWire's it controls are located on byte boundaries.
708 * Param p is a pointer to the 64-bit SMVW register.
709 * Param src is in [0:3] specifying one of the four VWire's.
710 * Param src_val is the new VWire state.
711 * SRC member is the 32-bit word at bits[63:32] in the SMVW structure.
712 * SRC[3:0] = SRC0 VWire state
713 * SRC[11:8] = SRC1 VWire state
714 * SRC[19:16] = SRC1 VWire state
715 * SRC[27:24] = SRC1 VWire state
716 * The SMVW registers are byte accessible allowing us to avoid a
717 * read-modify-write.
718 */
719 static __attribute__ ((always_inline))
720 inline void
mec_espi_smvw_set(ESPI_SMVW_REG * p,enum espi_smvw_src src,uint8_t new_val)721 mec_espi_smvw_set(ESPI_SMVW_REG * p, enum espi_smvw_src src, uint8_t new_val)
722 {
723 volatile uint8_t *p8 = (volatile uint8_t *)&p->SRC;
724
725 *(p8 + (uintptr_t) src) = new_val;
726 }
727
728 #endif /* #ifndef _ESPI_VW_H */
729 /* end espi_vw.h */
730 /** @}
731 */
732
