1 /* 2 * Copyright (c) 2020 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 /** 8 * @file Header with definitions for MCHP eSPI SAF registers 9 */ 10 11 #ifndef ESPI_SAF_H_ 12 #define ESPI_SAF_H_ 13 14 #include <stdint.h> 15 16 #define MCHP_ESPI_SAF_BASE_ADDR 0x40008000 17 #define MCHP_ESPI_SAF_COMM_BASE_ADDR 0x40071000 18 19 #define MCHP_ESPI_SAF_CS_MAX 2 20 21 /* Three TAG Map registers */ 22 #define MCHP_ESPI_SAF_TAGMAP_MAX 3 23 /* 17 protection regions */ 24 #define MCHP_ESPI_SAF_PR_MAX 17 25 26 /* 27 * SAF SPI Opcoded and indices specifying start QMSPI descriptor for 28 * each opcode. There is one register group per flash device. 29 * OPA: read status1, resume, suspend, write enable 30 * OPB: erase 4KB, erase 32KB, erase 64KB, page program 31 * OPC: Fast Read Quad or Dual, N/A, continuous mode byte, read status 2 32 * OP_DESCR: contains QMSPI descriptor indices for various opcode fields. 33 */ 34 struct mchp_espi_saf_op { 35 volatile uint32_t OPA; 36 volatile uint32_t OPB; 37 volatile uint32_t OPC; 38 volatile uint32_t OP_DESCR; 39 }; 40 41 /* 42 * SAF protection regions contain 4 32-bit registers: 43 * Start address in 4KB units. 44 * Limit address in 4KB units. 45 * Write-erase eSPI Master bit-map. 46 * Read access eSPI Master bit-map. 47 */ 48 struct mchp_espi_saf_pr { 49 volatile uint32_t START; 50 volatile uint32_t LIMIT; 51 volatile uint32_t WEBM; 52 volatile uint32_t RDBM; 53 }; 54 55 /* 56 * SAF configuration and control registers 57 */ 58 struct mchp_espi_saf { 59 uint32_t RSVD1[6]; 60 volatile uint32_t SAF_ECP_CMD; 61 volatile uint32_t SAF_ECP_FLAR; 62 volatile uint32_t SAF_ECP_START; 63 volatile uint32_t SAF_ECP_BFAR; 64 volatile uint32_t SAF_ECP_STATUS; 65 volatile uint32_t SAF_ECP_INTEN; 66 volatile uint32_t SAF_FL_CFG_SIZE_LIM; 67 volatile uint32_t SAF_FL_CFG_THRH; 68 volatile uint32_t SAF_FL_CFG_MISC; 69 volatile uint32_t SAF_ESPI_MON_STATUS; 70 volatile uint32_t SAF_ESPI_MON_INTEN; 71 volatile uint32_t SAF_ECP_BUSY; 72 uint32_t RSVD2[1]; 73 struct mchp_espi_saf_op SAF_CS_OP[MCHP_ESPI_SAF_CS_MAX]; 74 volatile uint32_t SAF_FL_CFG_GEN_DESCR; 75 volatile uint32_t SAF_PROT_LOCK; 76 volatile uint32_t SAF_PROT_DIRTY; 77 volatile uint32_t SAF_TAG_MAP[MCHP_ESPI_SAF_TAGMAP_MAX]; 78 struct mchp_espi_saf_pr SAF_PROT_RG[MCHP_ESPI_SAF_PR_MAX]; 79 volatile uint32_t SAF_POLL_TMOUT; 80 volatile uint32_t SAF_POLL_INTRVL; 81 volatile uint32_t SAF_SUS_RSM_INTRVL; 82 volatile uint32_t SAF_CONSEC_RD_TMOUT; 83 volatile uint16_t SAF_CS0_CFG_P2M; 84 volatile uint16_t SAF_CS1_CFG_P2M; 85 volatile uint32_t SAF_FL_CFG_SPM; 86 volatile uint32_t SAF_SUS_CHK_DLY; 87 volatile uint16_t SAF_CS0_CM_PRF; 88 volatile uint16_t SAF_CS1_CM_PRF; 89 volatile uint32_t SAF_DNX_PROT_BYP; 90 }; 91 typedef struct mchp_espi_saf MCHP_SAF_HW_REGS; 92 93 #define MCHP_SAF_FL_CM_PRF_CS0_OFS 0x1b0 94 #define MCHP_SAF_FL_CM_PRF_CS1_OFS 0x1b2 95 96 97 #define MCHP_ESPI_SAF_BASE 0x40008000 98 #define MCHP_ESPI_SAF_COMM_BASE 0x40071000 99 #define MCHP_ESPI_SAF_COMM_MODE_OFS 0x2b8 100 #define MCHP_ESPI_SAF_COMM_MODE_ADDR (MCHP_ESPI_SAF_COMM_BASE_ADDR + \ 101 MCHP_ESPI_SAF_COMM_MODE_OFS) 102 103 /* SAF Protection region described by 4 32-bit registers. 17 regions */ 104 #define MCHP_ESPI_SAF_PROT_MAX 17 105 106 /* SAF register structure pointer */ 107 #define MCHP_SAF_REGS ((MCHP_SAF_HW_REGS *)(MCHP_ESPI_SAF_BASE_ADDR)) 108 109 /* SAF Communication Mode register */ 110 #define MCHP_SAF_COMM_MODE_REG \ 111 *(volatile uint32_t *)(MCHP_ESPI_SAF_COMM_MODE_ADDR) 112 113 /* 114 * Interrupt connections 115 * HW bug: SAF interrupts do not have direct NVIC connections. 116 */ 117 #define MCHP_SAF_GIRQ 18 118 #define MCHP_SAF_GIRQ_ECP_DONE_POS 9 119 #define MCHP_SAF_GIRQ_ERROR_POS 10 120 #define MCHP_SAF_GIRQ_ECP_DONE_BIT BIT(9) 121 #define MCHP_SAF_GIRQ_ERROR_BIT BIT(10) 122 123 124 /* Register bit definitions */ 125 126 /* SAF EC Portal Command register */ 127 #define MCHP_SAF_ECP_CMD_OFS 0x18 128 #define MCHP_SAF_ECP_CMD_MASK 0xff00ffff 129 #define MCHP_SAF_ECP_CMD_PUT_POS 0 130 #define MCHP_SAF_ECP_CMD_PUT_MASK 0xff 131 #define MCHP_SAF_ECP_CMD_PUT_FLASH_NP 0x0a 132 #define MCHP_SAF_ECP_CMD_CTYPE_POS 8 133 #define MCHP_SAF_ECP_CMD_CTYPE_READ0 0x00 134 #define MCHP_SAF_ECP_CMD_CTYPE_WRITE0 0x01 135 #define MCHP_SAF_ECP_CMD_CTYPE_ERASE0 0x02 136 #define MCHP_SAF_ECP_CMD_CTYPE_MAX0 0x03 137 #define MCHP_SAF_ECP_CMD_CTYPE_MASK (0xff << MCHP_SAF_ECP_CMD_CTYPE_POS) 138 #define MCHP_SAF_ECP_CMD_CTYPE_READ (0x00 << MCHP_SAF_ECP_CMD_CTYPE_POS) 139 #define MCHP_SAF_ECP_CMD_CTYPE_WRITE (0x01 << MCHP_SAF_ECP_CMD_CTYPE_POS) 140 #define MCHP_SAF_ECP_CMD_CTYPE_ERASE (0x02 << MCHP_SAF_ECP_CMD_CTYPE_POS) 141 #define MCHP_SAF_ECP_CMD_LEN_POS 24 142 #define MCHP_SAF_ECP_CMD_LEN_MASK0 0xff 143 #define MCHP_SAF_ECP_CMD_LEN_MASK (0xff << MCHP_SAF_ECP_CMD_LEN_POS) 144 /* Read/Write request size (1 <= reqlen <= 64) bytes */ 145 #define MCHP_SAF_ECP_CMD_RW_LEN_MIN 1 146 #define MCHP_SAF_ECP_CMD_RW_LEN_MAX 64 147 /* Only three erase sizes are supported encoded as */ 148 #define MCHP_SAF_ECP_CMD_ERASE_4K (0x00 << MCHP_SAF_ECP_CMD_LEN_POS) 149 #define MCHP_SAF_ECP_CMD_ERASE_32K (0x01 << MCHP_SAF_ECP_CMD_LEN_POS) 150 #define MCHP_SAF_ECP_CMD_ERASE_64K (0x02 << MCHP_SAF_ECP_CMD_LEN_POS) 151 152 /* SAF EC Portal Flash Address register */ 153 #define MCHP_SAF_ECP_FLAR_OFS 0x1c 154 #define MCHP_SAF_ECP_FLAR_MASK 0xffffffff 155 156 /* SAF EC Portal Start register */ 157 #define MCHP_SAF_ECP_START_OFS 0x20 158 #define MCHP_SAF_ECP_START_MASK 0x01 159 #define MCHP_SAF_ECP_START BIT(0) 160 161 /* SAF EC Portal Buffer Address register */ 162 #define MCHP_SAF_ECP_BFAR_OFS 0x24 163 #define MCHP_SAF_ECP_BFAR_MASK 0xfffffffc 164 165 /* SAF EC Portal Status register */ 166 #define MCHP_SAF_ECP_STS_OFS 0x28 167 #define MCHP_SAF_ECP_STS_MASK 0x1ff 168 #define MCHP_SAF_ECP_STS_ERR_MASK 0x1fc 169 #define MCHP_SAF_ECP_STS_DONE BIT(0) 170 #define MCHP_SAF_ECP_STS_DONE_TST BIT(1) 171 #define MCHP_SAF_ECP_STS_TMOUT BIT(2) 172 #define MCHP_SAF_ECP_STS_OOR BIT(3) 173 #define MCHP_SAF_ECP_STS_AV BIT(4) 174 #define MCHP_SAF_ECP_STS_BND_4K BIT(5) 175 #define MCHP_SAF_ECP_STS_ERSZ BIT(6) 176 #define MCHP_SAF_ECP_STS_ST_OVFL BIT(6) 177 #define MCHP_SAF_ECP_STS_BAD_REQ BIT(8) 178 179 /* SAF EC Portal Interrupt Enable register */ 180 #define MCHP_SAF_ECP_INTEN_OFS 0x2c 181 #define MCHP_SAF_ECP_INTEN_MASK 0x01 182 #define MCHP_SAF_ECP_INTEN_DONE BIT(0) 183 184 /* SAF Flash Configuratin Size Limit register */ 185 #define MCHP_SAF_FL_CFG_SIZE_LIM_OFS 0x30 186 #define MCHP_SAF_FL_CFG_SIZE_LIM_MASK 0xffffffff 187 188 /* SAF Flash Configuration Threshold register */ 189 #define MCHP_SAF_FL_CFG_THRH_OFS 0x34 190 #define MCHP_SAF_FL_CFG_THRH_MASK 0xffffffff 191 192 /* SAF Flash Configuration Miscellaneous register */ 193 #define MCHP_SAF_FL_CFG_MISC_OFS 0x38 194 #define MCHP_SAF_FL_CFG_MISC_MASK 0x000030f3 195 #define MCHP_SAF_FL_CFG_MISC_PFOE_MASK 0x03 196 #define MCHP_SAF_FL_CFG_MISC_PFOE_DFLT 0x00 197 #define MCHP_SAF_FL_CFG_MISC_PFOE_EXP 0x03 198 #define MCHP_SAF_FL_CFG_MISC_CS0_4BM BIT(4) 199 #define MCHP_SAF_FL_CFG_MISC_CS1_4BM BIT(5) 200 #define MCHP_SAF_FL_CFG_MISC_CS0_CPE BIT(6) 201 #define MCHP_SAF_FL_CFG_MISC_CS1_CPE BIT(7) 202 #define MCHP_SAF_FL_CFG_MISC_SAF_EN BIT(12) 203 #define MCHP_SAF_FL_CFG_MISC_SAF_LOCK BIT(13) 204 205 /* SAF eSPI Monitor Status register */ 206 #define MCHP_SAF_ESPI_MON_STATUS_OFS 0x3c 207 #define MCHP_SAF_ESPI_MON_STATUS_MASK 0x1f 208 #define MCHP_SAF_ESPI_MON_STS_TMOUT BIT(0) 209 #define MCHP_SAF_ESPI_MON_STS_OOR BIT(1) 210 #define MCHP_SAF_ESPI_MON_STS_AV BIT(2) 211 #define MCHP_SAF_ESPI_MON_STS_BND_4K BIT(3) 212 #define MCHP_SAF_ESPI_MON_STS_ERSZ BIT(4) 213 214 /* SAF eSPI Monitor Interrupt Enable register */ 215 #define MCHP_SAF_ESPI_MON_INTEN_OFS 0x40 216 #define MCHP_SAF_ESPI_MON_INTEN_MASK 0x1f 217 #define MCHP_SAF_ESPI_MON_INTEN_TMOUT BIT(0) 218 #define MCHP_SAF_ESPI_MON_INTEN_OOR BIT(1) 219 #define MCHP_SAF_ESPI_MON_INTEN_AV BIT(2) 220 #define MCHP_SAF_ESPI_MON_INTEN_BND_4K BIT(3) 221 #define MCHP_SAF_ESPI_MON_INTEN_ERSZ BIT(4) 222 223 /* SAF EC Portal Busy register */ 224 #define MCHP_SAF_ECP_BUSY_OFS 0x44 225 #define MCHP_SAF_ECP_BUSY_MASK 0x01 226 #define MCHP_SAF_ECP_BUSY BIT(0) 227 228 /* SAF CS0/CS1 Opcode A registers */ 229 #define MCHP_SAF_CS0_OPA_OFS 0x4c 230 #define MCHP_SAF_CS1_OPA_OFS 0x5c 231 #define MCHP_SAF_CS_OPA_MASK 0xffffffff 232 #define MCHP_SAF_CS_OPA_WE_POS 0 233 #define MCHP_SAF_CS_OPA_WE_MASK 0xff 234 #define MCHP_SAF_CS_OPA_SUS_POS 8 235 #define MCHP_SAF_CS_OPA_SUS_MASK (0xff << MCHP_SAF_CS_OPA_SUS_POS) 236 #define MCHP_SAF_CS_OPA_RSM_POS 16 237 #define MCHP_SAF_CS_OPA_RSM_MASK (0xff << MCHP_SAF_CS_OPA_RSM_POS) 238 #define MCHP_SAF_CS_OPA_POLL1_POS 24 239 #define MCHP_SAF_CS_OPA_POLL1_MASK (0xff << MCHP_SAF_CS_OPA_POLL1_POS) 240 241 /* SAF CS0/CS1 Opcode B registers */ 242 #define MCHP_SAF_CS0_OPB_OFS 0x50 243 #define MCHP_SAF_CS1_OPB_OFS 0x60 244 #define MCHP_SAF_CS_OPB_OFS 0xffffffff 245 #define MCHP_SAF_CS_OPB_ER0_POS 0 246 #define MCHP_SAF_CS_OPB_ER0_MASK 0xff 247 #define MCHP_SAF_CS_OPB_ER1_POS 8 248 #define MCHP_SAF_CS_OPB_ER1_MASK (0xff << MCHP_SAF_CS_OPB_ER1_POS) 249 #define MCHP_SAF_CS_OPB_ER2_POS 16 250 #define MCHP_SAF_CS_OPB_ER2_MASK (0xff << MCHP_SAF_CS_OPB_ER2_POS) 251 #define MCHP_SAF_CS_OPB_PGM_POS 24 252 #define MCHP_SAF_CS_OPB_PGM_MASK (0xff << MCHP_SAF_CS_OPB_PGM_POS) 253 254 /* SAF CS0/CS1 Opcode C registers */ 255 #define MCHP_SAF_CS0_OPC_OFS 0x54 256 #define MCHP_SAF_CS1_OPC_OFS 0x64 257 #define MCHP_SAF_CS_OPC_MASK 0xffffffff 258 #define MCHP_SAF_CS_OPC_RD_POS 0 259 #define MCHP_SAF_CS_OPC_RD_MASK 0xff 260 #define MCHP_SAF_CS_OPC_MNC_POS 8 261 #define MCHP_SAF_CS_OPC_MNC_MASK (0xff << MCHP_SAF_CS_OPC_MN_POS) 262 #define MCHP_SAF_CS_OPC_MC_POS 16 263 #define MCHP_SAF_CS_OPC_MC_MASK (0xff << MCHP_SAF_CS_OPC_MC_POS) 264 #define MCHP_SAF_CS_OPC_POLL2_POS 24 265 #define MCHP_SAF_CS_OPC_POLL2_MASK (0xff << MCHP_SAF_CS_OPC_POLL2_POS) 266 267 /* SAF CS0/CS1 registers */ 268 #define MCHP_SAF_CS0_DESCR_OFS 0x58 269 #define MCHP_SAF_CS1_DESCR_OFS 0x68 270 #define MCHP_SAF_CS_DESCR_MASK 0x0000ff0f 271 #define MCHP_SAF_CS_DESCR_ENTC_POS 0 272 #define MCHP_SAF_CS_DESCR_ENTC_MASK 0x0f 273 #define MCHP_SAF_CS_DESCR_RDC_POS 8 274 #define MCHP_SAF_CS_DESCR_RDC_MASK (0x0f << MCHP_SAF_CS_DESCR_RDC_POS) 275 #define MCHP_SAF_CS_DESCR_SZC_POS 12 276 #define MCHP_SAF_CS_DESCR_SZC_MASK (0x0f << MCHP_SAF_CS_DESCR_SZC_POS) 277 278 /* SAF Flash Configuration General Descriptors register */ 279 #define MCHP_SAF_FL_CFG_GEN_DESCR_OFS 0x6c 280 #define MCHP_SAF_FL_CFG_GEN_DESCR_MASK 0x0000ff0f 281 /* value for standard 16 descriptor programming */ 282 #define MCHP_SAF_FL_CFG_GEN_DESCR_STD 0x0000ee0c 283 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_POS 0 284 #define MCHP_SAF_FL_CFG_GEN_DESCR_EXC_MASK 0x0f 285 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS 8 286 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_MASK \ 287 (0x0f << MCHP_SAF_FL_CFG_GEN_DESCR_POLL1_POS) 288 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS 12 289 #define MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_MASK \ 290 (0x0f << MCHP_SAF_FL_CFG_GEN_DESCR_POLL2_POS) 291 292 /* SAF Protection Lock register */ 293 #define MCHP_SAF_PROT_LOCK_OFS 0x70 294 #define MCHP_SAF_PROT_LOCK_MASK 0x1ffff 295 #define MCHP_SAF_PROT_LOCK0 BIT(0) 296 #define MCHP_SAF_PROT_LOCK1 BIT(1) 297 #define MCHP_SAF_PROT_LOCK2 BIT(2) 298 #define MCHP_SAF_PROT_LOCK3 BIT(3) 299 #define MCHP_SAF_PROT_LOCK4 BIT(4) 300 #define MCHP_SAF_PROT_LOCK5 BIT(5) 301 #define MCHP_SAF_PROT_LOCK6 BIT(6) 302 #define MCHP_SAF_PROT_LOCK7 BIT(7) 303 #define MCHP_SAF_PROT_LOCK8 BIT(8) 304 #define MCHP_SAF_PROT_LOCK9 BIT(9) 305 #define MCHP_SAF_PROT_LOCK10 BIT(10) 306 #define MCHP_SAF_PROT_LOCK11 BIT(11) 307 #define MCHP_SAF_PROT_LOCK12 BIT(12) 308 #define MCHP_SAF_PROT_LOCK13 BIT(13) 309 #define MCHP_SAF_PROT_LOCK14 BIT(14) 310 #define MCHP_SAF_PROT_LOCK15 BIT(15) 311 #define MCHP_SAF_PROT_LOCK16 BIT(16) 312 313 /* SAF Protection Dirty register */ 314 #define MCHP_SAF_PROT_DIRTY_OFS 0x74 315 #define MCHP_SAF_PROT_DIRTY_MASK 0x00fff 316 #define MCHP_SAF_PROT_DIRTY0 BIT(0) 317 #define MCHP_SAF_PROT_DIRTY1 BIT(1) 318 #define MCHP_SAF_PROT_DIRTY2 BIT(2) 319 #define MCHP_SAF_PROT_DIRTY3 BIT(3) 320 #define MCHP_SAF_PROT_DIRTY4 BIT(4) 321 #define MCHP_SAF_PROT_DIRTY5 BIT(5) 322 #define MCHP_SAF_PROT_DIRTY6 BIT(6) 323 #define MCHP_SAF_PROT_DIRTY7 BIT(7) 324 #define MCHP_SAF_PROT_DIRTY8 BIT(8) 325 #define MCHP_SAF_PROT_DIRTY9 BIT(9) 326 #define MCHP_SAF_PROT_DIRTY10 BIT(10) 327 #define MCHP_SAF_PROT_DIRTY11 BIT(11) 328 329 /* SAF Tag Map 0 register */ 330 #define MCHP_SAF_TAG_MAP0_OFS 0x78 331 #define MCHP_SAF_TAG_MAP0_MASK 0x77777777 332 #define MCHP_SAF_TAG_MAP0_DFLT 0x23221100 333 #define MCHP_SAF_TAG_MAP0_STM0_POS 0 334 #define MCHP_SAF_TAG_MAP0_STM0_MASK 0x07 335 #define MCHP_SAF_TAG_MAP0_STM1_POS 4 336 #define MCHP_SAF_TAG_MAP0_STM1_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM1_POS) 337 #define MCHP_SAF_TAG_MAP0_STM2_POS 8 338 #define MCHP_SAF_TAG_MAP0_STM2_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM2_POS) 339 #define MCHP_SAF_TAG_MAP0_STM3_POS 12 340 #define MCHP_SAF_TAG_MAP0_STM3_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM3_POS) 341 #define MCHP_SAF_TAG_MAP0_STM4_POS 16 342 #define MCHP_SAF_TAG_MAP0_STM4_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM4_POS) 343 #define MCHP_SAF_TAG_MAP0_STM5_POS 20 344 #define MCHP_SAF_TAG_MAP0_STM5_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM5_POS) 345 #define MCHP_SAF_TAG_MAP0_STM6_POS 24 346 #define MCHP_SAF_TAG_MAP0_STM6_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM6_POS) 347 #define MCHP_SAF_TAG_MAP0_STM7_POS 28 348 #define MCHP_SAF_TAG_MAP0_STM7_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM7_POS) 349 350 /* SAF Tag Map 1 register */ 351 #define MCHP_SAF_TAG_MAP1_OFS 0x7c 352 #define MCHP_SAF_TAG_MAP1_MASK 0x77777777 353 #define MCHP_SAF_TAG_MAP1_DFLT 0x77677767 354 #define MCHP_SAF_TAG_MAP1_STM8_POS 0 355 #define MCHP_SAF_TAG_MAP1_STM8_MASK 0x07 356 #define MCHP_SAF_TAG_MAP1_STM9_POS 4 357 #define MCHP_SAF_TAG_MAP1_STM9_MASK (0x07 << MCHP_SAF_TAG_MAP1_STM9_POS) 358 #define MCHP_SAF_TAG_MAP1_STMA_POS 8 359 #define MCHP_SAF_TAG_MAP1_STMA_MASK (0x07 << MCHP_SAF_TAG_MAP1_STMA_POS) 360 #define MCHP_SAF_TAG_MAP1_STMB_POS 12 361 #define MCHP_SAF_TAG_MAP1_STMB_MASK (0x07 << MCHP_SAF_TAG_MAP1_STMB_POS) 362 #define MCHP_SAF_TAG_MAP1_STMC_POS 16 363 #define MCHP_SAF_TAG_MAP1_STMC_MASK (0x07 << MCHP_SAF_TAG_MAP1_STMC_POS) 364 #define MCHP_SAF_TAG_MAP1_STMD_POS 20 365 #define MCHP_SAF_TAG_MAP1_STMD_MASK (0x07 << MCHP_SAF_TAG_MAP1_STMD_POS) 366 #define MCHP_SAF_TAG_MAP1_STME_POS 24 367 #define MCHP_SAF_TAG_MAP1_STME_MASK (0x07 << MCHP_SAF_TAG_MAP1_STME_POS) 368 #define MCHP_SAF_TAG_MAP1_STMF_POS 28 369 #define MCHP_SAF_TAG_MAP1_STMF_MASK (0x07 << MCHP_SAF_TAG_MAP1_STMF_POS) 370 371 /* SAF Tag Map 2 register */ 372 #define MCHP_SAF_TAG_MAP2_OFS 0x80 373 #define MCHP_SAF_TAG_MAP2_MASK 0x80000007 374 #define MCHP_SAF_TAG_MAP2_DFLT 0x00000005 375 #define MCHP_SAF_TAG_MAP2_SM_EC_POS 0 376 #define MCHP_SAF_TAG_MAP2_SM_EC_MASK 0x07 377 #define MCHP_SAF_TAG_MAP2_LOCK_POS 31 378 #define MCHP_SAF_TAG_MAP2_LOCK BIT(31) 379 380 /* SAF Protection Region Start registers */ 381 #define MCHP_SAF_PROT_RG0_START_OFS 0x84 382 #define MCHP_SAF_PROT_RG1_START_OFS 0x94 383 #define MCHP_SAF_PROT_RG2_START_OFS 0xa4 384 #define MCHP_SAF_PROT_RG3_START_OFS 0xb4 385 #define MCHP_SAF_PROT_RG4_START_OFS 0xc4 386 #define MCHP_SAF_PROT_RG5_START_OFS 0xd4 387 #define MCHP_SAF_PROT_RG6_START_OFS 0xe4 388 #define MCHP_SAF_PROT_RG7_START_OFS 0xf4 389 #define MCHP_SAF_PROT_RG8_START_OFS 0x104 390 #define MCHP_SAF_PROT_RG9_START_OFS 0x114 391 #define MCHP_SAF_PROT_RG10_START_OFS 0x124 392 #define MCHP_SAF_PROT_RG11_START_OFS 0x134 393 #define MCHP_SAF_PROT_RG12_START_OFS 0x144 394 #define MCHP_SAF_PROT_RG13_START_OFS 0x154 395 #define MCHP_SAF_PROT_RG14_START_OFS 0x164 396 #define MCHP_SAF_PROT_RG15_START_OFS 0x174 397 #define MCHP_SAF_PROT_RG16_START_OFS 0x184 398 #define MCHP_SAF_PROT_RG_START_MASK 0xfffff 399 #define MCHP_SAF_PROT_RG_START_DFLT 0x07fff 400 401 /* SAF Protection Region Limit registers */ 402 #define MCHP_SAF_PROT_RG0_LIMIT_OFS 0x88 403 #define MCHP_SAF_PROT_RG1_LIMIT_OFS 0x98 404 #define MCHP_SAF_PROT_RG2_LIMIT_OFS 0xa8 405 #define MCHP_SAF_PROT_RG3_LIMIT_OFS 0xb8 406 #define MCHP_SAF_PROT_RG4_LIMIT_OFS 0xc8 407 #define MCHP_SAF_PROT_RG5_LIMIT_OFS 0xd8 408 #define MCHP_SAF_PROT_RG6_LIMIT_OFS 0xe8 409 #define MCHP_SAF_PROT_RG7_LIMIT_OFS 0xf8 410 #define MCHP_SAF_PROT_RG8_LIMIT_OFS 0x108 411 #define MCHP_SAF_PROT_RG9_LIMIT_OFS 0x118 412 #define MCHP_SAF_PROT_RG10_LIMIT_OFS 0x128 413 #define MCHP_SAF_PROT_RG11_LIMIT_OFS 0x138 414 #define MCHP_SAF_PROT_RG12_LIMIT_OFS 0x148 415 #define MCHP_SAF_PROT_RG13_LIMIT_OFS 0x158 416 #define MCHP_SAF_PROT_RG14_LIMIT_OFS 0x168 417 #define MCHP_SAF_PROT_RG15_LIMIT_OFS 0x178 418 #define MCHP_SAF_PROT_RG16_LIMIT_OFS 0x188 419 #define MCHP_SAF_PROT_RG_LIMIT_MASK 0xfffff 420 #define MCHP_SAF_PROT_RG_LIMIT_DFLT 0 421 422 /* SAF Protection Region Write Bitmap registers */ 423 #define MCHP_SAF_PROT_RG0_WBM_OFS 0x8c 424 #define MCHP_SAF_PROT_RG1_WBM_OFS 0x9c 425 #define MCHP_SAF_PROT_RG2_WBM_OFS 0xac 426 #define MCHP_SAF_PROT_RG3_WBM_OFS 0xbc 427 #define MCHP_SAF_PROT_RG4_WBM_OFS 0xcc 428 #define MCHP_SAF_PROT_RG5_WBM_OFS 0xdc 429 #define MCHP_SAF_PROT_RG6_WBM_OFS 0xec 430 #define MCHP_SAF_PROT_RG7_WBM_OFS 0xfc 431 #define MCHP_SAF_PROT_RG8_WBM_OFS 0x10c 432 #define MCHP_SAF_PROT_RG9_WBM_OFS 0x11c 433 #define MCHP_SAF_PROT_RG10_WBM_OFS 0x12c 434 #define MCHP_SAF_PROT_RG11_WBM_OFS 0x13c 435 #define MCHP_SAF_PROT_RG12_WBM_OFS 0x14c 436 #define MCHP_SAF_PROT_RG13_WBM_OFS 0x15c 437 #define MCHP_SAF_PROT_RG14_WBM_OFS 0x16c 438 #define MCHP_SAF_PROT_RG15_WBM_OFS 0x17c 439 #define MCHP_SAF_PROT_RG16_WBM_OFS 0x18c 440 #define MCHP_SAF_PROT_RG_WBM_MASK 0xff 441 #define MCHP_SAF_PROT_RG_WBM0 BIT(0) 442 #define MCHP_SAF_PROT_RG_WBM1 BIT(1) 443 #define MCHP_SAF_PROT_RG_WBM2 BIT(2) 444 #define MCHP_SAF_PROT_RG_WBM3 BIT(3) 445 #define MCHP_SAF_PROT_RG_WBM4 BIT(4) 446 #define MCHP_SAF_PROT_RG_WBM5 BIT(5) 447 #define MCHP_SAF_PROT_RG_WBM6 BIT(6) 448 #define MCHP_SAF_PROT_RG_WBM7 BIT(7) 449 450 /* SAF Protection Region Read Bitmap registers */ 451 #define MCHP_SAF_PROT_RG0_RBM_OFS 0x90 452 #define MCHP_SAF_PROT_RG1_RBM_OFS 0xa0 453 #define MCHP_SAF_PROT_RG2_RBM_OFS 0xb0 454 #define MCHP_SAF_PROT_RG3_RBM_OFS 0xc0 455 #define MCHP_SAF_PROT_RG4_RBM_OFS 0xd0 456 #define MCHP_SAF_PROT_RG5_RBM_OFS 0xe0 457 #define MCHP_SAF_PROT_RG6_RBM_OFS 0xf0 458 #define MCHP_SAF_PROT_RG7_RBM_OFS 0x100 459 #define MCHP_SAF_PROT_RG8_RBM_OFS 0x110 460 #define MCHP_SAF_PROT_RG9_RBM_OFS 0x120 461 #define MCHP_SAF_PROT_RG10_RBM_OFS 0x130 462 #define MCHP_SAF_PROT_RG11_RBM_OFS 0x140 463 #define MCHP_SAF_PROT_RG12_RBM_OFS 0x150 464 #define MCHP_SAF_PROT_RG13_RBM_OFS 0x160 465 #define MCHP_SAF_PROT_RG14_RBM_OFS 0x170 466 #define MCHP_SAF_PROT_RG15_RBM_OFS 0x180 467 #define MCHP_SAF_PROT_RG16_RBM_OFS 0x190 468 #define MCHP_SAF_PROT_RG_RBM_MASK 0xff 469 #define MCHP_SAF_PROT_RG_RBM0 BIT(0) 470 #define MCHP_SAF_PROT_RG_RBM1 BIT(1) 471 #define MCHP_SAF_PROT_RG_RBM2 BIT(2) 472 #define MCHP_SAF_PROT_RG_RBM3 BIT(3) 473 #define MCHP_SAF_PROT_RG_RBM4 BIT(4) 474 #define MCHP_SAF_PROT_RG_RBM5 BIT(5) 475 #define MCHP_SAF_PROT_RG_RBM6 BIT(6) 476 #define MCHP_SAF_PROT_RG_RBM7 BIT(7) 477 478 /* SAF Poll Timeout register */ 479 #define MCHP_SAF_POLL_TMOUT_OFS 0x194 480 #define MCHP_SAF_POLL_TMOUT_MASK 0x3ffff 481 #define MCHP_SAF_POLL_TMOUT_5S 0x28000 482 483 /* SAF Poll Interval register */ 484 #define MCHP_SAF_POLL_INTRVL_OFS 0x198 485 #define MCHP_SAF_POLL_INTRVL_MASK 0xffff 486 487 /* SAF Suspend Resume Interval register */ 488 #define MCHP_SAF_SUS_RSM_INTRVL_OFS 0x19c 489 #define MCHP_SAF_SUS_RSM_INTRVL_MASK 0xffff 490 491 /* SAF Consecutive Read Timeout register */ 492 #define MCHP_SAF_CRD_TMOUT_OFS 0x1a0 493 #define MCHP_SAF_CRD_TMOUT_MASK 0xfffff 494 495 /* SAF Flash CS0/CS1 Configuration Poll2 Mask registers */ 496 #define MCHP_SAF_FL0_CFG_P2M_OFS 0x1a4 497 #define MCHP_SAF_FL1_CFG_P2M_OFS 0x1a6 498 #define MCHP_SAF_FL_CFG_P2M_MASK 0xffff 499 500 /* SAF Flash Configuration Special Mode register */ 501 #define MCHP_SAF_FL_CFG_SPM_OFS 0x1a8 502 #define MCHP_SAF_FL_CFG_SPM_MASK 0x01 503 #define MCHP_SAF_FL_CFG_SPM_DIS_SUSP BIT(0) 504 505 /* SAF Suspend Check Delay register */ 506 #define MCHP_SAF_SUS_CHK_DLY_OFS 0x1ac 507 #define MCHP_SAF_SUS_CHK_DLY_MASK 0xfffff 508 509 /* SAF Flash 0/1 Continuous Mode Prefix registers */ 510 #define MCHP_SAF_FL_CM_PRF_OFS 0x1b0 511 #define MCHP_SAF_FL_CM_PRF_MASK 0xffff 512 #define MCHP_SAF_FL_CM_PRF_CS_OP_POS 0 513 #define MCHP_SAF_FL_CM_PRF_CS_OP_MASK 0xff 514 #define MCHP_SAF_FL_CM_PRF_CS_DAT_POS 8 515 #define MCHP_SAF_FL_CM_PRF_CS_DAT_MASK \ 516 (0xff << MCHP_SAF_FL_CM_PRF_CS_DAT_POS) 517 518 /* SAF DnX Protection Bypass register */ 519 #define MCHP_SAF_DNX_PROT_BYP_OFS 0x1b4 520 #define MCHP_SAF_DNX_PROT_BYP_MASK 0xffffffff 521 522 /* SAF Communication Mode */ 523 #define MCHP_SAF_COMM_MODE_MASK 0x01 524 /* Allow pre-fetch from flash devices */ 525 #define MCHP_SAF_COMM_MODE_PF_EN BIT(0) 526 527 /* SAF TAG numbers[0:0xf] */ 528 #define MCHP_SAF_TAG_M0T0 0 529 #define MCHP_SAF_TAG_M0T1 1 530 #define MCHP_SAF_TAG_M1T0 2 531 #define MCHP_SAF_TAG_M1T1 3 532 #define MCHP_SAF_TAG_M2T0 4 533 #define MCHP_SAF_TAG_M2T1 5 534 #define MCHP_SAF_TAG_M3T0 6 535 #define MCHP_SAF_TAG_M2T2 7 536 #define MCHP_SAF_TAG_M6T0 9 537 #define MCHP_SAF_TAG_M6T1 0xd 538 #define MCHP_SAF_TAG_MAX 0x10 539 540 /* SAF Master numbers */ 541 #define MCHP_SAF_MSTR_CS_INIT 0 542 #define MCHP_SAF_MSTR_CPU 1 543 #define MCHP_SAF_MSTR_CS_ME 2 544 #define MCHP_SAF_MSTR_CS_LAN 3 545 #define MCHP_SAF_MSTR_UNUSED4 4 546 #define MCHP_SAF_MSTR_EC_FW 5 547 #define MCHP_SAF_MSTR_CS_IE 6 548 #define MCHP_SAF_MSTR_UNUSED7 7 549 #define MCHP_SAF_MSTR_MAX 8 550 #define MCHP_SAF_MSTR_ALL 0xff 551 552 553 #endif /* ESPI_SAF_H_ */ 554
