1 /**
2 *
3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries.
4 *
5 * \asf_license_start
6 *
7 * \page License
8 *
9 * SPDX-License-Identifier: Apache-2.0
10 *
11 * Licensed under the Apache License, Version 2.0 (the "License"); you may
12 * not use this file except in compliance with the License.
13 * You may obtain a copy of the Licence at
14 *
15 * http://www.apache.org/licenses/LICENSE-2.0
16 *
17 * Unless required by applicable law or agreed to in writing, software
18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
20 * See the License for the specific language governing permissions and
21 * limitations under the License.
22 *
23 * \asf_license_stop
24 *
25 */
26
27 /** @file espi_mem.h
28 *MEC1501 eSPI Memory Component definitions
29 */
30 /** @defgroup MEC1501 Peripherals eSPI MEM
31 */
32
33 #ifndef _ESPI_MEM_H
34 #define _ESPI_MEM_H
35
36 #include <stdint.h>
37 #include <stddef.h>
38
39 #include "regaccess.h"
40
41 /*------------------------------------------------------------------*/
42
43 /* =========================================================================*/
44 /* ================ eSPI Memory Component ================ */
45 /* =========================================================================*/
46
47 /*
48 * eSPI Memory Component Bus Master registers @ 0x400f3a00
49 */
50
51 /* BM_STS */
52 #define MCHP_ESPI_BM_STS_DONE_1_POS 0u
53 #define MCHP_ESPI_BM_STS_DONE_1 (1u << 0) /* RW1C */
54 #define MCHP_ESPI_BM_STS_BUSY_1_POS 1u
55 #define MCHP_ESPI_BM_STS_BUSY_1 (1u << 1) /* RO */
56 #define MCHP_ESPI_BM_STS_AB_EC_1_POS 2u
57 #define MCHP_ESPI_BM_STS_AB_EC_1 (1u << 2) /* RW1C */
58 #define MCHP_ESPI_BM_STS_AB_HOST_1_POS 3u
59 #define MCHP_ESPI_BM_STS_AB_HOST_1 (1u << 3) /* RW1C */
60 #define MCHP_ESPI_BM_STS_AB_CH2_1_POS 4u
61 #define MCHP_ESPI_BM_STS_CH2_AB_1 (1u << 4) /* RW1C */
62 #define MCHP_ESPI_BM_STS_OVFL_1_POS 5u
63 #define MCHP_ESPI_BM_STS_OVFL_1_CH2 (1u << 5) /* RW1C */
64 #define MCHP_ESPI_BM_STS_OVRUN_1_POS 6u
65 #define MCHP_ESPI_BM_STS_OVRUN_1_CH2 (1u << 6) /* RW1C */
66 #define MCHP_ESPI_BM_STS_INC_1_POS 7u
67 #define MCHP_ESPI_BM_STS_INC_1 (1u << 7) /* RW1C */
68 #define MCHP_ESPI_BM_STS_FAIL_1_POS 8u
69 #define MCHP_ESPI_BM_STS_FAIL_1 (1u << 8) /* RW1C */
70 #define MCHP_ESPI_BM_STS_IBERR_1_POS 9u
71 #define MCHP_ESPI_BM_STS_IBERR_1 (1u << 9) /* RW1C */
72 #define MCHP_ESPI_BM_STS_BADREQ_1_POS 11u
73 #define MCHP_ESPI_BM_STS_BADREQ_1 (1u << 11) /* RW1C */
74 #define MCHP_ESPI_BM_STS_DONE_2_POS 16u
75 #define MCHP_ESPI_BM_STS_DONE_2 (1u << 16) /* RW1C */
76 #define MCHP_ESPI_BM_STS_BUSY_2_POS 17u
77 #define MCHP_ESPI_BM_STS_BUSY_2 (1u << 17) /* RO */
78 #define MCHP_ESPI_BM_STS_AB_EC_2_POS 18u
79 #define MCHP_ESPI_BM_STS_AB_EC_2 (1u << 18) /* RW1C */
80 #define MCHP_ESPI_BM_STS_AB_HOST_2_POS 19u
81 #define MCHP_ESPI_BM_STS_AB_HOST_2 (1u << 19) /* RW1C */
82 #define MCHP_ESPI_BM_STS_AB_CH1_2_POS 20u
83 #define MCHP_ESPI_BM_STS_AB_CH1_2 (1u << 20) /* RW1C */
84 #define MCHP_ESPI_BM_STS_OVFL_2_POS 21u
85 #define MCHP_ESPI_BM_STS_OVFL_2_CH2 (1u << 21) /* RW1C */
86 #define MCHP_ESPI_BM_STS_OVRUN_2_POS 22u
87 #define MCHP_ESPI_BM_STS_OVRUN_CH2_2 (1u << 22) /* RW1C */
88 #define MCHP_ESPI_BM_STS_INC_2_POS 23u
89 #define MCHP_ESPI_BM_STS_INC_2 (1u << 23) /* RW1C */
90 #define MCHP_ESPI_BM_STS_FAIL_2_POS 24u
91 #define MCHP_ESPI_BM_STS_FAIL_2 (1u << 24) /* RW1C */
92 #define MCHP_ESPI_BM_STS_IBERR_2_POS 25u
93 #define MCHP_ESPI_BM_STS_IBERR_2 (1u << 25) /* RW1C */
94 #define MCHP_ESPI_BM_STS_BADREQ_2_POS 27u
95 #define MCHP_ESPI_BM_STS_BADREQ_2 (1u << 27) /* RW1C */
96
97 #define MCHP_ESPI_BM_STS_ALL_RW1C_1 0x0bfdu
98 #define MCHP_ESPI_BM_STS_ALL_RW1C_2 (0x0bfdu << 16)
99
100 /* BM_IEN */
101 #define MCHP_ESPI_BM1_IEN_DONE_POS 0u
102 #define MCHP_ESPI_BM1_IEN_DONE (1u << 0)
103 #define MCHP_ESPI_BM2_IEN_DONE_POS 16u
104 #define MCHP_ESPI_BM2_IEN_DONE (1u << 16)
105
106 /* BM_CFG */
107 #define MCHP_ESPI_BM1_CFG_TAG_POS 0u
108 #define MCHP_ESPI_BM1_CFG_TAG_MASK0 0x0fu
109 #define MCHP_ESPI_BM1_CFG_TAG_MASK (0x0fu << 0)
110 #define MCHP_ESPI_BM2_CFG_TAG_POS 16u
111 #define MCHP_ESPI_BM2_CFG_TAG_MASK0 0x0fu
112 #define MCHP_ESPI_BM2_CFG_TAG_MASK (0x0fu << 16)
113
114 /* BM1_CTRL */
115 #define MCHP_ESPI_BM1_CTRL_START_POS 0u
116 #define MCHP_ESPI_BM1_CTRL_START (1u << 0) /* WO */
117 #define MCHP_ESPI_BM1_CTRL_ABORT_POS 1u
118 #define MCHP_ESPI_BM1_CTRL_ABORT (1u << 1) /* WO */
119 #define MCHP_ESPI_BM1_CTRL_EN_INC_POS 2u
120 #define MCHP_ESPI_BM1_CTRL_EN_INC (1u << 2) /* RW */
121 #define MCHP_ESPI_BM1_CTRL_WAIT_NB2_POS 3u
122 #define MCHP_ESPI_BM1_CTRL_WAIT_NB2 (1u << 3) /* RW */
123 #define MCHP_ESPI_BM1_CTRL_CTYPE_POS 8u
124 #define MCHP_ESPI_BM1_CTRL_CTYPE_MASK0 0x03u
125 #define MCHP_ESPI_BM1_CTRL_CTYPE_MASK (0x03u << 8)
126 #define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR32 (0x00u << 8)
127 #define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR32 (0x01u << 8)
128 #define MCHP_ESPI_BM1_CTRL_CTYPE_RD_ADDR64 (0x02u << 8)
129 #define MCHP_ESPI_BM1_CTRL_CTYPE_WR_ADDR64 (0x03u << 8)
130 #define MCHP_ESPI_BM1_CTRL_LEN_POS 16u
131 #define MCHP_ESPI_BM1_CTRL_LEN_MASK0 0x1fffu
132 #define MCHP_ESPI_BM1_CTRL_LEN_MASK (0x1fffu << 16)
133
134 /* BM1_EC_ADDR_LSW */
135 #define MCHP_ESPI_BM1_EC_ADDR_LSW_MASK 0xfffffffcu
136
137 /* BM2_CTRL */
138 #define MCHP_ESPI_BM2_CTRL_START_POS 0u
139 #define MCHP_ESPI_BM2_CTRL_START (1u << 0) /* WO */
140 #define MCHP_ESPI_BM2_CTRL_ABORT_POS 1u
141 #define MCHP_ESPI_BM2_CTRL_ABORT (1u << 1) /* WO */
142 #define MCHP_ESPI_BM2_CTRL_EN_INC_POS 2u
143 #define MCHP_ESPI_BM2_CTRL_EN_INC (1u << 2) /* RW */
144 #define MCHP_ESPI_BM2_CTRL_WAIT_NB2_POS 3u
145 #define MCHP_ESPI_BM2_CTRL_WAIT_NB2 (1u << 3) /* RW */
146 #define MCHP_ESPI_BM2_CTRL_CTYPE_POS 8u
147 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK0 0x03u
148 #define MCHP_ESPI_BM2_CTRL_CTYPE_MASK (0x03u << 8)
149 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR32 (0x00u << 8)
150 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR32 (0x01u << 8)
151 #define MCHP_ESPI_BM2_CTRL_CTYPE_RD_ADDR64 (0x02u << 8)
152 #define MCHP_ESPI_BM2_CTRL_CTYPE_WR_ADDR64 (0x03u << 8)
153 #define MCHP_ESPI_BM2_CTRL_LEN_POS 16u
154 #define MCHP_ESPI_BM2_CTRL_LEN_MASK0 0x1fffu
155 #define MCHP_ESPI_BM2_CTRL_LEN_MASK (0x1fffu << 16)
156
157 /* BM2_EC_ADDR_LSW */
158 #define MCHP_ESPI_BM2_EC_ADDR_LSW_MASK 0xfffffffcu
159
160 typedef struct espi_mem_bm_regs
161 {
162 __IOM uint32_t BM_STS; /*! (@ 0x0000) Bus Master Status */
163 __IOM uint32_t BM_IEN; /*! (@ 0x0004) Bus Master interrupt enable */
164 __IOM uint32_t BM_CFG; /*! (@ 0x0008) Bus Master configuration */
165 uint8_t RSVD1[4];
166 __IOM uint32_t BM1_CTRL; /*! (@ 0x0010) Bus Master 1 control */
167 __IOM uint32_t BM1_HOST_ADDR_LSW; /*! (@ 0x0014) Bus Master 1 host address bits[31:0] */
168 __IOM uint32_t BM1_HOST_ADDR_MSW; /*! (@ 0x0018) Bus Master 1 host address bits[63:32] */
169 __IOM uint32_t BM1_EC_ADDR_LSW; /*! (@ 0x001c) Bus Master 1 EC address bits[31:0] */
170 __IOM uint32_t BM1_EC_ADDR_MSW; /*! (@ 0x0020) Bus Master 1 EC address bits[63:32] */
171 __IOM uint32_t BM2_CTRL; /*! (@ 0x0024) Bus Master 2 control */
172 __IOM uint32_t BM2_HOST_ADDR_LSW; /*! (@ 0x0028) Bus Master 2 host address bits[31:0] */
173 __IOM uint32_t BM2_HOST_ADDR_MSW; /*! (@ 0x002c) Bus Master 2 host address bits[63:32] */
174 __IOM uint32_t BM2_EC_ADDR_LSW; /*! (@ 0x0030) Bus Master 2 EC address bits[31:0] */
175 __IOM uint32_t BM2_EC_ADDR_MSW; /*! (@ 0x0034) Bus Master 2 EC address bits[63:32] */
176 } ESPI_MEM_BM_Type;
177
178 /*
179 * MCHP_ESPI_MEM_BAR_EC @ 0x400f3930
180 *
181 * Half-word H0 of each EC Memory BAR contains
182 * Memory BAR memory address mask bits in bits[7:0]
183 * Logical Device Number in bits[13:8]
184 */
185 #define MCHP_ESPI_EBAR_H0_MEM_MASK_POS 0u
186 #define MCHP_ESPI_EBAR_H0_MEM_MASK_MASK 0xffu
187 #define MCHP_ESPI_EBAR_H0_LDN_POS 8u
188 #define MCHP_ESPI_EBAR_H0_LDN_MASK0 0x3fu
189 #define MCHP_ESPI_EBAR_H0_LDN_MASK (0x3fu << 8u)
190
191 typedef struct espi_mem_bar_ec_regs
192 {
193 __IOM uint16_t EBAR_MBX_H0; /*! (@ 0x0000) Mailbox Logical Device BAR Internal b[15:0] */
194 __IOM uint16_t EBAR_MBX_H1; /*! (@ 0x0002) Mailbox Logical Device BAR Internal b[31:16] */
195 __IOM uint16_t EBAR_MBX_H2; /*! (@ 0x0004) Mailbox Logical Device BAR Internal b[47:32] */
196 __IOM uint16_t EBAR_MBX_H3; /*! (@ 0x0006) Mailbox Logical Device BAR Internal b[63:48] */
197 __IOM uint16_t EBAR_MBX_H4; /*! (@ 0x0008) Mailbox Logical Device BAR Internal b[79:64] */
198 __IOM uint16_t EBAR_ACPI_EC_0_H0; /*! (@ 0x000a) ACPI EC0 Logical Device BAR Internal b[15:0] */
199 __IOM uint16_t EBAR_ACPI_EC_0_H1; /*! (@ 0x000c) ACPI EC0 Logical Device BAR Internal b[31:16] */
200 __IOM uint16_t EBAR_ACPI_EC_0_H2; /*! (@ 0x000e) ACPI EC0 Logical Device BAR Internal b[47:32] */
201 __IOM uint16_t EBAR_ACPI_EC_0_H3; /*! (@ 0x0010) ACPI EC0 Logical Device BAR Internal b[63:48] */
202 __IOM uint16_t EBAR_ACPI_EC_0_H4; /*! (@ 0x0012) ACPI EC0 Logical Device BAR Internal b[79:64] */
203 __IOM uint16_t EBAR_ACPI_EC_1_H0; /*! (@ 0x0014) ACPI EC1 Logical Device BAR Internal b[15:0] */
204 __IOM uint16_t EBAR_ACPI_EC_1_H1; /*! (@ 0x0016) ACPI EC1 Logical Device BAR Internal b[31:16] */
205 __IOM uint16_t EBAR_ACPI_EC_1_H2; /*! (@ 0x0018) ACPI EC1 Logical Device BAR Internal b[47:32] */
206 __IOM uint16_t EBAR_ACPI_EC_1_H3; /*! (@ 0x001a) ACPI EC1 Logical Device BAR Internal b[63:48] */
207 __IOM uint16_t EBAR_ACPI_EC_1_H4; /*! (@ 0x001c) ACPI EC1 Logical Device BAR Internal b[79:64] */
208 __IOM uint16_t EBAR_ACPI_EC_2_H0; /*! (@ 0x001e) ACPI EC2 Logical Device BAR Internal b[15:0] */
209 __IOM uint16_t EBAR_ACPI_EC_2_H1; /*! (@ 0x0020) ACPI EC2 Logical Device BAR Internal b[31:16] */
210 __IOM uint16_t EBAR_ACPI_EC_2_H2; /*! (@ 0x0022) ACPI EC2 Logical Device BAR Internal b[47:32] */
211 __IOM uint16_t EBAR_ACPI_EC_2_H3; /*! (@ 0x0024) ACPI EC2 Logical Device BAR Internal b[63:48] */
212 __IOM uint16_t EBAR_ACPI_EC_2_H4; /*! (@ 0x0026) ACPI EC2 Logical Device BAR Internal b[79:64] */
213 __IOM uint16_t EBAR_ACPI_EC_3_H0; /*! (@ 0x0028) ACPI EC3 Logical Device BAR Internal b[15:0] */
214 __IOM uint16_t EBAR_ACPI_EC_3_H1; /*! (@ 0x002a) ACPI EC3 Logical Device BAR Internal b[31:16] */
215 __IOM uint16_t EBAR_ACPI_EC_3_H2; /*! (@ 0x002c) ACPI EC3 Logical Device BAR Internal b[47:32] */
216 __IOM uint16_t EBAR_ACPI_EC_3_H3; /*! (@ 0x002e) ACPI EC3 Logical Device BAR Internal b[63:48] */
217 __IOM uint16_t EBAR_ACPI_EC_3_H4; /*! (@ 0x0030) ACPI EC3 Logical Device BAR Internal b[79:64] */
218 uint8_t RSVD1[10];
219 __IOM uint16_t EBAR_EMI_0_H0; /*! (@ 0x003c) EMI0 Logical Device BAR Internal b[15:0] */
220 __IOM uint16_t EBAR_EMI_0_H1; /*! (@ 0x003e) EMI0 Logical Device BAR Internal b[31:16] */
221 __IOM uint16_t EBAR_EMI_0_H2; /*! (@ 0x0040) EMI0 Logical Device BAR Internal b[47:32] */
222 __IOM uint16_t EBAR_EMI_0_H3; /*! (@ 0x0042) EMI0 Logical Device BAR Internal b[63:48] */
223 __IOM uint16_t EBAR_EMI_0_H4; /*! (@ 0x0044) EMI0 Logical Device BAR Internal b[79:64] */
224 __IOM uint16_t EBAR_EMI_1_H0; /*! (@ 0x0046) EMI1 Logical Device BAR Internal b[15:0] */
225 __IOM uint16_t EBAR_EMI_1_H1; /*! (@ 0x0048) EMI1 Logical Device BAR Internal b[31:16] */
226 __IOM uint16_t EBAR_EMI_1_H2; /*! (@ 0x004a) EMI1 Logical Device BAR Internal b[47:32] */
227 __IOM uint16_t EBAR_EMI_1_H3; /*! (@ 0x004c) EMI1 Logical Device BAR Internal b[63:48] */
228 __IOM uint16_t EBAR_EMI_1_H4; /*! (@ 0x004e) EMI1 Logical Device BAR Internal b[79:64] */
229 } ESPI_MEM_BAR_EC_Type;
230
231 /*
232 * MCHP_ESPI_MEM_BAR_HOST @ 0x400f3b30
233 *
234 * Each Host BAR contains:
235 * bit[0] (RW) = Valid bit
236 * bits[15:1] = Reserved, read-only 0
237 * bits[47:16] (RW) = bits[31:0] of the Host Memory address.
238 */
239
240 /* Memory BAR Host address valid */
241 #define MCHP_ESPI_HBAR_VALID_POS 0u
242 #define MCHP_ESPI_HBAR_VALID_MASK 0x01u
243 /*
244 * Host address is in bits[47:16] of the HBAR
245 * HBAR's are spaced every 10 bytes (80 bits) but
246 * only implement bits[47:0]
247 */
248 #define MCHP_ESPI_HBAR_VALID_OFS 0x00u /* byte 0 */
249 /* 32-bit Host Address */
250 #define MCHP_ESPI_HBAR_ADDR_B0_OFS 0x02u /* byte 2 */
251 #define MCHP_ESPI_HBAR_ADDR_B1_OFS 0x03u /* byte 3 */
252 #define MCHP_ESPI_HBAR_ADDR_B2_OFS 0x04u /* byte 4 */
253 #define MCHP_ESPI_HBAR_ADDR_B3_OFS 0x05u /* byte 5 */
254
255 typedef struct espi_mem_bar_host_regs
256 {
257 __IOM uint16_t HBAR_MBX_H0; /*! (@ 0x0000) Mailbox Logical Device BAR Host b[15:0] */
258 __IOM uint16_t HBAR_MBX_H1; /*! (@ 0x0002) Mailbox Logical Device BAR Host b[31:16] */
259 __IOM uint16_t HBAR_MBX_H2; /*! (@ 0x0004) Mailbox Logical Device BAR Host b[47:32] */
260 __IOM uint16_t HBAR_MBX_H3; /*! (@ 0x0006) Mailbox Logical Device BAR Host b[63:48] */
261 __IOM uint16_t HBAR_MBX_H4; /*! (@ 0x0008) Mailbox Logical Device BAR Host b[79:64] */
262 __IOM uint16_t HBAR_ACPI_EC_0_H0; /*! (@ 0x000a) ACPI EC0 Logical Device BAR Host b[15:0] */
263 __IOM uint16_t HBAR_ACPI_EC_0_H1; /*! (@ 0x000c) ACPI EC0 Logical Device BAR Host b[31:16] */
264 __IOM uint16_t HBAR_ACPI_EC_0_H2; /*! (@ 0x000e) ACPI EC0 Logical Device BAR Host b[47:32] */
265 __IOM uint16_t HBAR_ACPI_EC_0_H3; /*! (@ 0x0010) ACPI EC0 Logical Device BAR Host b[63:48] */
266 __IOM uint16_t HBAR_ACPI_EC_0_H4; /*! (@ 0x0012) ACPI EC0 Logical Device BAR Host b[79:64] */
267 __IOM uint16_t HBAR_ACPI_EC_1_H0; /*! (@ 0x0014) ACPI EC1 Logical Device BAR Host b[15:0] */
268 __IOM uint16_t HBAR_ACPI_EC_1_H1; /*! (@ 0x0016) ACPI EC1 Logical Device BAR Host b[31:16] */
269 __IOM uint16_t HBAR_ACPI_EC_1_H2; /*! (@ 0x0018) ACPI EC1 Logical Device BAR Host b[47:32] */
270 __IOM uint16_t HBAR_ACPI_EC_1_H3; /*! (@ 0x001a) ACPI EC1 Logical Device BAR Host b[63:48] */
271 __IOM uint16_t HBAR_ACPI_EC_1_H4; /*! (@ 0x001c) ACPI EC1 Logical Device BAR Host b[79:64] */
272 __IOM uint16_t HBAR_ACPI_EC_2_H0; /*! (@ 0x001e) ACPI EC2 Logical Device BAR Host b[15:0] */
273 __IOM uint16_t HBAR_ACPI_EC_2_H1; /*! (@ 0x0020) ACPI EC2 Logical Device BAR Host b[31:16] */
274 __IOM uint16_t HBAR_ACPI_EC_2_H2; /*! (@ 0x0022) ACPI EC2 Logical Device BAR Host b[47:32] */
275 __IOM uint16_t HBAR_ACPI_EC_2_H3; /*! (@ 0x0024) ACPI EC2 Logical Device BAR Host b[63:48] */
276 __IOM uint16_t HBAR_ACPI_EC_2_H4; /*! (@ 0x0026) ACPI EC2 Logical Device BAR Host b[79:64] */
277 __IOM uint16_t HBAR_ACPI_EC_3_H0; /*! (@ 0x0028) ACPI EC3 Logical Device BAR Host b[15:0] */
278 __IOM uint16_t HBAR_ACPI_EC_3_H1; /*! (@ 0x002a) ACPI EC3 Logical Device BAR Host b[31:16] */
279 __IOM uint16_t HBAR_ACPI_EC_3_H2; /*! (@ 0x002c) ACPI EC3 Logical Device BAR Host b[47:32] */
280 __IOM uint16_t HBAR_ACPI_EC_3_H3; /*! (@ 0x002e) ACPI EC3 Logical Device BAR Host b[63:48] */
281 __IOM uint16_t HBAR_ACPI_EC_3_H4; /*! (@ 0x0030) ACPI EC3 Logical Device BAR Host b[79:64] */
282 uint8_t RSVD1[10];
283 __IOM uint16_t HBAR_EMI_0_H0; /*! (@ 0x003c) EMI0 Logical Device BAR Internal b[15:0] */
284 __IOM uint16_t HBAR_EMI_0_H1; /*! (@ 0x003e) EMI0 Logical Device BAR Internal b[31:16] */
285 __IOM uint16_t HBAR_EMI_0_H2; /*! (@ 0x0040) EMI0 Logical Device BAR Internal b[47:32] */
286 __IOM uint16_t HBAR_EMI_0_H3; /*! (@ 0x0042) EMI0 Logical Device BAR Internal b[63:48] */
287 __IOM uint16_t HBAR_EMI_0_H4; /*! (@ 0x0044) EMI0 Logical Device BAR Internal b[79:64] */
288 __IOM uint16_t HBAR_EMI_1_H0; /*! (@ 0x0046) EMI1 Logical Device BAR Internal b[15:0] */
289 __IOM uint16_t HBAR_EMI_1_H1; /*! (@ 0x0048) EMI1 Logical Device BAR Internal b[31:16] */
290 __IOM uint16_t HBAR_EMI_1_H2; /*! (@ 0x004a) EMI1 Logical Device BAR Internal b[47:32] */
291 __IOM uint16_t HBAR_EMI_1_H3; /*! (@ 0x004c) EMI1 Logical Device BAR Internal b[63:48] */
292 __IOM uint16_t HBAR_EMI_1_H4; /*! (@ 0x004e) EMI1 Logical Device BAR Internal b[79:64] */
293 } ESPI_MEM_BAR_HOST_Type;
294
295 /*
296 * eSPI Memory Component SRAM 0 and 1 EC BAR's @ 0x400f39a0
297 * bit[0] = Valid
298 * bits[2:1] = Access
299 * bit[3] = reserved, read-only 0
300 * bits[7:4] = Size as power of 2
301 * bits[15:8] = reserved, read-only 0
302 * bits[47:16] = Base address of EC SRAM mapped to this BAR must be
303 * aligned on Size boundary.
304 */
305 #define MCHP_EC_SRAM_BAR_H0_VALID_POS 0u
306 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK0 0x01u
307 #define MCHP_EC_SRAM_BAR_H0_VALID_MASK 0x01u
308 #define MCHP_EC_SRAM_BAR_H0_VALID 0x01u
309 #define MCHP_EC_SRAM_BAR_H0_ACCESS_POS 1u
310 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0 0x03u
311 #define MCHP_EC_SRAM_BAR_H0_ACCESS_MASK (0x03u << 1u)
312 #define MCHP_EC_SRAM_BAR_H0_ACCESS_NONE (0x00u << 1u)
313 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RO (0x01u << 1u)
314 #define MCHP_EC_SRAM_BAR_H0_ACCESS_WO (0x02u << 1u)
315 #define MCHP_EC_SRAM_BAR_H0_ACCESS_RW (0x03u << 1u)
316 #define MCHP_EC_SRAM_BAR_H0_SIZE_POS 4u
317 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK0 0x0fu
318 #define MCHP_EC_SRAM_BAR_H0_SIZE_MASK (0x0fu << 4u)
319 #define MCHP_EC_SRAM_BAR_H0_SIZE_1B (0x00u << 4u)
320 #define MCHP_EC_SRAM_BAR_H0_SIZE_2B (0x01u << 4u)
321 #define MCHP_EC_SRAM_BAR_H0_SIZE_4B (0x02u << 4u)
322 #define MCHP_EC_SRAM_BAR_H0_SIZE_8B (0x03u << 4u)
323 #define MCHP_EC_SRAM_BAR_H0_SIZE_16B (0x04u << 4u)
324 #define MCHP_EC_SRAM_BAR_H0_SIZE_32B (0x05u << 4u)
325 #define MCHP_EC_SRAM_BAR_H0_SIZE_64B (0x06u << 4u)
326 #define MCHP_EC_SRAM_BAR_H0_SIZE_128B (0x07u << 4u)
327 #define MCHP_EC_SRAM_BAR_H0_SIZE_256B (0x08u << 4u)
328 #define MCHP_EC_SRAM_BAR_H0_SIZE_512B (0x09u << 4u)
329 #define MCHP_EC_SRAM_BAR_H0_SIZE_1KB (0x0au << 4u)
330 #define MCHP_EC_SRAM_BAR_H0_SIZE_2KB (0x0bu << 4u)
331 #define MCHP_EC_SRAM_BAR_H0_SIZE_4KB (0x0cu << 4u)
332 #define MCHP_EC_SRAM_BAR_H0_SIZE_8KB (0x0du << 4u)
333 #define MCHP_EC_SRAM_BAR_H0_SIZE_16KB (0x0eu << 4u)
334 #define MCHP_EC_SRAM_BAR_H0_SIZE_32KB (0x0fu << 4u)
335 /* EC and Host SRAM BAR start offset of EC or Host memory address */
336 #define MCHP_EC_SRAM_BAR_MADDR_OFS1 2u
337 #define MCHP_EC_SRAM_BAR_MADDR_OFS2 4u
338
339 typedef struct espi_mem_sram_bar_ec_regs {
340 uint8_t RSVD1[12];
341 __IOM uint16_t EC_SRAM_0_H0; /*! (@ 0x000c) SRAM0 BAR Internal b[15:0] */
342 __IOM uint16_t EC_SRAM_0_H1; /*! (@ 0x000e) SRAM0 BAR Internal b[31:16] */
343 __IOM uint16_t EC_SRAM_0_H2; /*! (@ 0x0010) SRAM0 BAR Internal b[47:32] */
344 __IOM uint16_t EC_SRAM_0_H3; /*! (@ 0x0012) SRAM0 BAR Internal b[63:48] */
345 __IOM uint16_t EC_SRAM_0_H4; /*! (@ 0x0014) SRAM0 BAR Internal b[79:64] */
346 __IOM uint16_t EC_SRAM_1_H0; /*! (@ 0x0016) SRAM1 BAR Internal b[15:0] */
347 __IOM uint16_t EC_SRAM_1_H1; /*! (@ 0x0018) SRAM1 BAR Internal b[31:16] */
348 __IOM uint16_t EC_SRAM_1_H2; /*! (@ 0x001a) SRAM1 BAR Internal b[47:32] */
349 __IOM uint16_t EC_SRAM_1_H3; /*! (@ 0x001c) SRAM1 BAR Internal b[63:48] */
350 __IOM uint16_t EC_SRAM_1_H4; /*! (@ 0x001e) SRAM1 BAR Internal b[79:64] */
351 } ESPI_MEM_SRAM_BAR_EC_Type;
352
353 /*
354 * eSPI Memory Component SRAM 0 and 1 Host BAR's @ 0x400f3ba0
355 * bit[0] = Read-Only copy of EC BAR Valid bit
356 * bits[2:1] = Read-Only copy of EC BAR Access field
357 * bit[3] = reserved, read-only 0
358 * bits[7:4] = Read-Only copy of EC Size field
359 * bits[15:8] = reserved, read-only 0
360 * bits[47:16] = R/W. Base address in Host memory space for this BAR.
361 */
362 typedef struct espi_mem_sram_bar_host_regs {
363 uint8_t RSVD1[12];
364 __IOM uint16_t HOST_SRAM_0_H0; /*! (@ 0x03ac) SRAM0 BAR Host b[15:0] */
365 __IOM uint16_t HOST_SRAM_0_H1; /*! (@ 0x03ae) SRAM0 BAR Host b[31:16] */
366 __IOM uint16_t HOST_SRAM_0_H2; /*! (@ 0x03b0) SRAM0 BAR Host b[47:32] */
367 __IOM uint16_t HOST_SRAM_0_H3; /*! (@ 0x03b2) SRAM0 BAR Host b[63:48] */
368 __IOM uint16_t HOST_SRAM_0_H4; /*! (@ 0x03b4) SRAM0 BAR Host b[79:64] */
369 __IOM uint16_t HOST_SRAM_1_H0; /*! (@ 0x03b6) SRAM1 BAR Host b[15:0] */
370 __IOM uint16_t HOST_SRAM_1_H1; /*! (@ 0x03b8) SRAM1 BAR Host b[31:16] */
371 __IOM uint16_t HOST_SRAM_1_H2; /*! (@ 0x03ba) SRAM1 BAR Host b[47:32] */
372 __IOM uint16_t HOST_SRAM_1_H3; /*! (@ 0x03bc) SRAM1 BAR Host b[63:48] */
373 __IOM uint16_t HOST_SRAM_1_H4; /*! (@ 0x03be) SRAM1 BAR Host b[79:64] */
374 } ESPI_MEM_SRAM_BAR_HOST;
375
376 enum mec_espi_sram_bar_size {
377 MCHP_ESPI_SRAM_SZ_1B = 0,
378 MCHP_ESPI_SRAM_SZ_2B,
379 MCHP_ESPI_SRAM_SZ_4B,
380 MCHP_ESPI_SRAM_SZ_8B,
381 MCHP_ESPI_SRAM_SZ_16B,
382 MCHP_ESPI_SRAM_SZ_32B,
383 MCHP_ESPI_SRAM_SZ_64B,
384 MCHP_ESPI_SRAM_SZ_128B,
385 MCHP_ESPI_SRAM_SZ_256B,
386 MCHP_ESPI_SRAM_SZ_512B,
387 MCHP_ESPI_SRAM_SZ_1KB,
388 MCHP_ESPI_SRAM_SZ_2KB,
389 MCHP_ESPI_SRAM_SZ_4KB,
390 MCHP_ESPI_SRAM_SZ_8KB,
391 MCHP_ESPI_SRAM_SZ_16KB,
392 MCHP_ESPI_SRAM_SZ_32KB
393 };
394
395 enum mec_espi_sram_bar_access {
396 MCHP_ESPI_SRAM_ACCESS_NONE = 0,
397 MCHP_ESPI_SRAM_ACCESS_RO,
398 MCHP_ESPI_SRAM_ACCESS_WO,
399 MCHP_ESPI_SRAM_ACCESS_RW
400 };
401
402 enum mec_espi_sram_bar_valid {
403 MCHP_ESPI_SRAM_BAR_NOT_VALID = 0,
404 MCHP_ESPI_SRAM_BAR_VALID
405 };
406
407 static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_valid_get(uintptr_t bar_addr)408 mchp_espi_sram_bar_valid_get(uintptr_t bar_addr)
409 {
410 return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_VALID_POS)
411 & MCHP_EC_SRAM_BAR_H0_VALID_MASK0;
412 }
413
414 static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_valid_set(uintptr_t bar_addr,enum mec_espi_sram_bar_valid valid)415 mchp_espi_sram_bar_valid_set(uintptr_t bar_addr,
416 enum mec_espi_sram_bar_valid valid)
417 {
418 REG16(bar_addr) =
419 (REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_VALID_MASK))
420 | (((uint32_t) valid << MCHP_EC_SRAM_BAR_H0_VALID_POS)
421 & MCHP_EC_SRAM_BAR_H0_VALID_MASK);
422 }
423
424 static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_access_get(uintptr_t bar_addr)425 mchp_espi_sram_bar_access_get(uintptr_t bar_addr)
426 {
427 return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_ACCESS_POS)
428 & MCHP_EC_SRAM_BAR_H0_ACCESS_MASK0;
429 }
430
431 static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_access_set(uintptr_t bar_addr,enum mec_espi_sram_bar_size sz)432 mchp_espi_sram_bar_access_set(uintptr_t bar_addr, enum mec_espi_sram_bar_size sz)
433 {
434 REG16(bar_addr) =
435 (REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_ACCESS_MASK))
436 | (((uint32_t) sz << MCHP_EC_SRAM_BAR_H0_ACCESS_POS)
437 & MCHP_EC_SRAM_BAR_H0_ACCESS_MASK);
438 }
439
440 static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_size_get(uintptr_t bar_addr)441 mchp_espi_sram_bar_size_get(uintptr_t bar_addr)
442 {
443 return (REG16(bar_addr) >> MCHP_EC_SRAM_BAR_H0_SIZE_POS)
444 & MCHP_EC_SRAM_BAR_H0_SIZE_MASK0;
445 }
446
447 static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_size_set(uintptr_t bar_addr,enum mec_espi_sram_bar_size sz)448 mchp_espi_sram_bar_size_set(uintptr_t bar_addr, enum mec_espi_sram_bar_size sz)
449 {
450 REG16(bar_addr) =
451 (REG16(bar_addr) & ~(MCHP_EC_SRAM_BAR_H0_SIZE_MASK))
452 | (((uint32_t) sz << MCHP_EC_SRAM_BAR_H0_SIZE_POS)
453 & MCHP_EC_SRAM_BAR_H0_SIZE_MASK);
454 }
455
456 /*
457 * 32-bit EC or Host memory space address is in bits[47:16] of BAR
458 */
459 static __attribute__ ((always_inline)) inline uint32_t
mchp_espi_sram_bar_maddr_get(uintptr_t bar_addr)460 mchp_espi_sram_bar_maddr_get(uintptr_t bar_addr)
461 {
462 uint32_t maddr;
463
464 maddr = (uint32_t) REG16(bar_addr + 4u);
465 maddr <<= 16u;
466 maddr += (uint32_t) REG16(bar_addr + 2u);
467
468 return maddr;
469 }
470
471 static __attribute__ ((always_inline)) inline void
mchp_espi_sram_bar_maddr_set(uintptr_t bar_addr,uint32_t maddr)472 mchp_espi_sram_bar_maddr_set(uintptr_t bar_addr, uint32_t maddr)
473 {
474 REG16(bar_addr + 2u) = (uint16_t) maddr;
475 REG16(bar_addr + 4u) = (uint16_t) (maddr >> 16u);
476 }
477
478 #endif /* #ifndef _ESPI_MEM_H */
479 /* end espi_mem.h */
480 /** @}
481 */
482
