1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file emi.h 28 *MEC1501 EC Host Memory Interface Registers 29 */ 30 /** @defgroup MEC1501 Peripherals EMI 31 */ 32 33 #ifndef _EMI_H 34 #define _EMI_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ EMI ================ */ 43 /* =========================================================================*/ 44 45 #define MCHP_EMI_BASE_ADDR 0x400f4000u 46 47 #define MCHP_EMI_NUM_INSTANCES 2u 48 #define MCHP_EMI_SPACING 0x0400u 49 #define MCHP_EMI_SPACING_PWROF2 10u 50 51 #define MCHP_EMI0_ADDR 0x400f4000u 52 #define MCHP_EMI1_ADDR 0x400f4400u 53 54 /* 55 * EMI interrupts 56 */ 57 #define MCHP_EMI_GIRQ 15u 58 #define MCHP_EMI_GIRQ_NVIC 7u 59 /* Direct NVIC connections */ 60 #define MCHP_EMI0_NVIC 42u 61 #define MCHP_EMI1_NVIC 43u 62 63 /* GIRQ Source, Enable_Set/Clr, Result registers bit positions */ 64 #define MCHP_EMI0_GIRQ_POS 2u 65 #define MCHP_EMI1_GIRQ_POS 3u 66 67 #define MCHP_EMI0_GIRQ (1u << 2) 68 #define MCHP_EMI1_GIRQ (1u << 3) 69 70 /* 71 * OS_INT_SRC_LSB 72 */ 73 #define MCHP_EMI_OSIS_LSB_EC_WR_POS 0u 74 #define MCHP_EMI_OSIS_LSB_EC_WR (1u << 0) 75 /* the following bits are also apply to OS_INT_MASK_LSB */ 76 #define MCHP_EMI_OSIS_LSB_SWI_POS 1u 77 #define MCHP_EMI_OSIS_LSB_SWI_MASK0 0x7fu 78 #define MCHP_EMI_OSIS_LSB_SWI_MASK 0xfeu 79 #define MCHP_EMI_OSIS_LSB_SWI1 (1u << 1) 80 #define MCHP_EMI_OSIS_LSB_SWI2 (1u << 2) 81 #define MCHP_EMI_OSIS_LSB_SWI3 (1u << 3) 82 #define MCHP_EMI_OSIS_LSB_SWI4 (1u << 4) 83 #define MCHP_EMI_OSIS_LSB_SWI5 (1u << 5) 84 #define MCHP_EMI_OSIS_LSB_SWI6 (1u << 6) 85 #define MCHP_EMI_OSIS_LSB_SWI7 (1u << 7) 86 87 /* 88 * OS_INT_SRC_MSB and OS_INT_MASK_MSB 89 */ 90 #define MCHP_EMI_OSIS_MSB_SWI_POS 0u 91 #define MCHP_EMI_OSIS_MSB_SWI_MASK0 0xffu 92 #define MCHP_EMI_OSIS_MSB_SWI_MASK 0xffu 93 #define MCHP_EMI_OSIS_MSB_SWI8 (1u << 0) 94 #define MCHP_EMI_OSIS_MSB_SWI9 (1u << 1) 95 #define MCHP_EMI_OSIS_MSB_SWI10 (1u << 2) 96 #define MCHP_EMI_OSIS_MSB_SWI11 (1u << 3) 97 #define MCHP_EMI_OSIS_MSB_SWI12 (1u << 4) 98 #define MCHP_EMI_OSIS_MSB_SWI13 (1u << 5) 99 #define MCHP_EMI_OSIS_MSB_SWI14 (1u << 6) 100 #define MCHP_EMI_OSIS_MSB_SWI15 (1u << 7) 101 102 /* 103 * OS_APP_ID 104 */ 105 #define MCHP_EMI_OS_APP_ID_MASK 0xffu 106 107 /* 108 * MEM_BASE_0 and MEM_BASE_1 registers 109 * bits[1:0] = 00b read-only forcing EC SRAM location to 110 * be aligned >= 4 bytes. 111 */ 112 #define MCHP_EMI_MEM_BASE_MASK 0xfffffffcu 113 114 /* 115 * MEM_LIMIT_0 and MEM_LIMIT_1 registers are split into two fields 116 * bits[15:0] = read limit 117 * bits[1:0]=00b read-only forcing >= 4 byte alignment 118 * bits[31:16] = write limit 119 * bits[17:16]=00b read-only forcing >= 4 byte alignment 120 */ 121 #define MEM_EMI_MEM_LIMIT_MASK 0xfffcfffcu 122 #define MEM_EMI_MEM_LIMIT_RD_POS 0u 123 #define MEM_EMI_MEM_LIMIT_RD_MASK0 0xfffcu 124 #define MEM_EMI_MEM_LIMIT_RD_MASK 0xfffcu 125 #define MEM_EMI_MEM_LIMIT_WR_POS 16u 126 #define MEM_EMI_MEM_LIMIT_WR_MASK0 0xfffcu 127 #define MEM_EMI_MEM_LIMIT_WR_MASK (0xfffcu << 16) 128 129 /* 130 * EC_SET_OS_INT and EC_OS_INT_CLR_EN 131 */ 132 #define MCHP_EMI_EC_OS_SWI_MASK 0xfffeu 133 #define MCHP_EMI_EC_OS_SWI1 (1u << 1) 134 #define MCHP_EMI_EC_OS_SWI2 (1u << 2) 135 #define MCHP_EMI_EC_OS_SWI3 (1u << 3) 136 #define MCHP_EMI_EC_OS_SWI4 (1u << 4) 137 #define MCHP_EMI_EC_OS_SWI5 (1u << 5) 138 #define MCHP_EMI_EC_OS_SWI6 (1u << 6) 139 #define MCHP_EMI_EC_OS_SWI7 (1u << 7) 140 #define MCHP_EMI_EC_OS_SWI8 (1u << 8) 141 #define MCHP_EMI_EC_OS_SWI9 (1u << 9) 142 #define MCHP_EMI_EC_OS_SWI10 (1u << 10) 143 #define MCHP_EMI_EC_OS_SWI11 (1u << 11) 144 #define MCHP_EMI_EC_OS_SWI12 (1u << 12) 145 #define MCHP_EMI_EC_OS_SWI13 (1u << 13) 146 #define MCHP_EMI_EC_OS_SWI14 (1u << 14) 147 #define MCHP_EMI_EC_OS_SWI15 (1u << 15) 148 149 150 /** 151 * @brief EMI Registers (EMI) 152 */ 153 typedef struct emi_regs 154 { 155 __IOM uint8_t OS_H2E_MBOX; /*!< (@ 0x0000) OS space Host to EC mailbox register */ 156 __IOM uint8_t OS_E2H_MBOX; /*!< (@ 0x0001) OS space EC to Host mailbox register */ 157 __IOM uint8_t OS_EC_ADDR_LSB; /*!< (@ 0x0002) OS space EC memory address LSB register */ 158 __IOM uint8_t OS_EC_ADDR_MSB; /*!< (@ 0x0003) OS space EC memory address LSB register */ 159 __IOM uint32_t OS_EC_DATA; /*!< (@ 0x0004) OS space EC Data register */ 160 __IOM uint8_t OS_INT_SRC_LSB; /*!< (@ 0x0008) OS space Interrupt Source LSB register */ 161 __IOM uint8_t OS_INT_SRC_MSB; /*!< (@ 0x0009) OS space Interrupt Source MSB register */ 162 __IOM uint8_t OS_INT_MASK_LSB; /*!< (@ 0x000a) OS space Interrupt Mask LSB register */ 163 __IOM uint8_t OS_INT_MASK_MSB; /*!< (@ 0x000b) OS space Interrupt Mask MSB register */ 164 __IOM uint32_t OS_APP_ID; /*!< (@ 0x000c) OS space Application ID register */ 165 uint8_t RSVD1[0x100u - 0x10u]; 166 __IOM uint8_t H2E_MBOX; /*!< (@ 0x0100) Host to EC mailbox */ 167 __IOM uint8_t E2H_MBOX; /*!< (@ 0x0101) EC Data */ 168 uint8_t RSVD2[2]; 169 __IOM uint32_t MEM_BASE_0; /*!< (@ 0x0104) EC memory region 0 base address */ 170 __IOM uint32_t MEM_LIMIT_0; /*!< (@ 0x0108) EC memory region 0 read/write limits */ 171 __IOM uint32_t MEM_BASE_1; /*!< (@ 0x010c) EC memory region 1 base address */ 172 __IOM uint32_t MEM_LIMIT_1; /*!< (@ 0x0110) EC memory region 1 read/write limits */ 173 __IOM uint16_t EC_OS_INT_SET; /*!< (@ 0x0114) Set OS interrupt source */ 174 __IOM uint16_t EC_OS_INT_CLR_EN; /*!< (@ 0x0116) OS interrupt source clear enable */ 175 } EMI_Type; 176 177 #endif /* #ifndef _EMI_H */ 178 /* end emi.h */ 179 /** @} 180 */ 181
