1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file mec1501_ecia.h 28 *MEC1501 EC Interrupt Aggregator Subsystem definitions 29 */ 30 /** @defgroup MEC1501 Peripherals ECIA 31 */ 32 33 #ifndef _ECIA_H 34 #define _ECIA_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 #define MCHP_ECIA_ADDR 0x4000e000u 42 #define MCHP_FIRST_GIRQ 8u 43 #define MCHP_LAST_GIRQ 26u 44 45 #define MCHP_ECIA_GIRQ_NO_NVIC 22u 46 47 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) |\ 48 BIT(12) | BIT(24) | BIT(25) | BIT(26)) 49 50 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) |\ 51 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | BIT(23)) 52 53 /* 54 * ARM Cortex-M4 NVIC registers 55 * External sources are grouped by 32-bit registers. 56 * MEC15xx has 173 external sources requiring 6 32-bit registers. 57 */ 58 #define MCHP_NUM_NVIC_REGS 6u 59 #define MCHP_NVIC_SET_EN_BASE 0xe000e100u 60 #define MCHP_NVIC_CLR_EN_BASE 0xe000e180u 61 #define MCHP_NVIC_SET_PEND_BASE 0xe000e200u 62 #define MCHP_NVIC_CLR_PEND_BASE 0xe000e280u 63 #define MCHP_NVIC_ACTIVE_BASE 0xe000e800u 64 #define MCHP_NVIC_PRI_BASE 0xe000e400u 65 66 /* 0 <= n < MCHP_NUM_NVIC_REGS */ 67 #define MCHP_NVIC_SET_EN(n) \ 68 REG32(MCHP_NVIC_SET_EN_BASE + ((uintptr_t)(n) * 4u)) 69 70 #define MCHP_NVIC_CLR_EN(n) \ 71 REG32(MCHP_NVIC_CLR_EN_BASE + ((uintptr_t)(n) * 4u)) 72 73 #define MCHP_NVIC_SET_PEND(n) \ 74 REG32(MCHP_NVIC_SET_PEND_BASE + ((uintptr_t)(n) * 4u)) 75 76 #define MCHP_NVIC_CLR_PEND(n) \ 77 REG32(MCHP_NVIC_CLR_PEND_BASE + ((uintptr_t)(n) * 4u)) 78 79 /* 80 * ECIA registers 81 * Implements 19 GIRQ's. GIRQ's aggregated interrupts source into one 82 * set of registers. 83 * For historical reason GIRQ's are numbered starting at 8 in the documentation. 84 * This numbering only affects the ECIA BLOCK_EN_SET, BLOCK_EN_CLR, and 85 * BLOCK_ACTIVE registers: GIRQ8 is bit[8], ..., GIRQ26 is bit[26]. 86 * 87 * Each GIRQ is composed of 5 32-bit registers. 88 * +00h = GIRQ08 Source containing RW/1C status bits 89 * +04h = Enable Set write 1 to bit(s) to enable the corresponding source(s) 90 * +08h = Read-Only Result = Source AND Enable-Set 91 * +0Ch = Enable Clear write 1 to bit(s) to disable the corresponding source(s) 92 * +14h = Reserved(unused). 93 * +18h = GIRQ09 Source 94 * ... 95 * There are three other registers at offset 0x200, 0x204, and 0x208 96 * 0x200: BLOCK_EN_SET bit == 1 allows bit-wise OR of all GIRQn source 97 * bits to be connected to NVIC GIRQn input. 98 * bit[8]=GIRQ8, bit[9]=GIRQ9, ..., bit[26]=GIRQ26 99 * 0x204: BLOCK_EN_CLR bit == 1 disconnects bit-wise OR of GIRQn source 100 * bits from NVIC GIRQn input. 101 * 0x208: BLOCK_ACTIVE (read-only) 102 * bit[8]=GIRQ8 has at least one source bit enabled and active. 103 * ... 104 * bit[26]=GIRQ26 has at least one source bit enabled and active. 105 * 106 */ 107 108 /* zero based logical numbering */ 109 #define MCHP_GIRQ08_ZID 0u 110 #define MCHP_GIRQ09_ZID 1u 111 #define MCHP_GIRQ10_ZID 2u 112 #define MCHP_GIRQ11_ZID 3u 113 #define MCHP_GIRQ12_ZID 4u 114 #define MCHP_GIRQ13_ZID 5u 115 #define MCHP_GIRQ14_ZID 6u 116 #define MCHP_GIRQ15_ZID 7u 117 #define MCHP_GIRQ16_ZID 8u 118 #define MCHP_GIRQ17_ZID 9u 119 #define MCHP_GIRQ18_ZID 10u 120 #define MCHP_GIRQ19_ZID 11u 121 #define MCHP_GIRQ20_ZID 12u /* Nothing in datasheet */ 122 #define MCHP_GIRQ21_ZID 13u 123 124 #define MCHP_GIRQ23_ZID 14u /* Adjust per datasheet */ 125 #define MCHP_GIRQ24_ZID 15u 126 #define MCHP_GIRQ25_ZID 16u 127 #define MCHP_GIRQ26_ZID 17u 128 #define MCHP_GIRQ_ZID_MAX 18u 129 130 #define MCHP_ECIA_BLK_ENSET_OFS 0x200u 131 #define MCHP_ECIA_BLK_ENCLR_OFS 0x204u 132 #define MCHP_ECIA_BLK_ACTIVE_OFS 0x208u 133 134 #define MCHP_GIRQ_BLK_ENSET_ADDR \ 135 (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENSET_OFS) 136 137 #define MCHP_GIRQ_BLK_ENCLR_ADDR \ 138 (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ENCLR_OFS) 139 140 #define MCHP_GIRQ_BLK_ACTIVE_ADDR \ 141 (MCHP_ECIA_ADDR + MCHP_ECIA_BLK_ACTIVE_OFS) 142 143 /* 8 <= n <= 26 */ 144 #define MCHP_GIRQ_TO_AGGR_NVIC(n) (((n) < 23) ? ((n)-8) : ((n)-9)) 145 146 /* 8 <= n <= 26 */ 147 #define MCHP_GIRQ_SRC_ADDR(n) \ 148 ((MCHP_ECIA_ADDR + 0x00u) + (((uint32_t)(n) - 8u) * 0x14u)) 149 150 #define MCHP_GIRQ_ENSET_ADDR(n) \ 151 ((MCHP_ECIA_ADDR + 0x04u) + (((uint32_t)(n) - 8u) * 0x14u)) 152 153 #define MCHP_GIRQ_RESULT_ADDR(n) \ 154 ((MCHP_ECIA_ADDR + 0x08u) + (((uint32_t)(n) - 8u) * 0x14u)) 155 156 #define MCHP_GIRQ_ENCLR_ADDR(n) \ 157 ((MCHP_ECIA_ADDR + 0x0cu) + (((uint32_t)(n) - 8u) * 0x14u)) 158 159 #define MCHP_GIRQ08_SRC_ADDR MCHP_GIRQ_SRC_ADDR(8) 160 #define MCHP_GIRQ08_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(8) 161 #define MCHP_GIRQ08_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(8) 162 #define MCHP_GIRQ08_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(8) 163 164 #define MCHP_GIRQ09_SRC_ADDR MCHP_GIRQ_SRC_ADDR(9) 165 #define MCHP_GIRQ09_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(9) 166 #define MCHP_GIRQ09_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(9) 167 #define MCHP_GIRQ09_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(9) 168 169 #define MCHP_GIRQ10_SRC_ADDR MCHP_GIRQ_SRC_ADDR(10) 170 #define MCHP_GIRQ10_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(10) 171 #define MCHP_GIRQ10_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(10) 172 #define MCHP_GIRQ10_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(10) 173 174 #define MCHP_GIRQ11_SRC_ADDR MCHP_GIRQ_SRC_ADDR(11) 175 #define MCHP_GIRQ11_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(11) 176 #define MCHP_GIRQ11_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(11) 177 #define MCHP_GIRQ11_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(11) 178 179 #define MCHP_GIRQ12_SRC_ADDR MCHP_GIRQ_SRC_ADDR(12) 180 #define MCHP_GIRQ12_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(12) 181 #define MCHP_GIRQ12_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(12) 182 #define MCHP_GIRQ12_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(12) 183 184 #define MCHP_GIRQ13_SRC_ADDR MCHP_GIRQ_SRC_ADDR(13) 185 #define MCHP_GIRQ13_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(13) 186 #define MCHP_GIRQ13_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(13) 187 #define MCHP_GIRQ13_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(13) 188 189 #define MCHP_GIRQ14_SRC_ADDR MCHP_GIRQ_SRC_ADDR(14) 190 #define MCHP_GIRQ14_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(14) 191 #define MCHP_GIRQ14_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(14) 192 #define MCHP_GIRQ14_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(14) 193 194 #define MCHP_GIRQ15_SRC_ADDR MCHP_GIRQ_SRC_ADDR(15) 195 #define MCHP_GIRQ15_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(15) 196 #define MCHP_GIRQ15_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(15) 197 #define MCHP_GIRQ15_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(15) 198 199 #define MCHP_GIRQ16_SRC_ADDR MCHP_GIRQ_SRC_ADDR(16) 200 #define MCHP_GIRQ16_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(16) 201 #define MCHP_GIRQ16_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(16) 202 #define MCHP_GIRQ16_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(16) 203 204 #define MCHP_GIRQ17_SRC_ADDR MCHP_GIRQ_SRC_ADDR(17) 205 #define MCHP_GIRQ17_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(17) 206 #define MCHP_GIRQ17_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(17) 207 #define MCHP_GIRQ17_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(17) 208 209 #define MCHP_GIRQ18_SRC_ADDR MCHP_GIRQ_SRC_ADDR(18) 210 #define MCHP_GIRQ18_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(18) 211 #define MCHP_GIRQ18_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(18) 212 #define MCHP_GIRQ18_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(18) 213 214 #define MCHP_GIRQ19_SRC_ADDR MCHP_GIRQ_SRC_ADDR(19) 215 #define MCHP_GIRQ19_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(19) 216 #define MCHP_GIRQ19_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(19) 217 #define MCHP_GIRQ19_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(19) 218 219 #define MCHP_GIRQ20_SRC_ADDR MCHP_GIRQ_SRC_ADDR(20) 220 #define MCHP_GIRQ20_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(20) 221 #define MCHP_GIRQ20_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(20) 222 #define MCHP_GIRQ20_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(20) 223 224 #define MCHP_GIRQ21_SRC_ADDR MCHP_GIRQ_SRC_ADDR(21) 225 #define MCHP_GIRQ21_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(21) 226 #define MCHP_GIRQ21_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(21) 227 #define MCHP_GIRQ21_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(21) 228 229 #define MCHP_GIRQ22_SRC_ADDR MCHP_GIRQ_SRC_ADDR(22) 230 #define MCHP_GIRQ22_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(22) 231 #define MCHP_GIRQ22_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(22) 232 #define MCHP_GIRQ22_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(22) 233 234 #define MCHP_GIRQ23_SRC_ADDR MCHP_GIRQ_SRC_ADDR(23) 235 #define MCHP_GIRQ23_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(23) 236 #define MCHP_GIRQ23_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(23) 237 #define MCHP_GIRQ23_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(23) 238 239 #define MCHP_GIRQ24_SRC_ADDR MCHP_GIRQ_SRC_ADDR(24) 240 #define MCHP_GIRQ24_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(24) 241 #define MCHP_GIRQ24_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(24) 242 #define MCHP_GIRQ24_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(24) 243 244 #define MCHP_GIRQ25_SRC_ADDR MCHP_GIRQ_SRC_ADDR(25) 245 #define MCHP_GIRQ25_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(25) 246 #define MCHP_GIRQ25_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(25) 247 #define MCHP_GIRQ25_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(25) 248 249 #define MCHP_GIRQ26_SRC_ADDR MCHP_GIRQ_SRC_ADDR(26) 250 #define MCHP_GIRQ26_ENSET_ADDR MCHP_GIRQ_ENSET_ADDR(26) 251 #define MCHP_GIRQ26_RESULT_ADDR MCHP_GIRQ_RESULT_ADDR(26) 252 #define MCHP_GIRQ26_ENCLR_ADDR MCHP_GIRQ_ENCLR_ADDR(26) 253 254 /* 255 * Register access 256 */ 257 #define MCHP_GIRQ_BLK_ENSET() \ 258 REG32(MCHP_GIRQ_BLK_ENSET_ADDR) 259 260 #define MCHP_GIRQ_BLK_ENCLR() \ 261 REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) 262 263 #define MCHP_GIRQ_BLK_ACTIVE() \ 264 REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) 265 266 /* 267 * Set/clear GIRQ Block Enable 268 * Check if block is active 269 * 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 270 */ 271 #define MCHP_GIRQ_BLK_SETEN(n) \ 272 REG32(MCHP_GIRQ_BLK_ENSET_ADDR) = BIT(n) 273 274 #define MCHP_GIRQ_BLK_CLREN(n) \ 275 REG32(MCHP_GIRQ_BLK_ENCLR_ADDR) = BIT(n) 276 277 #define MCHP_GIRQ_BLK_IS_ACTIVE(n) \ 278 ((REG32(MCHP_GIRQ_BLK_ACTIVE_ADDR) & BIT(n)) != 0u) 279 280 /* 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 */ 281 #define MCHP_GIRQ_SRC(n) REG32(MCHP_GIRQ_SRC_ADDR(n)) 282 283 #define MCHP_GIRQ_ENSET(n) REG32(MCHP_GIRQ_ENSET_ADDR(n)) 284 285 #define MCHP_GIRQ_RESULT(n) REG32(MCHP_GIRQ_RESULT_ADDR(n)) 286 #define MCHP_GIRQ_ENCLR(n) REG32(MCHP_GIRQ_ENCLR_ADDR(n)) 287 288 /* 289 * 8 <= n <= 26 corresponding to GIRQ08, GIRQ09, ..., GIRQ26 290 * 0 <= pos <= 31 the bit position of the peripheral interrupt source. 291 */ 292 #define MCHP_GIRQ_SRC_CLR(n, pos) \ 293 REG32(MCHP_GIRQ_SRC_ADDR(n)) = BIT(pos) 294 295 #define MCHP_GIRQ_SET_EN(n, pos) \ 296 REG32(MCHP_GIRQ_ENSET_ADDR(n)) = BIT(pos) 297 298 #define MCHP_GIRQ_CLR_EN(n, pos) \ 299 REG32(MCHP_GIRQ_ENCLR_ADDR(n)) = BIT(pos) 300 301 #define MCHP_GIRQ_IS_RESULT(n, pos) \ 302 ((REG32(MCHP_GIRQ_RESULT_ADDR(n)) & BIT(pos)) != 0u) 303 304 /* =========================================================================*/ 305 /* ================ ECIA ================ */ 306 /* =========================================================================*/ 307 308 enum MCHP_GIRQ_IDS { 309 MCHP_GIRQ08_ID = 8, 310 MCHP_GIRQ09_ID, 311 MCHP_GIRQ10_ID, 312 MCHP_GIRQ11_ID, 313 MCHP_GIRQ12_ID, 314 MCHP_GIRQ13_ID, 315 MCHP_GIRQ14_ID, 316 MCHP_GIRQ15_ID, 317 MCHP_GIRQ16_ID, 318 MCHP_GIRQ17_ID, 319 MCHP_GIRQ18_ID, 320 MCHP_GIRQ19_ID, 321 MCHP_GIRQ20_ID, 322 MCHP_GIRQ21_ID, 323 MCHP_GIRQ22_ID, 324 MCHP_GIRQ23_ID, 325 MCHP_GIRQ24_ID, 326 MCHP_GIRQ25_ID, 327 MCHP_GIRQ26_ID, 328 MCHP_GIRQ_ID_MAX, 329 }; 330 331 /* 332 * Legacy names: Port 80h capture peripherals. 333 * GIRQ Source, Enable_Set/Clr, Result registers bit positions 334 */ 335 #define MCHP_PORT80_DEBUG0_GIRQ_VAL BIT(22) 336 #define MCHP_PORT80_DEBUG1_GIRQ_VAL BIT(23) 337 338 /* GIRQ08 Source, Enable_Set/Clr, Result registers bit positions */ 339 #define MCHP_GPIO_0140_GIRQ_BIT BIT(0) 340 #define MCHP_GPIO_0141_GIRQ_BIT BIT(1) 341 #define MCHP_GPIO_0142_GIRQ_BIT BIT(2) 342 #define MCHP_GPIO_0143_GIRQ_BIT BIT(3) 343 #define MCHP_GPIO_0144_GIRQ_BIT BIT(4) 344 #define MCHP_GPIO_0145_GIRQ_BIT BIT(5) 345 #define MCHP_GPIO_0146_GIRQ_BIT BIT(6) 346 #define MCHP_GPIO_0147_GIRQ_BIT BIT(7) 347 #define MCHP_GPIO_0150_GIRQ_BIT BIT(8) 348 #define MCHP_GPIO_0151_GIRQ_BIT BIT(9) 349 #define MCHP_GPIO_0152_GIRQ_BIT BIT(10) 350 #define MCHP_GPIO_0153_GIRQ_BIT BIT(11) 351 #define MCHP_GPIO_0154_GIRQ_BIT BIT(12) 352 #define MCHP_GPIO_0155_GIRQ_BIT BIT(13) 353 #define MCHP_GPIO_0156_GIRQ_BIT BIT(14) 354 #define MCHP_GPIO_0157_GIRQ_BIT BIT(15) 355 #define MCHP_GPIO_0161_GIRQ_BIT BIT(17) 356 #define MCHP_GPIO_0162_GIRQ_BIT BIT(18) 357 #define MCHP_GPIO_0163_GIRQ_BIT BIT(19) 358 #define MCHP_GPIO_0165_GIRQ_BIT BIT(21) 359 #define MCHP_GPIO_0170_GIRQ_BIT BIT(24) 360 #define MCHP_GPIO_0171_GIRQ_BIT BIT(25) 361 #define MCHP_GPIO_0172_GIRQ_BIT BIT(26) 362 #define MCHP_GPIO_0175_GIRQ_BIT BIT(29) 363 #define MCHP_GPIO_0140_0176_GIRQ_MASK 0x272effffu 364 365 /* GIRQ09 Source, Enable_Set/Clr, Result registers bit positions */ 366 #define MCHP_GPIO_0100_GIRQ_BIT BIT(0) 367 #define MCHP_GPIO_0101_GIRQ_BIT BIT(1) 368 #define MCHP_GPIO_0102_GIRQ_BIT BIT(2) 369 #define MCHP_GPIO_0104_GIRQ_BIT BIT(4) 370 #define MCHP_GPIO_0105_GIRQ_BIT BIT(5) 371 #define MCHP_GPIO_0106_GIRQ_BIT BIT(6) 372 #define MCHP_GPIO_0107_GIRQ_BIT BIT(7) 373 #define MCHP_GPIO_0112_GIRQ_BIT BIT(10) 374 #define MCHP_GPIO_0113_GIRQ_BIT BIT(11) 375 #define MCHP_GPIO_0114_GIRQ_BIT BIT(12) 376 #define MCHP_GPIO_0115_GIRQ_BIT BIT(13) 377 #define MCHP_GPIO_0116_GIRQ_BIT BIT(14) 378 #define MCHP_GPIO_0117_GIRQ_BIT BIT(15) 379 #define MCHP_GPIO_0120_GIRQ_BIT BIT(16) 380 #define MCHP_GPIO_0121_GIRQ_BIT BIT(17) 381 #define MCHP_GPIO_0122_GIRQ_BIT BIT(18) 382 #define MCHP_GPIO_0123_GIRQ_BIT BIT(19) 383 #define MCHP_GPIO_0124_GIRQ_BIT BIT(20) 384 #define MCHP_GPIO_0125_GIRQ_BIT BIT(21) 385 #define MCHP_GPIO_0126_GIRQ_BIT BIT(22) 386 #define MCHP_GPIO_0127_GIRQ_BIT BIT(23) 387 #define MCHP_GPIO_0130_GIRQ_BIT BIT(24) 388 #define MCHP_GPIO_0131_GIRQ_BIT BIT(25) 389 #define MCHP_GPIO_0132_GIRQ_BIT BIT(26) 390 #define MCHP_GPIO_0100_0136_GIRQ_MASK 0x07fffcf7u 391 392 /* GIRQ10 Source, Enable_Set/Clr, Result registers bit positions */ 393 #define MCHP_GPIO_0040_GIRQ_BIT BIT(0) 394 #define MCHP_GPIO_0042_GIRQ_BIT BIT(2) 395 #define MCHP_GPIO_0043_GIRQ_BIT BIT(3) 396 #define MCHP_GPIO_0044_GIRQ_BIT BIT(4) 397 #define MCHP_GPIO_0045_GIRQ_BIT BIT(5) 398 #define MCHP_GPIO_0046_GIRQ_BIT BIT(6) 399 #define MCHP_GPIO_0047_GIRQ_BIT BIT(7) 400 #define MCHP_GPIO_0050_GIRQ_BIT BIT(8) 401 #define MCHP_GPIO_0051_GIRQ_BIT BIT(9) 402 #define MCHP_GPIO_0052_GIRQ_BIT BIT(10) 403 #define MCHP_GPIO_0053_GIRQ_BIT BIT(11) 404 #define MCHP_GPIO_0054_GIRQ_BIT BIT(12) 405 #define MCHP_GPIO_0055_GIRQ_BIT BIT(13) 406 #define MCHP_GPIO_0056_GIRQ_BIT BIT(14) 407 #define MCHP_GPIO_0057_GIRQ_BIT BIT(15) 408 #define MCHP_GPIO_0060_GIRQ_BIT BIT(16) 409 #define MCHP_GPIO_0061_GIRQ_BIT BIT(17) 410 #define MCHP_GPIO_0062_GIRQ_BIT BIT(18) 411 #define MCHP_GPIO_0063_GIRQ_BIT BIT(19) 412 #define MCHP_GPIO_0064_GIRQ_BIT BIT(20) 413 #define MCHP_GPIO_0065_GIRQ_BIT BIT(21) 414 #define MCHP_GPIO_0066_GIRQ_BIT BIT(22) 415 #define MCHP_GPIO_0067_GIRQ_BIT BIT(23) 416 #define MCHP_GPIO_0070_GIRQ_BIT BIT(24) 417 #define MCHP_GPIO_0071_GIRQ_BIT BIT(25) 418 #define MCHP_GPIO_0072_GIRQ_BIT BIT(26) 419 #define MCHP_GPIO_0073_GIRQ_BIT BIT(27) 420 #define MCHP_GPIO_0074_GIRQ_BIT BIT(28) 421 #define MCHP_GPIO_0075_GIRQ_BIT BIT(29) 422 #define MCHP_GPIO_0040_0076_GIRQ_MASK 0x3ffffffdu 423 424 /* GIRQ11 Source, Enable_Set/Clr, Result registers bit positions */ 425 #define MCHP_GPIO_0000_GIRQ_BIT BIT(0) 426 #define MCHP_GPIO_0002_GIRQ_BIT BIT(2) 427 #define MCHP_GPIO_0003_GIRQ_BIT BIT(3) 428 #define MCHP_GPIO_0004_GIRQ_BIT BIT(4) 429 #define MCHP_GPIO_0007_GIRQ_BIT BIT(7) 430 #define MCHP_GPIO_0010_GIRQ_BIT BIT(8) 431 #define MCHP_GPIO_0011_GIRQ_BIT BIT(9) 432 #define MCHP_GPIO_0012_GIRQ_BIT BIT(10) 433 #define MCHP_GPIO_0013_GIRQ_BIT BIT(11) 434 #define MCHP_GPIO_0014_GIRQ_BIT BIT(12) 435 #define MCHP_GPIO_0015_GIRQ_BIT BIT(13) 436 #define MCHP_GPIO_0016_GIRQ_BIT BIT(14) 437 #define MCHP_GPIO_0017_GIRQ_BIT BIT(15) 438 #define MCHP_GPIO_0020_GIRQ_BIT BIT(16) 439 #define MCHP_GPIO_0021_GIRQ_BIT BIT(17) 440 #define MCHP_GPIO_0022_GIRQ_BIT BIT(18) 441 #define MCHP_GPIO_0023_GIRQ_BIT BIT(19) 442 #define MCHP_GPIO_0024_GIRQ_BIT BIT(20) 443 #define MCHP_GPIO_0025_GIRQ_BIT BIT(21) 444 #define MCHP_GPIO_0026_GIRQ_BIT BIT(22) 445 #define MCHP_GPIO_0027_GIRQ_BIT BIT(23) 446 #define MCHP_GPIO_0030_GIRQ_BIT BIT(24) 447 #define MCHP_GPIO_0031_GIRQ_BIT BIT(25) 448 #define MCHP_GPIO_0032_GIRQ_BIT BIT(26) 449 #define MCHP_GPIO_0033_GIRQ_BIT BIT(27) 450 #define MCHP_GPIO_0034_GIRQ_BIT BIT(28) 451 #define MCHP_GPIO_0035_GIRQ_BIT BIT(29) 452 #define MCHP_GPIO_0036_GIRQ_BIT BIT(30) 453 #define MCHP_GPIO_0000_0036_GIRQ_MASK 0x7fffff9du 454 455 /* GIRQ12 Source, Enable_Set/Clr, Result registers bit positions */ 456 #define MCHP_GPIO_0200_GIRQ_BIT BIT(0) 457 #define MCHP_GPIO_0201_GIRQ_BIT BIT(1) 458 #define MCHP_GPIO_0202_GIRQ_BIT BIT(2) 459 #define MCHP_GPIO_0203_GIRQ_BIT BIT(3) 460 #define MCHP_GPIO_0204_GIRQ_BIT BIT(4) 461 #define MCHP_GPIO_0205_GIRQ_BIT BIT(5) 462 #define MCHP_GPIO_0206_GIRQ_BIT BIT(6) 463 #define MCHP_GPIO_0207_GIRQ_BIT BIT(7) 464 #define MCHP_GPIO_0211_GIRQ_BIT BIT(9) 465 #define MCHP_GPIO_0212_GIRQ_BIT BIT(10) 466 #define MCHP_GPIO_0213_GIRQ_BIT BIT(11) 467 #define MCHP_GPIO_0221_GIRQ_BIT BIT(17) 468 #define MCHP_GPIO_0222_GIRQ_BIT BIT(18) 469 #define MCHP_GPIO_0223_GIRQ_BIT BIT(19) 470 #define MCHP_GPIO_0224_GIRQ_BIT BIT(20) 471 #define MCHP_GPIO_0226_GIRQ_BIT BIT(22) 472 #define MCHP_GPIO_0227_GIRQ_BIT BIT(23) 473 #define MCHP_GPIO_0200_0236_GIRQ_MASK 0x00de0effu 474 475 /* GIRQ13 Source, Enable_Set/Clr, Result registers bit positions */ 476 #define MCHP_I2C_SMB_0_GIRQ_BIT BIT(0) 477 #define MCHP_I2C_SMB_1_GIRQ_BIT BIT(1) 478 #define MCHP_I2C_SMB_2_GIRQ_BIT BIT(2) 479 #define MCHP_I2C_SMB_3_GIRQ_BIT BIT(3) 480 #define MCHP_I2C_SMB_4_GIRQ_BIT BIT(4) 481 #define MCHP_I2C_0_GIRQ_BIT BIT(5) 482 #define MCHP_I2C_1_GIRQ_BIT BIT(6) 483 #define MCHP_I2C_2_GIRQ_BIT BIT(7) 484 /* Masks for blocks with multiple instances or sources */ 485 #define MCHP_SMB_I2C_GIRQ_MASK 0x1fu 486 #define MCHP_I2C_GIRQ_MASK 0xe0u 487 488 /* GIRQ14 Source, Enable_Set/Clr, Result registers bit positions */ 489 #define MCHP_DMA_CH00_GIRQ_BIT BIT(0) 490 #define MCHP_DMA_CH01_GIRQ_BIT BIT(1) 491 #define MCHP_DMA_CH02_GIRQ_BIT BIT(2) 492 #define MCHP_DMA_CH03_GIRQ_BIT BIT(3) 493 #define MCHP_DMA_CH04_GIRQ_BIT BIT(4) 494 #define MCHP_DMA_CH05_GIRQ_BIT BIT(5) 495 #define MCHP_DMA_CH06_GIRQ_BIT BIT(6) 496 #define MCHP_DMA_CH07_GIRQ_BIT BIT(7) 497 #define MCHP_DMA_CH08_GIRQ_BIT BIT(8) 498 #define MCHP_DMA_CH09_GIRQ_BIT BIT(9) 499 #define MCHP_DMA_CH10_GIRQ_BIT BIT(10) 500 #define MCHP_DMA_CH11_GIRQ_BIT BIT(11) 501 #define MCHP_DMA_GIRQ_MASK 0x0fffu 502 503 /* GIRQ15 Source, Enable_Set/Clr, Result registers bit positions */ 504 #define MCHP_UART_0_GIRQ_BIT BIT(0) 505 #define MCHP_UART_1_GIRQ_BIT BIT(1) 506 #define MCHP_EMI_0_GIRQ_BIT BIT(2) 507 #define MCHP_EMI_1_GIRQ_BIT BIT(3) 508 #define MCHP_UART_2_GIRQ_BIT BIT(4) 509 #define MCHP_ACPI_EC_0_IBF_GIRQ_BIT BIT(5) 510 #define MCHP_ACPI_EC_0_OBE_GIRQ_BIT BIT(6) 511 #define MCHP_ACPI_EC_1_IBF_GIRQ_BIT BIT(7) 512 #define MCHP_ACPI_EC_1_OBE_GIRQ_BIT BIT(8) 513 #define MCHP_ACPI_EC_2_IBF_GIRQ_BIT BIT(9) 514 #define MCHP_ACPI_EC_2_OBE_GIRQ_BIT BIT(10) 515 #define MCHP_ACPI_EC_3_IBF_GIRQ_BIT BIT(11) 516 #define MCHP_ACPI_EC_3_OBE_GIRQ_BIT BIT(12) 517 #define MCHP_ACPI_PM1_CTL_GIRQ_BIT BIT(15) 518 #define MCHP_ACPI_PM1_EN_GIRQ_BIT BIT(16) 519 #define MCHP_ACPI_PM1_STS_GIRQ_BIT BIT(17) 520 #define MCHP_KBC_OBE_GIRQ_BIT BIT(18) 521 #define MCHP_KBC_IBF_GIRQ_BIT BIT(19) 522 #define MCHP_MBOX_0_GIRQ_BIT BIT(20) 523 #define MCHP_P80BD_0_GIRQ_BIT BIT(22) 524 #define MCHP_P80BD_1_GIRQ_BIT BIT(23) 525 /* Masks for blocks with multiple instances or sources */ 526 #define MCHP_UART_GIRQ_MASK 0x13u 527 #define MCHP_UART_EMI_GIRQ_MASK 0x0cu 528 #define MCHP_ACPI_EC_GIRQ_MASK 0x01fe0u 529 #define MCHP_ACPI_PM1_GIRQ_MASK 0x38000u 530 #define MCHP_KBC_GIRQ_MASK 0xc0000u 531 #define MCHP_BDP_MASK 0xc00000u 532 #define MCHP_HOST_PERIPH_GIRQ_MASK 0xdf9fffu 533 534 /* GIRQ16 Source, Enable_Set/Clr, Result registers bit positions */ 535 #define MCHP_PK_ERR_GIRQ_BIT BIT(0) 536 #define MCHP_PK_END_GIRQ_BIT BIT(1) 537 #define MCHP_RNG_GIRQ_BIT BIT(2) 538 #define MCHP_AES_GIRQ_BIT BIT(3) 539 #define MCHP_HASH_GIRQ_BIT BIT(4) 540 #define MCHP_CRYPTO_GIRQ_MASK 0x1fu 541 542 /* GIRQ17 Source, Enable_Set/Clr, Result registers bit positions */ 543 #define MCHP_PECI_GIRQ_BIT BIT(0) 544 #define MCHP_TACH_0_GIRQ_BIT BIT(1) 545 #define MCHP_TACH_1_GIRQ_BIT BIT(2) 546 #define MCHP_TACH_2_GIRQ_BIT BIT(3) 547 #define MCHP_TACH_3_GIRQ_BIT BIT(4) 548 #define MCHP_HDMI_CEC_0_GIRQ_BIT BIT(5) 549 #define MCHP_ADC_0_SGL_GIRQ_BIT BIT(8) 550 #define MCHP_ADC_0_RPT_GIRQ_BIT BIT(9) 551 #define MCHP_LED_0_GIRQ_BIT BIT(13) 552 #define MCHP_LED_1_GIRQ_BIT BIT(14) 553 #define MCHP_LED_2_GIRQ_BIT BIT(15) 554 #define MCHP_PHOT_0_GIRQ_BIT BIT(17) 555 /* Masks for blocks with multiple instances or sources */ 556 #define MCHP_TACH_GIRQ_MASK 0x1eu 557 #define MCHP_ADC_GIRQ_MASK 0x300u 558 #define MCHP_LED_GIRQ_MASK 0xe000u 559 #define MCHP_PERIPH_GROUP_1_MASK 0x2e33fu 560 561 /* GIRQ18 Source, Enable_Set/Clr, Result registers bit positions */ 562 #define MCHP_SPIEP_0_GIRQ_BIT BIT(0) 563 #define MCHP_QMSPI_0_GIRQ_BIT BIT(1) 564 #define MCHP_PS2_0_ACT_GIRQ_BIT BIT(10) 565 #define MCHP_PS2_1_ACT_GIRQ_BIT BIT(11) 566 #define MCHP_EERPROMC_0_GIRQ_BIT BIT(13) 567 #define MCHP_CCT_0_CNT_GIRQ_BIT BIT(20) 568 #define MCHP_CCT_0_CAP0_GIRQ_BIT BIT(21) 569 #define MCHP_CCT_0_CAP1_GIRQ_BIT BIT(22) 570 #define MCHP_CCT_0_CAP2_GIRQ_BIT BIT(23) 571 #define MCHP_CCT_0_CAP3_GIRQ_BIT BIT(24) 572 #define MCHP_CCT_0_CAP4_GIRQ_BIT BIT(25) 573 #define MCHP_CCT_0_CAP5_GIRQ_BIT BIT(26) 574 #define MCHP_CCT_0_CMP0_GIRQ_BIT BIT(27) 575 #define MCHP_CCT_0_CMP1_GIRQ_BIT BIT(28) 576 /* Masks for blocks with multiple instances or sources */ 577 #define MCHP_PS2_GIRQ_MASK 0xc00u 578 #define MCHP_CCT_0_GIRQ_MASK 0x1ff00000u 579 #define MCHP_PERIPH_GROUP_2_MASK 0x1ff02c03u 580 581 /* GIRQ19 Source, Enable_Set/Clr, Result registers bit positions */ 582 #define MCHP_ESPI_PC_GIRQ_BIT BIT(0) 583 #define MCHP_ESPI_BM1_GIRQ_BIT BIT(1) 584 #define MCHP_ESPI_BM2_GIRQ_BIT BIT(2) 585 #define MCHP_ESPI_LTR_GIRQ_BIT BIT(3) 586 #define MCHP_ESPI_OOB_UP_GIRQ_BIT BIT(4) 587 #define MCHP_ESPI_OOB_DN_GIRQ_BIT BIT(5) 588 #define MCHP_ESPI_FC_GIRQ_BIT BIT(6) 589 #define MCHP_ESPI_RESET_GIRQ_BIT BIT(7) 590 #define MCHP_ESPI_VWEN_GIRQ_BIT BIT(8) 591 #define MCHP_ESPI_SAF_DONE_GIRQ_BIT BIT(9) 592 #define MCHP_ESPI_SAF_ERR_GIRQ_BIT BIT(10) 593 /* Masks for blocks with multiple instances or sources */ 594 #define MCHP_ESPI_BM_GIRQ_MASK 0x006u 595 #define MCHP_ESPI_OOB_GIRQ_MASK 0x030u 596 #define MCHP_ESPI_SAF_GIRQ_MASK 0x600u 597 #define MCHP_ESPI_GIRQ_MASK 0xfffu 598 599 /* GIRQ20 Source, Enable_Set/Clr, Result registers bit positions */ 600 #define MCHP_STAP_OBF_GIRQ_BIT BIT(0) 601 #define MCHP_STAP_IBF_GIRQ_BIT BIT(1) 602 #define MCHP_STAP_WAKE_GIRQ_BIT BIT(2) 603 #define MCHP_OTP_READY_GIRQ_BIT BIT(3) 604 /* Masks for blocks with multiple instances or sources */ 605 #define MCHP_STAP_GIRQ_MASK 0x007u 606 #define MCHP_PERIPH_GROUP_3_MASK 0x00fu 607 608 /* GIRQ21 Source, Enable_Set/Clr, Result registers bit positions */ 609 #define MCHP_WDT_GIRQ_BIT BIT(2) 610 #define MCHP_WTMR_ALARM_GIRQ_BIT BIT(3) 611 #define MCHP_WTMR_SUBWK_GIRQ_BIT BIT(4) 612 #define MCHP_WTMR_ONESEC_GIRQ_BIT BIT(5) 613 #define MCHP_WTMR_SUBSEC_GIRQ_BIT BIT(6) 614 #define MCHP_WTMR_SPP_GIRQ_BIT BIT(7) 615 #define MCHP_RTC_GIRQ_BIT BIT(8) 616 #define MCHP_RTC_ALARM_GIRQ_BIT BIT(9) 617 #define MCHP_VCI_OVRD_IN_GIRQ_BIT BIT(10) 618 #define MCHP_VCI_IN0_GIRQ_BIT BIT(11) 619 #define MCHP_VCI_IN1_GIRQ_BIT BIT(12) 620 #define MCHP_VCI_IN2_GIRQ_BIT BIT(13) 621 #define MCHP_VCI_IN3_GIRQ_BIT BIT(14) 622 #define MCHP_PS2_0_PORT0A_WK_GIRQ_BIT BIT(18) 623 #define MCHP_PS2_0_PORT0B_WK_GIRQ_BIT BIT(19) 624 #define MCHP_PS2_0_PORT1B_WK_GIRQ_BIT BIT(21) 625 #define MCHP_KEYSCAN_GIRQ_BIT BIT(25) 626 #define MCHP_GLUE_GIRQ_BIT BIT(26) 627 /* Masks for blocks with multiple instances or sources */ 628 #define MCHP_WTMR_GIRQ_MASK 0xf8u 629 #define MCHP_RTC_GIRQ_MASK 0x300u 630 #define MCHP_VCI_GIRQ_MASK 0x7c00u 631 #define MCHP_PS2_PORT_WK_GIRQ_MASK 0x2c0000u 632 #define MCHP_PERIPH_GROUP_4_MASK 0x62c7ffcu 633 634 /* 635 * GIRQ22 Source, Enable_Set/Clr, Result registers bit positions 636 * NOTE: These wake sources allow the peripheral to turn back on clocks 637 * long enough to facilite the data transfer. No interrupt to the EC occurs 638 * unless the peripheral was configured to generate an EC interrupt for 639 * the specific data transfer. 640 */ 641 #define MCHP_SPIEP_WK_CLK_GIRQ_BIT BIT(0) 642 #define MCHP_I2C_SMB_0_WK_CLK_GIRQ_BIT BIT(1) 643 #define MCHP_I2C_SMB_1_WK_CLK_GIRQ_BIT BIT(2) 644 #define MCHP_I2C_SMB_2_WK_CLK_GIRQ_BIT BIT(3) 645 #define MCHP_I2C_SMB_3_WK_CLK_GIRQ_BIT BIT(4) 646 #define MCHP_I2C_SMB_4_WK_CLK_GIRQ_BIT BIT(5) 647 #define MCHP_I2C_0_WK_CLK_GIRQ_BIT BIT(6) 648 #define MCHP_I2C_1_WK_CLK_GIRQ_BIT BIT(7) 649 #define MCHP_I2C_2_WK_CLK_GIRQ_BIT BIT(8) 650 #define MCHP_ESPI_WK_CLK_GIRQ_BIT BIT(9) 651 /* Masks for blocks with multiple instances or sources */ 652 #define MCHP_I2C_SMB_WK_CLK_GIRQ_MASK 0x3eu 653 #define MCHP_I2C_WK_CLK_GIRQ_MASK 0x1c0u 654 #define MCHP_CLK_WK_CLK_GIRQ_MASK 0x3ffu 655 656 /* GIRQ23 Source, Enable_Set/Clr, Result registers bit positions */ 657 #define MCHP_BTMR16_0_GIRQ_BIT BIT(0) 658 #define MCHP_BTMR16_1_GIRQ_BIT BIT(1) 659 #define MCHP_BTMR32_0_GIRQ_BIT BIT(4) 660 #define MCHP_BTMR32_1_GIRQ_BIT BIT(5) 661 #define MCHP_RTMR_0_GIRQ_BIT BIT(10) 662 #define MCHP_RTMR_0_SWI0_GIRQ_BIT BIT(11) 663 #define MCHP_RTMR_0_SWI1_GIRQ_BIT BIT(12) 664 #define MCHP_RTMR_0_SWI2_GIRQ_BIT BIT(13) 665 #define MCHP_RTMR_0_SWI3_GIRQ_BIT BIT(14) 666 #define MCHP_HTMR_0_GIRQ_BIT BIT(16) 667 #define MCHP_HTMR_1_GIRQ_BIT BIT(17) 668 /* Masks for blocks with multiple instances or sources */ 669 #define MCHP_BTMR16_GIRQ_MASK 0x03u 670 #define MCHP_BTMR32_GIRQ_MASK 0x30u 671 #define MCHP_RMTR_GIRQ_MASK 0x7c00u 672 #define MCHP_HTMR_GIRQ_MASK 0x30000u 673 #define MCHP_PERIPH_GROUP_5_GIRQ_MASK 0x37c33u 674 675 /* GIRQ24 Source, Enable_Set/Clr, Result registers bit positions */ 676 #define MCHP_MSVW00_SRC0_GIRQ_BIT BIT(0) 677 #define MCHP_MSVW00_SRC1_GIRQ_BIT BIT(1) 678 #define MCHP_MSVW00_SRC2_GIRQ_BIT BIT(2) 679 #define MCHP_MSVW00_SRC3_GIRQ_BIT BIT(3) 680 #define MCHP_MSVW01_SRC0_GIRQ_BIT BIT(4) 681 #define MCHP_MSVW01_SRC1_GIRQ_BIT BIT(5) 682 #define MCHP_MSVW01_SRC2_GIRQ_BIT BIT(6) 683 #define MCHP_MSVW01_SRC3_GIRQ_BIT BIT(7) 684 #define MCHP_MSVW02_SRC0_GIRQ_BIT BIT(8) 685 #define MCHP_MSVW02_SRC1_GIRQ_BIT BIT(9) 686 #define MCHP_MSVW02_SRC2_GIRQ_BIT BIT(10) 687 #define MCHP_MSVW02_SRC3_GIRQ_BIT BIT(11) 688 #define MCHP_MSVW03_SRC0_GIRQ_BIT BIT(12) 689 #define MCHP_MSVW03_SRC1_GIRQ_BIT BIT(13) 690 #define MCHP_MSVW03_SRC2_GIRQ_BIT BIT(14) 691 #define MCHP_MSVW03_SRC3_GIRQ_BIT BIT(15) 692 #define MCHP_MSVW04_SRC0_GIRQ_BIT BIT(16) 693 #define MCHP_MSVW04_SRC1_GIRQ_BIT BIT(17) 694 #define MCHP_MSVW04_SRC2_GIRQ_BIT BIT(18) 695 #define MCHP_MSVW04_SRC3_GIRQ_BIT BIT(19) 696 #define MCHP_MSVW05_SRC0_GIRQ_BIT BIT(20) 697 #define MCHP_MSVW05_SRC1_GIRQ_BIT BIT(21) 698 #define MCHP_MSVW05_SRC2_GIRQ_BIT BIT(22) 699 #define MCHP_MSVW05_SRC3_GIRQ_BIT BIT(23) 700 #define MCHP_MSVW06_SRC0_GIRQ_BIT BIT(24) 701 #define MCHP_MSVW06_SRC1_GIRQ_BIT BIT(25) 702 #define MCHP_MSVW06_SRC2_GIRQ_BIT BIT(26) 703 #define MCHP_MSVW06_SRC3_GIRQ_BIT BIT(27) 704 /* Masks for blocks with multiple instances or sources */ 705 #define MCHP_MSVW00_GIRQ_MASK 0xfu 706 #define MCHP_MSVW01_GIRQ_MASK 0xf0u 707 #define MCHP_MSVW02_GIRQ_MASK 0xf00u 708 #define MCHP_MSVW03_GIRQ_MASK 0xf000u 709 #define MCHP_MSVW04_GIRQ_MASK 0xf0000u 710 #define MCHP_MSVW05_GIRQ_MASK 0xf00000u 711 #define MCHP_MSVW06_GIRQ_MASK 0xf000000u 712 #define MCHP_MSVW00_06_GIRQ_MASK 0x0fffffffu 713 714 /* GIRQ25 Source, Enable_Set/Clr, Result registers bit positions */ 715 #define MCHP_MSVW07_SRC0_GIRQ_BIT BIT(0) 716 #define MCHP_MSVW07_SRC1_GIRQ_BIT BIT(1) 717 #define MCHP_MSVW07_SRC2_GIRQ_BIT BIT(2) 718 #define MCHP_MSVW07_SRC3_GIRQ_BIT BIT(3) 719 #define MCHP_MSVW08_SRC0_GIRQ_BIT BIT(4) 720 #define MCHP_MSVW08_SRC1_GIRQ_BIT BIT(5) 721 #define MCHP_MSVW08_SRC2_GIRQ_BIT BIT(6) 722 #define MCHP_MSVW08_SRC3_GIRQ_BIT BIT(7) 723 #define MCHP_MSVW09_SRC0_GIRQ_BIT BIT(8) 724 #define MCHP_MSVW09_SRC1_GIRQ_BIT BIT(9) 725 #define MCHP_MSVW09_SRC2_GIRQ_BIT BIT(10) 726 #define MCHP_MSVW09_SRC3_GIRQ_BIT BIT(11) 727 #define MCHP_MSVW10_SRC0_GIRQ_BIT BIT(12) 728 #define MCHP_MSVW10_SRC1_GIRQ_BIT BIT(13) 729 #define MCHP_MSVW10_SRC2_GIRQ_BIT BIT(14) 730 #define MCHP_MSVW10_SRC3_GIRQ_BIT BIT(15) 731 /* Masks for blocks with multiple instances or sources */ 732 #define MCHP_MSVW07_GIRQ_MASK 0xfu 733 #define MCHP_MSVW08_GIRQ_MASK 0xf0u 734 #define MCHP_MSVW09_GIRQ_MASK 0xf00u 735 #define MCHP_MSVW10_GIRQ_MASK 0xf000u 736 #define MCHP_MSVW07_10_GIRQ_MASK 0xffffu 737 738 /* GIRQ26 Source, Enable_Set/Clr, Result registers bit positions */ 739 #define MCHP_GPIO_0240_GIRQ_BIT BIT(0) 740 #define MCHP_GPIO_0241_GIRQ_BIT BIT(1) 741 #define MCHP_GPIO_0242_GIRQ_BIT BIT(2) 742 #define MCHP_GPIO_0243_GIRQ_BIT BIT(3) 743 #define MCHP_GPIO_0244_GIRQ_BIT BIT(4) 744 #define MCHP_GPIO_0245_GIRQ_BIT BIT(5) 745 #define MCHP_GPIO_0246_GIRQ_BIT BIT(6) 746 #define MCHP_GPIO_0250_GIRQ_BIT BIT(8) 747 #define MCHP_GPIO_0253_GIRQ_BIT BIT(11) 748 #define MCHP_GPIO_0254_GIRQ_BIT BIT(12) 749 #define MCHP_GPIO_0255_GIRQ_BIT BIT(13) 750 /* Masks for blocks with multiple instances or sources */ 751 #define MCHP_GPIO_0240_0276_GIRQ_MASK 0x397fu 752 753 #define MCHP_GIRQ_START_NUM 8u 754 #define MCHP_GIRQ_LAST_NUM 26u 755 #define MCHP_GIRQ_IDX(girq) ((uint32_t)(girq) - 8u) 756 #define MCHP_GIRQ_IDX_FIRST 0u 757 #define MCHP_GIRQ_IDX_MAX 19u 758 #define MCHP_MAX_NVIC_IDX 6u 759 760 /** @brief ECIA GIRQn register block. Size = 0x14(20) bytes */ 761 typedef struct girq_regs 762 { 763 __IOM uint32_t SRC; /* R/W1C source status bits */ 764 __IOM uint32_t EN_SET; /* R/W1S Write 1 to set enable(s) */ 765 __IOM uint32_t RESULT; /* R/O equals SRC AND EN_SET */ 766 __IOM uint32_t EN_CLR; /* R/W1S Write 1 to clear enable(s) */ 767 uint8_t RSVD1[4]; 768 } GIRQ_Type; 769 770 /** @brief EC Interrupt Aggregator (ECIA) */ 771 typedef struct ecia_regs 772 { /*!< (@ 0x4000e000) ECIA Structure */ 773 union { 774 struct { 775 GIRQ_Type GIRQ08; /*!< (@ 0x0000) GIRQ08 registers */ 776 GIRQ_Type GIRQ09; /*!< (@ 0x0014) GIRQ09 registers */ 777 GIRQ_Type GIRQ10; /*!< (@ 0x0028) GIRQ10 registers */ 778 GIRQ_Type GIRQ11; /*!< (@ 0x003c) GIRQ11 registers */ 779 GIRQ_Type GIRQ12; /*!< (@ 0x0050) GIRQ12 registers */ 780 GIRQ_Type GIRQ13; /*!< (@ 0x0064) GIRQ13 registers */ 781 GIRQ_Type GIRQ14; /*!< (@ 0x0078) GIRQ14 registers */ 782 GIRQ_Type GIRQ15; /*!< (@ 0x008c) GIRQ15 registers */ 783 GIRQ_Type GIRQ16; /*!< (@ 0x00a0) GIRQ16 registers */ 784 GIRQ_Type GIRQ17; /*!< (@ 0x00b4) GIRQ17 registers */ 785 GIRQ_Type GIRQ18; /*!< (@ 0x00c8) GIRQ18 registers */ 786 GIRQ_Type GIRQ19; /*!< (@ 0x00dc) GIRQ19 registers */ 787 GIRQ_Type GIRQ20; /*!< (@ 0x00f0) GIRQ20 registers */ 788 GIRQ_Type GIRQ21; /*!< (@ 0x0104) GIRQ21 registers */ 789 GIRQ_Type GIRQ22; /*!< (@ 0x0118) GIRQ22 registers */ 790 GIRQ_Type GIRQ23; /*!< (@ 0x012c) GIRQ23 registers */ 791 GIRQ_Type GIRQ24; /*!< (@ 0x0140) GIRQ24 registers */ 792 GIRQ_Type GIRQ25; /*!< (@ 0x0154) GIRQ25 registers */ 793 GIRQ_Type GIRQ26; /*!< (@ 0x0168) GIRQ26 registers */ 794 }; 795 GIRQ_Type GIRQ[19]; 796 }; 797 uint8_t RSVD2[(0x0200u - 0x017cu)]; /* offsets 0x017c - 0x1ff */ 798 __IOM uint32_t BLK_EN_SET; /*! (@ 0x00000200) Aggregated GIRQ output Enable Set */ 799 __IOM uint32_t BLK_EN_CLR; /*! (@ 0x00000204) Aggregated GIRQ output Enable Clear */ 800 __IM uint32_t BLK_ACTIVE; /*! (@ 0x00000204) GIRQ Active bitmap (RO) */ 801 } ECIA_Type; 802 803 #endif /* #ifndef _ECIA_H */ 804 /* end ecia.h */ 805 /** @} 806 */ 807
