1 /** 2 * \file 3 * 4 * \brief Component description for CCL 5 * 6 * Copyright (c) 2016 Atmel Corporation, 7 * a wholly owned subsidiary of Microchip Technology Inc. 8 * 9 * \asf_license_start 10 * 11 * \page License 12 * 13 * Licensed under the Apache License, Version 2.0 (the "License"); 14 * you may not use this file except in compliance with the License. 15 * You may obtain a copy of the Licence at 16 * 17 * http://www.apache.org/licenses/LICENSE-2.0 18 * 19 * Unless required by applicable law or agreed to in writing, software 20 * distributed under the License is distributed on an "AS IS" BASIS, 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 * See the License for the specific language governing permissions and 23 * limitations under the License. 24 * 25 * \asf_license_stop 26 * 27 */ 28 29 #ifndef _SAML21_CCL_COMPONENT_ 30 #define _SAML21_CCL_COMPONENT_ 31 32 /* ========================================================================== */ 33 /** SOFTWARE API DEFINITION FOR CCL */ 34 /* ========================================================================== */ 35 /** \addtogroup SAML21_CCL Configurable Custom Logic */ 36 /*@{*/ 37 38 #define CCL_U2225 39 #define REV_CCL 0x101 40 41 /* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 46 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 47 uint8_t :4; /*!< bit: 2.. 5 Reserved */ 48 uint8_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ 49 uint8_t :1; /*!< bit: 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } CCL_CTRL_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 #define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ 56 #define CCL_CTRL_RESETVALUE _U(0x00) /**< \brief (CCL_CTRL reset_value) Control */ 57 58 #define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ 59 #define CCL_CTRL_SWRST (_U(0x1) << CCL_CTRL_SWRST_Pos) 60 #define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ 61 #define CCL_CTRL_ENABLE (_U(0x1) << CCL_CTRL_ENABLE_Pos) 62 #define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run during Standby */ 63 #define CCL_CTRL_RUNSTDBY (_U(0x1) << CCL_CTRL_RUNSTDBY_Pos) 64 #define CCL_CTRL_MASK _U(0x43) /**< \brief (CCL_CTRL) MASK Register */ 65 66 /* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { 69 struct { 70 uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ 71 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 72 } bit; /*!< Structure used for bit access */ 73 uint8_t reg; /*!< Type used for register access */ 74 } CCL_SEQCTRL_Type; 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 #define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ 78 #define CCL_SEQCTRL_RESETVALUE _U(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ 79 80 #define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ 81 #define CCL_SEQCTRL_SEQSEL_Msk (_U(0xF) << CCL_SEQCTRL_SEQSEL_Pos) 82 #define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) 83 #define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ 84 #define CCL_SEQCTRL_SEQSEL_DFF_Val _U(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ 85 #define CCL_SEQCTRL_SEQSEL_JK_Val _U(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ 86 #define CCL_SEQCTRL_SEQSEL_LATCH_Val _U(0x3) /**< \brief (CCL_SEQCTRL) D latch */ 87 #define CCL_SEQCTRL_SEQSEL_RS_Val _U(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ 88 #define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) 89 #define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) 90 #define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) 91 #define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) 92 #define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) 93 #define CCL_SEQCTRL_MASK _U(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ 94 95 /* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ 96 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 97 typedef union { 98 struct { 99 uint32_t :1; /*!< bit: 0 Reserved */ 100 uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ 101 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 102 uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ 103 uint32_t :1; /*!< bit: 6 Reserved */ 104 uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ 105 uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ 106 uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ 107 uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ 108 uint32_t INVEI:1; /*!< bit: 20 Input Event Invert */ 109 uint32_t LUTEI:1; /*!< bit: 21 Event Input Enable */ 110 uint32_t LUTEO:1; /*!< bit: 22 Event Output Enable */ 111 uint32_t :1; /*!< bit: 23 Reserved */ 112 uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ 113 } bit; /*!< Structure used for bit access */ 114 uint32_t reg; /*!< Type used for register access */ 115 } CCL_LUTCTRL_Type; 116 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 117 118 #define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ 119 #define CCL_LUTCTRL_RESETVALUE _U(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ 120 121 #define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ 122 #define CCL_LUTCTRL_ENABLE (_U(0x1) << CCL_LUTCTRL_ENABLE_Pos) 123 #define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ 124 #define CCL_LUTCTRL_FILTSEL_Msk (_U(0x3) << CCL_LUTCTRL_FILTSEL_Pos) 125 #define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) 126 #define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ 127 #define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ 128 #define CCL_LUTCTRL_FILTSEL_FILTER_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ 129 #define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) 130 #define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) 131 #define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) 132 #define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ 133 #define CCL_LUTCTRL_EDGESEL (_U(0x1) << CCL_LUTCTRL_EDGESEL_Pos) 134 #define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ 135 #define CCL_LUTCTRL_INSEL0_Msk (_U(0xF) << CCL_LUTCTRL_INSEL0_Pos) 136 #define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) 137 #define CCL_LUTCTRL_INSEL0_MASK_Val _U(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ 138 #define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ 139 #define CCL_LUTCTRL_INSEL0_LINK_Val _U(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ 140 #define CCL_LUTCTRL_INSEL0_EVENT_Val _U(0x3) /**< \brief (CCL_LUTCTRL) Event in put source */ 141 #define CCL_LUTCTRL_INSEL0_IO_Val _U(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ 142 #define CCL_LUTCTRL_INSEL0_AC_Val _U(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ 143 #define CCL_LUTCTRL_INSEL0_TC_Val _U(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ 144 #define CCL_LUTCTRL_INSEL0_ALTTC_Val _U(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ 145 #define CCL_LUTCTRL_INSEL0_TCC_Val _U(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ 146 #define CCL_LUTCTRL_INSEL0_SERCOM_Val _U(0x9) /**< \brief (CCL_LUTCTRL) SERCOM inout source */ 147 #define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) 148 #define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) 149 #define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) 150 #define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) 151 #define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) 152 #define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) 153 #define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) 154 #define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) 155 #define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) 156 #define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) 157 #define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ 158 #define CCL_LUTCTRL_INSEL1_Msk (_U(0xF) << CCL_LUTCTRL_INSEL1_Pos) 159 #define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) 160 #define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ 161 #define CCL_LUTCTRL_INSEL2_Msk (_U(0xF) << CCL_LUTCTRL_INSEL2_Pos) 162 #define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) 163 #define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Input Event Invert */ 164 #define CCL_LUTCTRL_INVEI (_U(0x1) << CCL_LUTCTRL_INVEI_Pos) 165 #define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) Event Input Enable */ 166 #define CCL_LUTCTRL_LUTEI (_U(0x1) << CCL_LUTCTRL_LUTEI_Pos) 167 #define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) Event Output Enable */ 168 #define CCL_LUTCTRL_LUTEO (_U(0x1) << CCL_LUTCTRL_LUTEO_Pos) 169 #define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ 170 #define CCL_LUTCTRL_TRUTH_Msk (_U(0xFF) << CCL_LUTCTRL_TRUTH_Pos) 171 #define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) 172 #define CCL_LUTCTRL_MASK _U(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ 173 174 /** \brief CCL hardware registers */ 175 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 176 typedef struct { 177 __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ 178 RoReg8 Reserved1[0x3]; 179 __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ 180 RoReg8 Reserved2[0x2]; 181 __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ 182 } Ccl; 183 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 184 185 /*@}*/ 186 187 #endif /* _SAML21_CCL_COMPONENT_ */ 188
