1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file peci.h 28 *MEC1501 Analog to Digital Converter registers 29 */ 30 /** @defgroup MEC1501 Peripherals ADC 31 */ 32 33 #ifndef _ADC_H 34 #define _ADC_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /* =========================================================================*/ 42 /* ================ ADC =========== */ 43 /* =========================================================================*/ 44 45 #define MCHP_ADC_BASE_ADDR 0x40007c00u 46 47 /* 48 * ADC block implements two interrupt signals: 49 * single conversion and repeat conversion done. 50 */ 51 #define MCHP_ADC_GIRQ 17u 52 53 /* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */ 54 #define MCHP_ADC_SNG_DONE_GIRQ_POS 8 55 #define MCHP_ADC_RPT_DONE_GIRQ_POS 9 56 57 #define MCHP_ADC_SNG_DONE_GIRQ_VAL BIT(MCHP_ADC_SNG_DONE_GIRQ_POS) 58 #define MCHP_ADC_RPT_DONE_GIRQ_VAL BIT(MCHP_ADC_RPT_DONE_GIRQ_POS) 59 60 /* ADC GIRQ aggregated NVIC input */ 61 #define MCHP_ADC_SNG_DONE_NVIC_AGGR 9u 62 #define MCHP_ADC_RPT_DONE_NVIC_AGGR 9u 63 64 /* ADC direct NVIC inputs */ 65 #define MCHP_ADC_SNG_DONE_NVIC_DIRECT 78u 66 #define MCHP_ADC_RPT_DONE_NVIC_DIRECT 79u 67 68 /* Eight ADC channels numbered 0 - 7 */ 69 #define MCHP_ADC_MAX_CHAN 8u 70 #define MCHP_ADC_MAX_CHAN_MASK 0x07u 71 72 /* Control register */ 73 #define MCHP_ADC_CTRL_REG_OFS 0u 74 #define MCHP_ADC_CTRL_REG_MASK 0xdfu 75 #define MCHP_ADC_CTRL_REG_RW_MASK 0x1fu 76 #define MCHP_ADC_CTRL_REG_RW1C_MASK 0xc0u 77 #define MCHP_ADC_CTRL_ACTV BIT(0) 78 #define MCHP_ADC_CTRL_START_SNGL BIT(1) 79 #define MCHP_ADC_CTRL_START_RPT BIT(2) 80 #define MCHP_ADC_CTRL_PWRSV_DIS BIT(3) 81 #define MCHP_ADC_CTRL_SRST BIT(4) 82 #define MCHP_ADC_CTRL_RPT_DONE_STS BIT(6) /* R/W1C */ 83 #define MCHP_ADC_CTRL_SNGL_DONE_STS BIT(7) /* R/W1C */ 84 85 /* Delay register. Start and repeat delays in units of 40 us */ 86 #define MCHP_ADC_DELAY_REG_OFS 4u 87 #define MCHP_ADC_DELAY_REG_MASK 0xffffffffu 88 #define MCHP_ADC_DELAY_START_POS 0u 89 #define MCHP_ADC_DELAY_START_MASK 0xffffu 90 #define MCHP_ADC_DELAY_RPT_POS 16u 91 #define MCHP_ADC_DELAY_RPT_MASK 0xffff0000u 92 93 /* Status register. 0 <= n < MCHP_ADC_MAX_CHAN */ 94 #define MCHP_ADC_STATUS_REG_OFS 8u 95 #define MCHP_ADC_STATUS_REG_MASK 0xffffu 96 #define MCHP_ADC_STATUS_CHAN(n) BIT(n) 97 98 /* Single Conversion Select register */ 99 #define MCHP_ADC_SCS_REG_OFS 0x0cu 100 #define MCHP_ADC_SCS_REG_MASK 0xffu 101 #define MCHP_ADC_SCS_CH_0_7 0xffu 102 #define MCHP_ADC_SCS_CH(n) BIT((n) & 0x07) 103 104 /* Repeat Conversion Select register */ 105 #define MCHP_ADC_RCS_REG_OFS 0x10u 106 #define MCHP_ADC_RCS_REG_MASK 0xffu 107 #define MCHP_ADC_RCS_CH_0_7 0xffu 108 #define MCHP_ADC_RCS_CH(n) BIT((n) & 0x07) 109 110 /* Channel reading registers */ 111 #define MCHP_ADC_RDCH_REG_MASK 0xfffu 112 #define MCHP_ADC_RDCH0_REG_OFS 0x14 113 #define MCHP_ADC_RDCH1_REG_OFS 0x18 114 #define MCHP_ADC_RDCH2_REG_OFS 0x1c 115 #define MCHP_ADC_RDCH3_REG_OFS 0x20 116 #define MCHP_ADC_RDCH4_REG_OFS 0x24 117 #define MCHP_ADC_RDCH5_REG_OFS 0x28 118 #define MCHP_ADC_RDCH6_REG_OFS 0x2c 119 #define MCHP_ADC_RDCH7_REG_OFS 0x30 120 121 /* Configuration register */ 122 #define MCHP_ADC_CFG_REG_OFS 0x7cu 123 #define MCHP_ADC_CFG_REG_MASK 0xffffu 124 #define MCHP_ADC_CFG_CLK_LO_TIME_POS 0 125 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK0 0xffu 126 #define MCHP_ADC_CFG_CLK_LO_TIME_MASK 0xffu 127 #define MCHP_ADC_CFG_CLK_HI_TIME_POS 8 128 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK0 0xffu 129 #define MCHP_ADC_CFG_CLK_HI_TIME_MASK (0xffu << 8) 130 131 /* Channel Vref Select register */ 132 #define MCHP_ADC_CH_VREF_SEL_REG_OFS 0x80u 133 #define MCHP_ADC_CH_VREF_SEL_REG_MASK 0x00ffffffu 134 #define MCHP_ADC_CH_VREF_SEL_MASK(n) (0x03u << (((n) & 0x07) << 1)) 135 #define MCHP_ADC_CH_VREF_SEL_PAD(n) 0u 136 #define MCHP_ADC_CH_VREF_SEL_GPIO(n) (0x01u << (((n) & 0x07) << 1)) 137 138 /* Vref Control register */ 139 #define MCHP_ADC_VREF_CTRL_REG_OFS 0x84u 140 #define MCHP_ADC_VREF_CTRL_REG_MASK 0xffffffffu 141 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_POS 0 142 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK0 0xffffu 143 #define MCHP_ADC_VREF_CTRL_CHRG_DEL_MASK 0xffffu 144 #define MCHP_ADC_VREF_CTRL_SW_DEL_POS 16 145 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK0 0x1fffu 146 #define MCHP_ADC_VREF_CTRL_SW_DEL_MASK (0x1fffu << 16) 147 #define MCHP_ADC_VREF_CTRL_PAD_POS 29 148 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_FLOAT 0 149 #define MCHP_ADC_VREF_CTRL_PAD_UNUSED_DRIVE_LO BIT(29) 150 #define MCHP_ADC_VREF_CTRL_SEL_STS_POS 30 151 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK0 0x03u 152 #define MCHP_ADC_VREF_CTRL_SEL_STS_MASK (0x03u << 30) 153 154 /* SAR ADC Control register */ 155 #define MCHP_ADC_SAR_CTRL_REG_OFS 0x88u 156 #define MCHP_ADC_SAR_CTRL_REG_MASK 0x0001ff8fu 157 /* Select single ended or differential operation */ 158 #define MCHP_ADC_SAR_CTRL_SELDIFF_POS 0 159 #define MCHP_ADC_SAR_CTRL_SELDIFF_DIS 0 160 #define MCHP_ADC_SAR_CTRL_SELDIFF_EN BIT(0) 161 /* Select resolution */ 162 #define MCHP_ADC_SAR_CTRL_RES_POS 1 163 #define MCHP_ADC_SAR_CTRL_RES_MASK0 0x03u 164 #define MCHP_ADC_SAR_CTRL_RES_MASK (0x03u << 1) 165 #define MCHP_ADC_SAR_CTRL_RES_10_BITS (0x02u << 1) 166 #define MCHP_ADC_SAR_CTRL_RES_12_BITS (0x03u << 1) 167 /* Shift data in reading register */ 168 #define MCHP_ADC_SAR_CTRL_SHIFTD_POS 3 169 #define MCHP_ADC_SAR_CTRL_SHIFTD_DIS 0 170 #define MCHP_ADC_SAR_CTRL_SHIFTD_EN BIT(3) 171 /* Warm up delay in ADC clock cycles */ 172 #define MCHP_ADC_SAR_CTRL_WUP_DLY_POS 7 173 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK0 0x3ffu 174 #define MCHP_ADC_SAR_CTRL_WUP_DLY_MASK (0x3ffu << 7) 175 #define MCHP_ADC_SAR_CTRL_WUP_DLY_DFLT (0x202u << 7) 176 177 /* Register interface */ 178 #define MCHP_ADC_CH_NUM(n) ((n) & MCHP_ADC_MAX_CHAN_MASK) 179 #define MCHP_ADC_CH_OFS(n) (MCHP_ADC_CH_NUM(n) << 2) 180 #define MCHP_ADC_CH_ADDR(n) (MCHP_ADC_BASE_ADDR + MCHP_ADC_CH_OFS(n)) 181 182 #define MCHP_ADC_RD_CHAN(n) REG32(MCHP_ADC_CH_ADDR(n)) 183 184 /** 185 * @brief Analog to Digital Converter Registers (ADC) 186 */ 187 typedef struct adc_regs { 188 __IOM uint32_t CONTROL; /*!< (@ 0x0000) ADC Control */ 189 __IOM uint32_t DELAY; /*!< (@ 0x0004) ADC Delay */ 190 __IOM uint32_t STATUS; /*!< (@ 0x0008) ADC Status */ 191 __IOM uint32_t SINGLE; /*!< (@ 0x000C) ADC Single */ 192 __IOM uint32_t REPEAT; /*!< (@ 0x0010) ADC Repeat */ 193 __IOM uint32_t RDCH0; /*!< (@ 0x0014) ADC Chan0 Reading */ 194 __IOM uint32_t RDCH1; /*!< (@ 0x0018) ADC Chan1 Reading */ 195 __IOM uint32_t RDCH2; /*!< (@ 0x001C) ADC Chan2 Reading */ 196 __IOM uint32_t RDCH3; /*!< (@ 0x0020) ADC Chan3 Reading */ 197 __IOM uint32_t RDCH4; /*!< (@ 0x0024) ADC Chan4 Reading */ 198 __IOM uint32_t RDCH5; /*!< (@ 0x0028) ADC Chan5 Reading */ 199 __IOM uint32_t RDCH6; /*!< (@ 0x002C) ADC Chan6 Reading */ 200 __IOM uint32_t RDCH7; /*!< (@ 0x0030) ADC Chan7 Reading */ 201 uint8_t RSVD1[0x7C - 0x34]; 202 __IOM uint32_t CONFIG; /*!< (@ 0x007C) ADC Configuration */ 203 __IOM uint32_t VREF_CHAN_SEL; /*!< (@ 0x0080) ADC Vref Channel Sel. */ 204 __IOM uint32_t VREF_CTRL; /*!< (@ 0x0084) ADC Vref Control */ 205 __IOM uint32_t SARADC_CTRL; /*!< (@ 0x0088) SAR ARD Control */ 206 } ADC_Type; 207 208 #endif /* #ifndef _ADC_H */ 209 /* end adc.h */ 210 /** @} 211 */ 212
