1 /* 2 * Copyright (c) 2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 */ 7 8 #ifndef __TARGET_CFG_COMMON_H__ 9 #define __TARGET_CFG_COMMON_H__ 10 11 #include <stdint.h> 12 #include <stddef.h> 13 #include "target_cfg.h" 14 #include "tfm_plat_defs.h" 15 16 /** 17 * \brief Holds the data necessary to do isolation for a specific peripheral. 18 */ 19 struct platform_data_t 20 { 21 uint32_t periph_start; 22 uint32_t periph_limit; 23 ppc_bank_t periph_ppc_bank; 24 int16_t periph_ppc_mask; 25 }; 26 27 /** 28 * \brief Store the addresses of memory regions 29 */ 30 struct memory_region_limits { 31 uint32_t non_secure_code_start; 32 uint32_t non_secure_partition_base; 33 uint32_t non_secure_partition_limit; 34 uint32_t veneer_base; 35 uint32_t veneer_limit; 36 #ifdef BL2 37 uint32_t secondary_partition_base; 38 uint32_t secondary_partition_limit; 39 #endif /* BL2 */ 40 }; 41 42 /** 43 * \brief Clear MPC interrupt. 44 */ 45 void mpc_clear_irq(void); 46 47 /** 48 * \brief Clears PPC interrupt. 49 */ 50 void ppc_clear_irq(void); 51 52 /** 53 * \brief Configures SAU and IDAU. 54 */ 55 void sau_and_idau_cfg(void); 56 57 /** 58 * \brief Configures the Memory Protection Controller. 59 * 60 * \return Returns error code. 61 */ 62 enum tfm_plat_err_t mpc_init_cfg(void); 63 64 /** 65 * \brief Configures the Peripheral Protection Controller. 66 */ 67 enum tfm_plat_err_t ppc_init_cfg(void); 68 69 /** 70 * \brief Restict peripheral access to secure access only 71 * 72 * \note The function does not configure privilege 73 */ 74 void ppc_configure_to_secure(ppc_bank_t bank, uint32_t pos); 75 76 /** 77 * \brief Allow non-secure access to peripheral 78 * 79 * \note The function does not configure privilege 80 */ 81 void ppc_configure_to_non_secure(ppc_bank_t bank, uint32_t pos); 82 83 /** 84 * \brief Enable secure unprivileged access to peripheral 85 */ 86 void ppc_en_secure_unpriv(ppc_bank_t bank, uint32_t pos); 87 88 /** 89 * \brief Clear secure unprivileged access to peripheral 90 */ 91 void ppc_clr_secure_unpriv(ppc_bank_t bank, uint32_t pos); 92 93 /** 94 * \brief Enables the fault handlers BusFault, UsageFault, 95 * MemManageFault and SecureFault. 96 */ 97 enum tfm_plat_err_t enable_fault_handlers(void); 98 99 /** 100 * \brief Configures the system reset request properties 101 * 102 * \return Returns values as specified by the \ref tfm_plat_err_t 103 */ 104 enum tfm_plat_err_t system_reset_cfg(void); 105 106 /** 107 * \brief Configures all external interrupts to target the 108 * NS state, apart for the ones associated to secure 109 * peripherals (plus MPC and PPC) 110 * 111 * \return Returns values as specified by the \ref tfm_plat_err_t 112 */ 113 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 114 115 /** 116 * \brief This function enable the interrupts associated 117 * to the secure peripherals (plus MPC and PPC) 118 * 119 * \return Returns values as specified by the \ref tfm_plat_err_t 120 */ 121 enum tfm_plat_err_t nvic_interrupt_enable(void); 122 123 /** 124 * \brief Configures the system debug properties. 125 * 126 * \return Returns values as specified by the \ref tfm_plat_err_t 127 */ 128 enum tfm_plat_err_t init_debug(void); 129 130 /** 131 * \brief Returns platform's MMIO list and length, defined in 132 * tfm_peripherals_def.c file. 133 */ 134 void get_partition_named_mmio_list(const uintptr_t** list, size_t* length); 135 136 #endif /* __TARGET_CFG_COMMON_H__ */ 137
