1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * @file mss_io_config.h 12 * @author Microchip-FPGA Embedded Systems Solutions 13 * @brief MSS IO related code 14 * 15 */ 16 17 #ifndef xUSER_CONFIG_MSS_DDRC_MSS_IO_CONFIG_H_ 18 #define xUSER_CONFIG_MSS_DDRC_MSS_IO_CONFIG_H_ 19 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /* 26 * fields of LIBERO_SETTING_MSSIO_CONFIGURATION_OPTIONS 27 * */ 28 #define EMMC_CONFIGURED_MASK (0x01U<<0U) /*!< set => eMMC is configured */ 29 #define SD_CONFIGURED_MASK (0x01U<<1U) /*!< set => SD is configured */ 30 #define DEFAULT_ON_START_MASK (0x01U<<2U) /*!< set => default is SD config, not set default is eMMC config */ 31 32 #define ICICLE_KIT_REF_DESIGN_FPGS_SWITCH_ADDRESS 0x4f000000 33 34 typedef enum MSSIO_CONFIG_OPTION_ 35 { 36 DEFAULT_MSSIO_CONFIGURATION = 0x00, /*!< 0 default behavior */ 37 ALT_MSSIO_CONFIGURATION = 0x01, /*!< 1 alternate config */ 38 } MSSIO_CONFIG_OPTION; 39 40 typedef enum MSS_IO_OPTIONS_ 41 { 42 NO_SUPPORT_MSSIO_CONFIGURATION = 0x00, /*!< 0 MSS Configurator version too early */ 43 NOT_SETUP_MSSIO_CONFIGURATION = 0x01, /*!< 0 none configured */ 44 SD_MSSIO_CONFIGURATION = 0x02, /*!< 0 SD config */ 45 EMMC_MSSIO_CONFIGURATION = 0x03, /*!< 1 eMMC config */ 46 } MSS_IO_OPTIONS; 47 48 /* 49 * There are 38 general purpose IO pads, referred to as MSSIO, to support 50 * peripheral devices. System registers will select which signals are connected 51 * to the IO pads. These are in addition to the SGMII IO for the Ethernet MACs, 52 * DDR I/O and two IOs to allow interfacing to an external 32kHz crystal. All 53 * of these MSSIOs are bonded out to pins in all packages. The MSSIOs may be 54 * configured as the IOs of any of the MSS peripherals listed in the table 55 * below. 56 */ 57 58 /* 59 - MUX -> PAD options set by Libero, register iomux1_cr to iomux5_cr 60 | option | value | Info | 61 |:-------------:|:-------------:|:-----:| 62 | SD_SDIO | 0x0 | | 63 | EMMC | 0x1 | | 64 | QSPI | 0x2 | | 65 | SPI | 0x3 | | 66 | USB | 0x4 | | 67 | MMUART | 0x5 | | 68 | I2C | 0x6 | | 69 | CAN | 0x7 | | 70 | MDIO | 0x8 | | 71 | Miscellaneous | 0x9 | | 72 | Reservedx | 0xA | | 73 | GPIO_PAD | 0xB | | 74 | Fabric_test | 0xC | | 75 | Logic_0 | 0xD | | 76 | Logic_1 | 0xE | | 77 | Tristate | 0xF |Default| 78 */ 79 80 /** 81 * \brief IOMUX configuration 82 */ 83 typedef struct IOMUX_CONFIG_ { 84 __IO uint32_t iomux0_cr; /* peripheral is connected to the Fabric or 85 IOMUX structure */ 86 __IO uint32_t iomux1_cr; /* BNK4 SDV PAD 0 to 7 */ 87 __IO uint32_t iomux2_cr; /* BNK4 SDV PAD 8 to 13 */ 88 __IO uint32_t iomux3_cr; /* BNK2 SDV PAD 14 to 21 */ 89 __IO uint32_t iomux4_cr; /* BNK2 SDV PAD 22 to 29 */ 90 __IO uint32_t iomux5_cr; /* BNK2 PAD 30 to 37 */ 91 __IO uint32_t iomux6_cr; /* MMC/SD Voltage select lines are inverted on 92 entry to the IOMUX structure */ 93 } IOMUX_CONFIG; 94 95 96 97 /* 98 pcode, ncode and drive strength for each bank is set using direct writes to 99 the SCB registers 100 101 The MSS IO pad configuration is provided by nineteen system registers 102 each configuring two IO's using 15-bits per IO 103 Theses registers are located in the MSS sysreg. 104 105 - (mssio_bank*_io_cfg_*_*_cr). 106 107 | mssio_bank*_io_cfg_*_*_cr | offset | info | 108 | field | | info | 109 |:-------------------------:|:-------------:|:-----| 110 | io_cfg_ibufmd_0 |0 | | 111 | io_cfg_ibufmd_1 |1 | | 112 | io_cfg_ibufmd_2 |2 | | 113 | io_cfg_drv_0 |3 | | 114 | Io_cfg_drv_1 |4 | | 115 | Io_cfg_drv_2 |5 | | 116 | io_cfg_drv_3 |6 | | 117 | io_cfg_clamp |7 | | 118 | io_cfg_enhyst |8 | | 119 | io_cfg_lockdn_en |9 | | 120 | io_cfg_wpd |10 | | 121 | io_cfg_wpu |11 | | 122 | io_cfg_atp_en |12 | | 123 | io_cfg_lp_persist_en |13 | | 124 | io_cfg_lp_bypass_en |14 | | 125 126 */ 127 128 /** 129 * \brief Bank 2 and 4 voltage settings 130 * 131 */ 132 typedef struct HSS_MSSIO_Bank_Config_ { 133 __IO uint32_t mssio_bank4_pcode_ncode_vs; /* bank 4- set pcode, ncode and 134 drive strength */ 135 __IO uint32_t mssio_bank2_pcode_ncode_vs; /* bank 2- set pcode, ncode and 136 drive strength */ 137 }MSSIO_BANK_CONFIG; 138 139 /** 140 * \brief MSS IO Bank 4 configuration 141 */ 142 typedef struct MSSIO_Bank4_IO_Config_ { 143 __IO uint32_t mssio_bank4_io_cfg_0_cr; /* x_vddi Ratio Rx<0-2> == 001 144 drv<3-6> == 1111 145 7:clamp == 0 146 enhyst == 0 147 lockdn_en == 1 148 10:wpd == 0 149 atp_en`== 0 150 lpmd_ibuf == 0 151 lpmd_obuf == 0 152 persist == 0 153 */ 154 __IO uint32_t mssio_bank4_io_cfg_1_cr; 155 __IO uint32_t mssio_bank4_io_cfg_2_cr; 156 __IO uint32_t mssio_bank4_io_cfg_3_cr; 157 __IO uint32_t mssio_bank4_io_cfg_4_cr; 158 __IO uint32_t mssio_bank4_io_cfg_5_cr; 159 __IO uint32_t mssio_bank4_io_cfg_6_cr; 160 161 }MSSIO_BANK4_CONFIG; 162 163 /** 164 * \brief MSS IO Bank 2 configuration 165 */ 166 typedef struct MSSIO_Bank2_IO_Config_ { 167 __IO uint32_t mssio_bank2_io_cfg_0_cr; /* x_vddi Ratio Rx<0-2> == 001 168 drv<3-6> == 1111 169 7:clamp == 0 170 enhyst == 0 171 lockdn_en == 1 172 10:wpd == 0 173 atp_en`== 0 174 lpmd_ibuf == 0 175 lpmd_obuf == 0 176 persist == 0 177 */ 178 __IO uint32_t mssio_bank2_io_cfg_1_cr; 179 __IO uint32_t mssio_bank2_io_cfg_2_cr; 180 __IO uint32_t mssio_bank2_io_cfg_3_cr; 181 __IO uint32_t mssio_bank2_io_cfg_4_cr; 182 __IO uint32_t mssio_bank2_io_cfg_5_cr; 183 __IO uint32_t mssio_bank2_io_cfg_6_cr; 184 __IO uint32_t mssio_bank2_io_cfg_7_cr; 185 __IO uint32_t mssio_bank2_io_cfg_8_cr; 186 __IO uint32_t mssio_bank2_io_cfg_9_cr; 187 __IO uint32_t mssio_bank2_io_cfg_10_cr; 188 __IO uint32_t mssio_bank2_io_cfg_11_cr; 189 }MSSIO_BANK2_CONFIG; 190 191 192 /***************************************************************************//** 193 The int32_t mssio_setup(void)() 194 195 Setup the IOMUX and IO bank 2 and 4. 196 The values used in this function are set by Libero. 197 It configures the I/O mux, which detemines what peripherals are connected to 198 what pins, and the electrical properties of each bank and each I/O. 199 200 @return 201 This function returns status, 0 => OK 202 203 Example: 204 @code 205 206 error |= mssio_setup(); 207 208 @endcode 209 210 */ 211 uint8_t 212 mssio_setup 213 ( 214 void 215 ); 216 217 218 /***************************************************************************//** 219 The gpio_toggle_test(void)() 220 221 Toggle a GPIO PIN on start-up 222 223 @return 224 This function returns status, 0 => OK 225 226 Example: 227 @code 228 229 error |= mssio_setup(); 230 231 @endcode 232 233 */ 234 int32_t 235 gpio_toggle_test 236 ( 237 void 238 ); 239 240 /***************************************************************************//** 241 set_bank2_and_bank4_volts() 242 Sets bank 2 and 4 voltages, with Values coming from Libero 243 244 Example: 245 246 @code 247 248 set_bank2_and_bank4_volts(); 249 250 @endcode 251 252 * 253 */ 254 void 255 set_bank2_and_bank4_volts 256 ( 257 MSSIO_CONFIG_OPTION config 258 ); 259 260 261 /***************************************************************************//** 262 switch_mssio_config() 263 switches as instructed SD/eMMC 264 265 Example: 266 267 @code 268 269 ASSERT(mss_does_xml_ver_support_switch() == true) 270 271 if ( switch_mssio_config(EMMC_MSSIO_CONFIGURATION) == false ) 272 { 273 while(1u); 274 } 275 switch_external_mux(EMMC_MSSIO_CONFIGURATION); 276 g_mmc.clk_rate = MSS_MMC_CLOCK_200MHZ; 277 g_mmc.card_type = MSS_MMC_CARD_TYPE_MMC; 278 g_mmc.bus_speed_mode = MSS_MMC_MODE_HS200; 279 g_mmc.data_bus_width = MSS_MMC_DATA_WIDTH_4BIT; 280 g_mmc.bus_voltage = MSS_MMC_1_8V_BUS_VOLTAGE; 281 282 @endcode 283 284 * 285 */ 286 uint8_t 287 switch_mssio_config 288 ( 289 MSS_IO_OPTIONS option 290 ) 291 ; 292 293 /***************************************************************************//** 294 mss_does_xml_ver_support_switch() 295 Sets bank 2 and 4 voltages, with Values coming from Libero 296 297 Example: 298 299 @code 300 301 ASSERT(mss_does_xml_ver_support_switch() == true); 302 303 @endcode 304 305 * 306 */ 307 uint8_t mss_does_xml_ver_support_switch(void); 308 309 /***************************************************************************//** 310 mss_is_alternate_io_configured() 311 312 Example: 313 314 @code 315 316 if ( mss_is_alternate_io_configured() == true ) 317 { 318 ... 319 } 320 321 @endcode 322 323 * 324 */ 325 uint8_t mss_is_alternate_io_configured(void); 326 327 /***************************************************************************//** 328 mss_is_alternate_io_setting_emmc() 329 330 331 Example: 332 333 @code 334 335 if ( mss_is_alternate_io_setting_emmc() == true ) 336 { 337 ... 338 } 339 340 @endcode 341 342 * 343 */ 344 uint8_t mss_is_alternate_io_setting_emmc(void); 345 346 /***************************************************************************//** 347 mss_is_alternate_io_setting_sd() 348 349 Example: 350 351 @code 352 353 if ( mss_is_alternate_io_setting_sd() == true ) 354 { 355 ... 356 } 357 358 @endcode 359 360 * 361 */ 362 uint8_t mss_is_alternate_io_setting_sd(void); 363 364 /***************************************************************************//** 365 switch_external_mux() 366 This is a function used to switch external mux. 367 Requires fpga switch hdl. This comes with reference icicle kit design. 368 Will need to create your own or copy when creating your own fpga design 369 along with an external mux in your board design if you wish to use SD/eMMC 370 muxing in your hardware design. 371 372 Example: 373 374 @code 375 376 switch_external_mux(SD_MSSIO_CONFIGURATION); 377 378 @endcode 379 380 */ 381 uint8_t switch_external_mux(MSS_IO_OPTIONS option); 382 383 /***************************************************************************//** 384 mss_io_default_setting() 385 This helper function may be useful, e.g. print a message on start-up 386 explaining configuration. 387 388 Example: 389 390 @code 391 392 if ( mss_io_default_setting() == SD_MSSIO_CONFIGURATION ) 393 { 394 // ... 395 } 396 397 @endcode 398 399 */ 400 uint8_t mss_io_default_setting(void); 401 402 403 #ifdef __cplusplus 404 } 405 #endif 406 407 #endif /* USER_CONFIG_MSS_DDRC_MSS_IO_CONFIG_H_ */ 408
