1 /*******************************************************************************
2  * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * MPFS HAL Embedded Software
7  *
8  */
9 
10 /*******************************************************************************
11  * @file mss_ddr_defs.h
12  * @author Microchip-FPGA Embedded Systems Solutions
13  * @brief mss_ddr_debug related defines
14  *
15  */
16 
17 #ifndef SRC_PLATFORM_MPFS_HAL_NWC_MSS_DDR_DEFS_H_
18 #define SRC_PLATFORM_MPFS_HAL_NWC_MSS_DDR_DEFS_H_
19 
20 #define PATTERN_INCREMENTAL     (0x01U << 0U)
21 #define PATTERN_WALKING_ONE     (0x01U << 1U)
22 #define PATTERN_WALKING_ZERO    (0x01U << 2U)
23 #define PATTERN_RANDOM          (0x01U << 3U)
24 #define PATTERN_0xCCCCCCCC      (0x01U << 4U)
25 #define PATTERN_0x55555555      (0x01U << 5U)
26 #define PATTERN_ZEROS           (0x01U << 6U)
27 #define MAX_NO_PATTERNS         7U
28 
29 /* Training types status offsets */
30 #define BCLK_SCLK_BIT            (0x1U<<0U)
31 #define ADDCMD_BIT               (0x1U<<1U)
32 #define WRLVL_BIT                (0x1U<<2U)
33 #define RDGATE_BIT               (0x1U<<3U)
34 #define DQ_DQS_BIT               (0x1U<<4U)
35 
36 /*  The first five bits represent the currently supported training in the TIP */
37 /*  This value will not change unless more training possibilities are added to
38  *  the TIP */
39 #define TRAINING_MASK             (BCLK_SCLK_BIT|\
40                                        ADDCMD_BIT|\
41                                        WRLVL_BIT|\
42                                        RDGATE_BIT|\
43                                        DQ_DQS_BIT)
44 
45 #endif /* SRC_PLATFORM_MPFS_HAL_NWC_MSS_DDR_DEFS_H_ */
46