1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 /*=========================================================================*//** 10 11 *//*=========================================================================*/ 12 #ifndef __MSS_AXISW_H_ 13 #define __MSS_AXISW_H_ 1 14 15 16 #include <stddef.h> 17 #include <stdint.h> 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /***************************************************************************//** 24 25 */ 26 27 typedef enum { 28 MSS_AXISW_FIC0_RD_CHAN = 0x000, 29 MSS_AXISW_FIC0_WR_CHAN, 30 MSS_AXISW_FIC1_RD_CHAN, 31 MSS_AXISW_FIC1_WR_CHAN, 32 MSS_AXISW_FIC2_RD_CHAN, 33 MSS_AXISW_FIC2_WR_CHAN, 34 MSS_AXISW_ATHENA_RD_CHAN, 35 MSS_AXISW_ATHENA_WR_CHAN, 36 MSS_AXISW_GEM0_RD_CHAN, 37 MSS_AXISW_GEM0_WR_CHAN, 38 MSS_AXISW_GEM1_RD_CHAN, 39 MSS_AXISW_GEM1_WR_CHAN, 40 MSS_AXISW_MMC_RD_CHAN, 41 MSS_AXISW_MMC_WR_CHAN, 42 MSS_AXISW_USB_RD_CHAN, 43 MSS_AXISW_USB_WR_CHAN, 44 MSS_AXISW_SCB_RD_CHAN, 45 MSS_AXISW_SCB_WR_CHAN, 46 MSS_AXISW_CPLEX_D0_RD_CHAN, 47 MSS_AXISW_CPLEX_D0_WR_CHAN, 48 MSS_AXISW_CPLEX_D1_RD_CHAN, 49 MSS_AXISW_CPLEX_D1_WR_CHAN, 50 MSS_AXISW_CPLEX_F0_RD_CHAN, 51 MSS_AXISW_CPLEX_F0_WR_CHAN, 52 MSS_AXISW_CPLEX_F1_RD_CHAN, 53 MSS_AXISW_CPLEX_F1_WR_CHAN, 54 MSS_AXISW_CPLEX_NC_RD_CHAN, 55 MSS_AXISW_CPLEX_NC_WR_CHAN, 56 MSS_AXISW_TRACE_RD_CHAN, 57 MSS_AXISW_TRACE_WR_CHAN, 58 } mss_axisw_mport_t; 59 60 61 typedef enum { 62 MSS_AXISW_BURSTINESS_EN = 0x00, 63 MSS_AXISW_PEAKRT_XCTRT, 64 MSS_AXISW_QOS_VAL, 65 MSS_AXISW_SLV_RDY, 66 } mss_axisw_cmd_t; 67 68 typedef enum { 69 MSS_AXISW_MASTER_RD_CHAN = 0x00, 70 MSS_AXISW_MASTER_WR_CHAN = 0x01, 71 } mss_axisw_mchan_t; 72 73 /* 74 The Peak rate and transaction rates are encoded as follows. 75 1000_0000_0000 1/2 76 0100_0000_0000 1/4 77 0010_0000_0000 1/8 78 0001_0000_0000 1/16 79 0000_1000_0000 1/32 80 0000_0100_0000 1/64 81 0000_0010_0000 1/128 82 0000_0001_0000 1/256 83 0000_0000_1000 1/512 84 0000_0000_0100 1/1024 85 0000_0000_0010 1/2048 86 0000_0000_0001 1/4096 87 88 Programming the transaction rate as 0000_0000_0000 disables token generation and 89 traffic is not regulated based on the tokens. 90 91 Programming the peak rate as 0000_0000_0000 disables the peak rate control logic and 92 traffic is not regulated by the peak rate logic. 93 */ 94 typedef enum { 95 MSS_AXISW_TXNRATE_BY4096 = 0x001, 96 MSS_AXISW_TXNRATE_BY2098 = 0x002, 97 MSS_AXISW_TXNRATE_BY1024 = 0x004, 98 MSS_AXISW_TXNRATE_BY512 = 0x008, 99 MSS_AXISW_TXNRATE_BY256 = 0x010, 100 MSS_AXISW_TXNRATE_BY128 = 0x020, 101 MSS_AXISW_TXNRATE_BY64 = 0x040, 102 MSS_AXISW_TXNRATE_BY32 = 0x080, 103 MSS_AXISW_TXNRATE_BY16 = 0x100, 104 MSS_AXISW_TXNRATE_BY8 = 0x200, 105 MSS_AXISW_TXNRATE_BY4 = 0x400, 106 MSS_AXISW_TXNRATE_BY2 = 0x800, 107 MSS_AXISW_TXNRATE_DISABLE = 0x0, 108 } mss_axisw_rate_t; 109 110 #define AXISW_CMD_EN 31U 111 #define AXISW_CMD_EN_MASK (uint32_t)(0x01U << AXISW_CMD_EN) 112 113 #define AXISW_CMD_RW 30U 114 #define AXISW_CMD_RW_MASK (uint32_t)(0x01U << AXISW_CMD_RW) 115 116 #define AXISW_CMD_SWRST 29U 117 #define AXISW_CMD_SWRST_MASK (uint32_t)(0x01U << AXISW_CMD_SWRST) 118 119 #define AXISW_CMD_ERR 28U 120 #define AXISW_CMD_ERR_MASK (uint32_t)(0x01U << AXISW_CMD_ERR) 121 122 //#define AXISW_CMD_MPORT 8U 123 //#define AXISW_CMD_MPORT_MASK (0x0F << AXISW_CMD_MPORT) 124 125 #define AXISW_CMD_RWCHAN 7U 126 #define AXISW_CMD_RWCHAN_MASK (uint32_t)(0x1F << AXISW_CMD_RWCHAN) 127 128 #define AXISW_CMD_CMD 0U 129 #define AXISW_CMD_CMD_MASK (0x01U << AXISW_CMD_CMD) 130 131 #define AXISW_DATA_PEAKRT 20U 132 #define AXISW_DATA_PEAKRT_MASK (0xFFFU << AXISW_DATA_PEAKRT) 133 134 #define AXISW_DATA_XCTRT 4U 135 #define AXISW_DATA_XCTRT_MASK (0xFFFU << AXISW_DATA_XCTRT) 136 137 #define AXISW_DATA_BURSTI 16U 138 #define AXISW_DATA_BURSTI_MASK (0xFFU << AXISW_DATA_BURSTI) 139 140 #define AXISW_DATA_QOSVAL 0U 141 #define AXISW_DATA_QOSVAL_MASK (0xFU << AXISW_DATA_QOSVAL) 142 143 typedef struct 144 { 145 __IO uint32_t VID; 146 __IO uint32_t HWCFG; 147 __IO uint32_t CMD; 148 __IO uint32_t DATA; 149 } AXISW_TypeDef; 150 151 152 #define AXISW ((AXISW_TypeDef*)0x20004000UL) 153 154 155 uint32_t MSS_AXISW_get_hwcfg(void); 156 uint32_t MSS_AXISW_get_vid(void); 157 uint32_t MSS_AXISW_write_qos_val(mss_axisw_mport_t master_port_num, 158 uint32_t data); 159 uint32_t MSS_AXISW_read_qos_val(mss_axisw_mport_t master_port_num, 160 uint32_t* rd_data); 161 uint32_t MSS_AXISW_write_rate(mss_axisw_mport_t master_port_num, 162 mss_axisw_rate_t peak_rate, 163 mss_axisw_rate_t xct_rate); 164 uint32_t MSS_AXISW_read_rate(mss_axisw_mport_t master_port_num, 165 mss_axisw_rate_t* peak_rate, 166 mss_axisw_rate_t* xct_rate); 167 int32_t MSS_AXISW_write_burstiness(mss_axisw_mport_t master_port_num, 168 uint32_t burstiness_val, 169 uint32_t regulator_en); 170 uint32_t MSS_AXISW_read_burstiness(mss_axisw_mport_t master_port_num, 171 uint32_t* burstiness_val); 172 uint32_t MSS_AXISW_write_slave_ready(mss_axisw_mport_t master_port_num, 173 uint8_t slave_ready_en); 174 uint32_t MSS_AXISW_read_slave_ready(mss_axisw_mport_t master_port_num, 175 uint8_t* slave_ready_en); 176 177 178 #ifdef __cplusplus 179 } 180 #endif 181 182 #endif /* __MSS_AXISW_H_ */ 183 184
