1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_I2C_SMB_V3_7_H 7 #define _MEC5_I2C_SMB_V3_7_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 /** 13 * @brief I2C Controller with SMBus network layer (MEC_I2C_SMB0) 14 */ 15 16 typedef struct mec_i2c_smb_regs { /*!< (@ 0x40004000) MEC_I2C_SMB0 Structure */ 17 18 union { 19 __OM uint8_t CTRL; /*!< (@ 0x00000000) I2C mode Control(WO) */ 20 __IM uint8_t STATUS; /*!< (@ 0x00000000) I2C mode Status(RO) */ 21 }; 22 __IM uint8_t RESERVED; 23 __IM uint16_t RESERVED1; 24 __IOM uint32_t OWN_ADDR; /*!< (@ 0x00000004) I2C own addresses */ 25 __IOM uint8_t DATA; /*!< (@ 0x00000008) I2C mode data */ 26 __IM uint8_t RESERVED2; 27 __IM uint16_t RESERVED3; 28 __IOM uint32_t CM_CMD; /*!< (@ 0x0000000C) I2C-SMB Network layer Controller-mode command */ 29 __IOM uint32_t TM_CMD; /*!< (@ 0x00000010) I2C-SMB Network layer Target-mode command */ 30 __IOM uint8_t PEC; /*!< (@ 0x00000014) I2C-SMB PEC */ 31 __IM uint8_t RESERVED4; 32 __IM uint16_t RESERVED5; 33 __IOM uint32_t RSHT; /*!< (@ 0x00000018) I2C-SMB Repeat Start Hold time */ 34 __IOM uint32_t EXTLEN; /*!< (@ 0x0000001C) I2C-SMB Network layer extended lengths */ 35 __IOM uint32_t COMPL; /*!< (@ 0x00000020) I2C-SMB Completion */ 36 __IOM uint32_t IDLESC; /*!< (@ 0x00000024) I2C-SMB Idle scaling */ 37 __IOM uint32_t CONFIG; /*!< (@ 0x00000028) I2C-SMB Configuration */ 38 __IOM uint32_t BUSCLK; /*!< (@ 0x0000002C) I2C-SMB Bus Clock */ 39 __IOM uint32_t BLKID; /*!< (@ 0x00000030) I2C-SMB Block ID(RO) */ 40 __IOM uint32_t BLKREV; /*!< (@ 0x00000034) I2C-SMB Block Revision(RO) */ 41 __IOM uint8_t BBCTRL; /*!< (@ 0x00000038) I2C-SMB Bit-Bang Control */ 42 __IM uint8_t RESERVED6; 43 __IM uint16_t RESERVED7; 44 __IOM uint32_t MCHPR3C; /*!< (@ 0x0000003C) I2C-SMB MCHP Reserved at offset 0x3c */ 45 __IOM uint32_t DATATM; /*!< (@ 0x00000040) I2C-SMB Data timing */ 46 __IOM uint32_t TMOUTSC; /*!< (@ 0x00000044) I2C-SMB Data Timeout scaling */ 47 __IOM uint8_t TM_TXB; /*!< (@ 0x00000048) Target mode TX buffer */ 48 __IM uint8_t RESERVED8; 49 __IM uint16_t RESERVED9; 50 __IOM uint8_t TM_RXB; /*!< (@ 0x0000004C) Target mode RX buffer */ 51 __IM uint8_t RESERVED10; 52 __IM uint16_t RESERVED11; 53 __IOM uint8_t CM_TXB; /*!< (@ 0x00000050) Controller mode TX buffer */ 54 __IM uint8_t RESERVED12; 55 __IM uint16_t RESERVED13; 56 __IOM uint8_t CM_RXB; /*!< (@ 0x00000054) Controller mode RX buffer */ 57 __IM uint8_t RESERVED14; 58 __IM uint16_t RESERVED15; 59 __IM uint32_t FSM_I2C; /*!< (@ 0x00000058) I2C FSM(RO) */ 60 __IM uint32_t FSM_SNL; /*!< (@ 0x0000005C) I2C SMB Network Layer FSM(RO) */ 61 __IOM uint32_t WAKE_STS; /*!< (@ 0x00000060) I2C Wake Status */ 62 __IOM uint32_t WAKE_EN; /*!< (@ 0x00000064) I2C Wake Enable */ 63 __IOM uint32_t FAST_RSYNC; /*!< (@ 0x00000068) I2C Fast re-sync */ 64 __IOM uint32_t SHAD_ADDR; /*!< (@ 0x0000006C) Capture of I2C address received from external 65 controller. b[0]=nW/R, b[7:1]=7-bit I2C address */ 66 __IOM uint32_t PROM_ARS; /*!< (@ 0x00000070) Promiscuous mode address captured status */ 67 __IOM uint32_t PROM_IEN; /*!< (@ 0x00000074) Promiscuous mode interrupt enable */ 68 __IOM uint32_t PROM_CTRL; /*!< (@ 0x00000078) Promiscuous mode control register */ 69 __IOM uint32_t SHAD_DATA; /*!< (@ 0x0000007C) Capture of current I2C data tranmitted or received */ 70 } MEC_I2C_SMB_Type; /*!< Size = 128 (0x80) */ 71 72 /** @} */ /* End of group Device_Peripheral_peripherals */ 73 74 /** @addtogroup PosMask_peripherals 75 * @{ 76 */ 77 /* ========================================================= CTRL ========================================================== */ 78 #define MEC_I2C_SMB_CTRL_ACK_Pos (0UL) /*!< ACK (Bit 0) */ 79 #define MEC_I2C_SMB_CTRL_ACK_Msk (0x1UL) /*!< ACK (Bitfield-Mask: 0x01) */ 80 #define MEC_I2C_SMB_CTRL_STO_Pos (1UL) /*!< STO (Bit 1) */ 81 #define MEC_I2C_SMB_CTRL_STO_Msk (0x2UL) /*!< STO (Bitfield-Mask: 0x01) */ 82 #define MEC_I2C_SMB_CTRL_STA_Pos (2UL) /*!< STA (Bit 2) */ 83 #define MEC_I2C_SMB_CTRL_STA_Msk (0x4UL) /*!< STA (Bitfield-Mask: 0x01) */ 84 #define MEC_I2C_SMB_CTRL_ENI_Pos (3UL) /*!< ENI (Bit 3) */ 85 #define MEC_I2C_SMB_CTRL_ENI_Msk (0x8UL) /*!< ENI (Bitfield-Mask: 0x01) */ 86 #define MEC_I2C_SMB_CTRL_ESO_Pos (6UL) /*!< ESO (Bit 6) */ 87 #define MEC_I2C_SMB_CTRL_ESO_Msk (0x40UL) /*!< ESO (Bitfield-Mask: 0x01) */ 88 #define MEC_I2C_SMB_CTRL_PIN_Pos (7UL) /*!< PIN (Bit 7) */ 89 #define MEC_I2C_SMB_CTRL_PIN_Msk (0x80UL) /*!< PIN (Bitfield-Mask: 0x01) */ 90 /* ======================================================== STATUS ========================================================= */ 91 #define MEC_I2C_SMB_STATUS_NBB_Pos (0UL) /*!< NBB (Bit 0) */ 92 #define MEC_I2C_SMB_STATUS_NBB_Msk (0x1UL) /*!< NBB (Bitfield-Mask: 0x01) */ 93 #define MEC_I2C_SMB_STATUS_LAB_Pos (1UL) /*!< LAB (Bit 1) */ 94 #define MEC_I2C_SMB_STATUS_LAB_Msk (0x2UL) /*!< LAB (Bitfield-Mask: 0x01) */ 95 #define MEC_I2C_SMB_STATUS_AAT_Pos (2UL) /*!< AAT (Bit 2) */ 96 #define MEC_I2C_SMB_STATUS_AAT_Msk (0x4UL) /*!< AAT (Bitfield-Mask: 0x01) */ 97 #define MEC_I2C_SMB_STATUS_LRB_Pos (3UL) /*!< LRB (Bit 3) */ 98 #define MEC_I2C_SMB_STATUS_LRB_Msk (0x8UL) /*!< LRB (Bitfield-Mask: 0x01) */ 99 #define MEC_I2C_SMB_STATUS_BER_Pos (4UL) /*!< BER (Bit 4) */ 100 #define MEC_I2C_SMB_STATUS_BER_Msk (0x10UL) /*!< BER (Bitfield-Mask: 0x01) */ 101 #define MEC_I2C_SMB_STATUS_STS_Pos (5UL) /*!< STS (Bit 5) */ 102 #define MEC_I2C_SMB_STATUS_STS_Msk (0x20UL) /*!< STS (Bitfield-Mask: 0x01) */ 103 #define MEC_I2C_SMB_STATUS_SAD_Pos (6UL) /*!< SAD (Bit 6) */ 104 #define MEC_I2C_SMB_STATUS_SAD_Msk (0x40UL) /*!< SAD (Bitfield-Mask: 0x01) */ 105 #define MEC_I2C_SMB_STATUS_PIN_Pos (7UL) /*!< PIN (Bit 7) */ 106 #define MEC_I2C_SMB_STATUS_PIN_Msk (0x80UL) /*!< PIN (Bitfield-Mask: 0x01) */ 107 /* ======================================================= OWN_ADDR ======================================================== */ 108 #define MEC_I2C_SMB_OWN_ADDR_OAD0_Pos (0UL) /*!< OAD0 (Bit 0) */ 109 #define MEC_I2C_SMB_OWN_ADDR_OAD0_Msk (0x7fUL) /*!< OAD0 (Bitfield-Mask: 0x7f) */ 110 #define MEC_I2C_SMB_OWN_ADDR_OAD1_Pos (8UL) /*!< OAD1 (Bit 8) */ 111 #define MEC_I2C_SMB_OWN_ADDR_OAD1_Msk (0x7f00UL) /*!< OAD1 (Bitfield-Mask: 0x7f) */ 112 /* ========================================================= DATA ========================================================== */ 113 /* ======================================================== CM_CMD ========================================================= */ 114 #define MEC_I2C_SMB_CM_CMD_RUN_Pos (0UL) /*!< RUN (Bit 0) */ 115 #define MEC_I2C_SMB_CM_CMD_RUN_Msk (0x1UL) /*!< RUN (Bitfield-Mask: 0x01) */ 116 #define MEC_I2C_SMB_CM_CMD_PROCEED_Pos (1UL) /*!< PROCEED (Bit 1) */ 117 #define MEC_I2C_SMB_CM_CMD_PROCEED_Msk (0x2UL) /*!< PROCEED (Bitfield-Mask: 0x01) */ 118 #define MEC_I2C_SMB_CM_CMD_START0_Pos (8UL) /*!< START0 (Bit 8) */ 119 #define MEC_I2C_SMB_CM_CMD_START0_Msk (0x100UL) /*!< START0 (Bitfield-Mask: 0x01) */ 120 #define MEC_I2C_SMB_CM_CMD_STARTN_Pos (9UL) /*!< STARTN (Bit 9) */ 121 #define MEC_I2C_SMB_CM_CMD_STARTN_Msk (0x200UL) /*!< STARTN (Bitfield-Mask: 0x01) */ 122 #define MEC_I2C_SMB_CM_CMD_STOP_Pos (10UL) /*!< STOP (Bit 10) */ 123 #define MEC_I2C_SMB_CM_CMD_STOP_Msk (0x400UL) /*!< STOP (Bitfield-Mask: 0x01) */ 124 #define MEC_I2C_SMB_CM_CMD_PEC_TERM_Pos (11UL) /*!< PEC_TERM (Bit 11) */ 125 #define MEC_I2C_SMB_CM_CMD_PEC_TERM_Msk (0x800UL) /*!< PEC_TERM (Bitfield-Mask: 0x01) */ 126 #define MEC_I2C_SMB_CM_CMD_READM_Pos (12UL) /*!< READM (Bit 12) */ 127 #define MEC_I2C_SMB_CM_CMD_READM_Msk (0x1000UL) /*!< READM (Bitfield-Mask: 0x01) */ 128 #define MEC_I2C_SMB_CM_CMD_READ_PEC_Pos (13UL) /*!< READ_PEC (Bit 13) */ 129 #define MEC_I2C_SMB_CM_CMD_READ_PEC_Msk (0x2000UL) /*!< READ_PEC (Bitfield-Mask: 0x01) */ 130 #define MEC_I2C_SMB_CM_CMD_WRCNT_LSB_Pos (16UL) /*!< WRCNT_LSB (Bit 16) */ 131 #define MEC_I2C_SMB_CM_CMD_WRCNT_LSB_Msk (0xff0000UL) /*!< WRCNT_LSB (Bitfield-Mask: 0xff) */ 132 #define MEC_I2C_SMB_CM_CMD_RDCNT_LSB_Pos (24UL) /*!< RDCNT_LSB (Bit 24) */ 133 #define MEC_I2C_SMB_CM_CMD_RDCNT_LSB_Msk (0xff000000UL) /*!< RDCNT_LSB (Bitfield-Mask: 0xff) */ 134 /* ======================================================== TM_CMD ========================================================= */ 135 #define MEC_I2C_SMB_TM_CMD_RUN_Pos (0UL) /*!< RUN (Bit 0) */ 136 #define MEC_I2C_SMB_TM_CMD_RUN_Msk (0x1UL) /*!< RUN (Bitfield-Mask: 0x01) */ 137 #define MEC_I2C_SMB_TM_CMD_PROCEED_Pos (1UL) /*!< PROCEED (Bit 1) */ 138 #define MEC_I2C_SMB_TM_CMD_PROCEED_Msk (0x2UL) /*!< PROCEED (Bitfield-Mask: 0x01) */ 139 #define MEC_I2C_SMB_TM_CMD_TX_PEC_Pos (2UL) /*!< TX_PEC (Bit 2) */ 140 #define MEC_I2C_SMB_TM_CMD_TX_PEC_Msk (0x4UL) /*!< TX_PEC (Bitfield-Mask: 0x01) */ 141 #define MEC_I2C_SMB_TM_CMD_WRCNT_LSB_Pos (8UL) /*!< WRCNT_LSB (Bit 16) */ 142 #define MEC_I2C_SMB_TM_CMD_WRCNT_LSB_Msk (0xff00UL) /*!< WRCNT_LSB (Bitfield-Mask: 0xff) */ 143 #define MEC_I2C_SMB_TM_CMD_RDCNT_LSB_Pos (16UL) /*!< RDCNT_LSB (Bit 24) */ 144 #define MEC_I2C_SMB_TM_CMD_RDCNT_LSB_Msk (0xff0000UL) /*!< RDCNT_LSB (Bitfield-Mask: 0xff) */ 145 /* ========================================================== PEC ========================================================== */ 146 /* ========================================================= RSHT ========================================================== */ 147 /* ======================================================== EXTLEN ========================================================= */ 148 #define MEC_I2C_SMB_ELEN_CM_WRCNT_MSB_Pos (0UL) /*!< CM_WRCNT_MSB (Bit 0) */ 149 #define MEC_I2C_SMB_ELEN_CM_WRCNT_MSB_Msk (0xffUL) /*!< CM_WRCNT_MSB (Bitfield-Mask: 0xff) */ 150 #define MEC_I2C_SMB_ELEN_CM_RDCNT_MSB_Pos (8UL) /*!< CM_RDCNT_MSB (Bit 8) */ 151 #define MEC_I2C_SMB_ELEN_CM_RDCNT_MSB_Msk (0xff00UL) /*!< CM_RDCNT_MSB (Bitfield-Mask: 0xff) */ 152 #define MEC_I2C_SMB_ELEN_TM_WRCNT_MSB_Pos (16UL) /*!< TM_WRCNT_MSB (Bit 16) */ 153 #define MEC_I2C_SMB_ELEN_TM_WRCNT_MSB_Msk (0xff0000UL) /*!< TM_WRCNT_MSB (Bitfield-Mask: 0xff) */ 154 #define MEC_I2C_SMB_ELEN_TM_RDCNT_MSB_Pos (24UL) /*!< TM_RDCNT_MSB (Bit 24) */ 155 #define MEC_I2C_SMB_ELEN_TM_RDCNT_MSB_Msk (0xff000000UL) /*!< TM_RDCNT_MSB (Bitfield-Mask: 0xff) */ 156 /* ========================================================= COMPL ========================================================= */ 157 #define MEC_I2C_SMB_COMPL_DTEN_Pos (2UL) /*!< DTEN (Bit 2) */ 158 #define MEC_I2C_SMB_COMPL_DTEN_Msk (0x4UL) /*!< DTEN (Bitfield-Mask: 0x01) */ 159 #define MEC_I2C_SMB_COMPL_MCEN_Pos (3UL) /*!< MCEN (Bit 3) */ 160 #define MEC_I2C_SMB_COMPL_MCEN_Msk (0x8UL) /*!< MCEN (Bitfield-Mask: 0x01) */ 161 #define MEC_I2C_SMB_COMPL_SCEN_Pos (4UL) /*!< SCEN (Bit 4) */ 162 #define MEC_I2C_SMB_COMPL_SCEN_Msk (0x10UL) /*!< SCEN (Bitfield-Mask: 0x01) */ 163 #define MEC_I2C_SMB_COMPL_BIDEN_Pos (5UL) /*!< BIDEN (Bit 5) */ 164 #define MEC_I2C_SMB_COMPL_BIDEN_Msk (0x20UL) /*!< BIDEN (Bitfield-Mask: 0x01) */ 165 #define MEC_I2C_SMB_COMPL_TIMERR_Pos (6UL) /*!< TIMERR (Bit 6) */ 166 #define MEC_I2C_SMB_COMPL_TIMERR_Msk (0x40UL) /*!< TIMERR (Bitfield-Mask: 0x01) */ 167 #define MEC_I2C_SMB_COMPL_DTO_Pos (8UL) /*!< DTO (Bit 8) */ 168 #define MEC_I2C_SMB_COMPL_DTO_Msk (0x100UL) /*!< DTO (Bitfield-Mask: 0x01) */ 169 #define MEC_I2C_SMB_COMPL_MCTO_Pos (9UL) /*!< MCTO (Bit 9) */ 170 #define MEC_I2C_SMB_COMPL_MCTO_Msk (0x200UL) /*!< MCTO (Bitfield-Mask: 0x01) */ 171 #define MEC_I2C_SMB_COMPL_SCTO_Pos (10UL) /*!< SCTO (Bit 10) */ 172 #define MEC_I2C_SMB_COMPL_SCTO_Msk (0x400UL) /*!< SCTO (Bitfield-Mask: 0x01) */ 173 #define MEC_I2C_SMB_COMPL_CHDL_Pos (11UL) /*!< CHDL (Bit 11) */ 174 #define MEC_I2C_SMB_COMPL_CHDL_Msk (0x800UL) /*!< CHDL (Bitfield-Mask: 0x01) */ 175 #define MEC_I2C_SMB_COMPL_CHDH_Pos (12UL) /*!< CHDH (Bit 12) */ 176 #define MEC_I2C_SMB_COMPL_CHDH_Msk (0x1000UL) /*!< CHDH (Bitfield-Mask: 0x01) */ 177 #define MEC_I2C_SMB_COMPL_BUSERR_Pos (13UL) /*!< BUSERR (Bit 13) */ 178 #define MEC_I2C_SMB_COMPL_BUSERR_Msk (0x2000UL) /*!< BUSERR (Bitfield-Mask: 0x01) */ 179 #define MEC_I2C_SMB_COMPL_LABSTS_Pos (14UL) /*!< LABSTS (Bit 14) */ 180 #define MEC_I2C_SMB_COMPL_LABSTS_Msk (0x4000UL) /*!< LABSTS (Bitfield-Mask: 0x01) */ 181 #define MEC_I2C_SMB_COMPL_TM_NAKR_Pos (16UL) /*!< SNAKR (Bit 16) */ 182 #define MEC_I2C_SMB_COMPL_TM_NAKR_Msk (0x10000UL) /*!< SNAKR (Bitfield-Mask: 0x01) */ 183 #define MEC_I2C_SMB_COMPL_TM_TR_Pos (17UL) /*!< STR (Bit 17) */ 184 #define MEC_I2C_SMB_COMPL_TM_TR_Msk (0x20000UL) /*!< STR (Bitfield-Mask: 0x01) */ 185 #define MEC_I2C_SMB_COMPL_TM_PROT_Pos (19UL) /*!< SPROT (Bit 19) */ 186 #define MEC_I2C_SMB_COMPL_TM_PROT_Msk (0x80000UL) /*!< SPROT (Bitfield-Mask: 0x01) */ 187 #define MEC_I2C_SMB_COMPL_RPTRD_Pos (20UL) /*!< RPTRD (Bit 20) */ 188 #define MEC_I2C_SMB_COMPL_RPTRD_Msk (0x100000UL) /*!< RPTRD (Bitfield-Mask: 0x01) */ 189 #define MEC_I2C_SMB_COMPL_RPTWR_Pos (21UL) /*!< RPTWR (Bit 21) */ 190 #define MEC_I2C_SMB_COMPL_RPTWR_Msk (0x200000UL) /*!< RPTWR (Bitfield-Mask: 0x01) */ 191 #define MEC_I2C_SMB_COMPL_CM_NAKX_Pos (24UL) /*!< MNAKX (Bit 24) */ 192 #define MEC_I2C_SMB_COMPL_CM_NAKX_Msk (0x1000000UL) /*!< MNAKX (Bitfield-Mask: 0x01) */ 193 #define MEC_I2C_SMB_COMPL_CM_TR_Pos (25UL) /*!< MTR (Bit 25) */ 194 #define MEC_I2C_SMB_COMPL_CM_TR_Msk (0x2000000UL) /*!< MTR (Bitfield-Mask: 0x01) */ 195 #define MEC_I2C_SMB_COMPL_IDLE_Pos (29UL) /*!< IDLE (Bit 29) */ 196 #define MEC_I2C_SMB_COMPL_IDLE_Msk (0x20000000UL) /*!< IDLE (Bitfield-Mask: 0x01) */ 197 #define MEC_I2C_SMB_COMPL_CM_DONE_Pos (30UL) /*!< CM_DONE (Bit 30) */ 198 #define MEC_I2C_SMB_COMPL_CM_DONE_Msk (0x40000000UL) /*!< CM_DONE (Bitfield-Mask: 0x01) */ 199 #define MEC_I2C_SMB_COMPL_TM_DONE_Pos (31UL) /*!< TM_DONE (Bit 31) */ 200 #define MEC_I2C_SMB_COMPL_TM_DONE_Msk (0x80000000UL) /*!< TM_DONE (Bitfield-Mask: 0x01) */ 201 /* ======================================================== IDLESC ========================================================= */ 202 #define MEC_I2C_SMB_IDLESC_FBIM_Pos (0UL) /*!< FBIM (Bit 0) */ 203 #define MEC_I2C_SMB_IDLESC_FBIM_Msk (0xfffUL) /*!< FBIM (Bitfield-Mask: 0xfff) */ 204 #define MEC_I2C_SMB_IDLESC_FIDLY_Pos (16UL) /*!< FIDLY (Bit 16) */ 205 #define MEC_I2C_SMB_IDLESC_FIDLY_Msk (0xfff0000UL) /*!< FIDLY (Bitfield-Mask: 0xfff) */ 206 /* ======================================================== CONFIG ========================================================= */ 207 #define MEC_I2C_SMB_CONFIG_PORT_SEL_Pos (0UL) /*!< PORT_SEL (Bit 0) */ 208 #define MEC_I2C_SMB_CONFIG_PORT_SEL_Msk (0xfUL) /*!< PORT_SEL (Bitfield-Mask: 0x0f) */ 209 #define MEC_I2C_SMB_CONFIG_TCEN_Pos (4UL) /*!< TCEN (Bit 4) */ 210 #define MEC_I2C_SMB_CONFIG_TCEN_Msk (0x10UL) /*!< TCEN (Bitfield-Mask: 0x01) */ 211 #define MEC_I2C_SMB_CONFIG_SLOW_CLK_Pos (5UL) /*!< SLOW_CLK (Bit 5) */ 212 #define MEC_I2C_SMB_CONFIG_SLOW_CLK_Msk (0x20UL) /*!< SLOW_CLK (Bitfield-Mask: 0x01) */ 213 #define MEC_I2C_SMB_CONFIG_PCEN_Pos (7UL) /*!< PCEN (Bit 7) */ 214 #define MEC_I2C_SMB_CONFIG_PCEN_Msk (0x80UL) /*!< PCEN (Bitfield-Mask: 0x01) */ 215 #define MEC_I2C_SMB_CONFIG_FEN_Pos (8UL) /*!< FEN (Bit 8) */ 216 #define MEC_I2C_SMB_CONFIG_FEN_Msk (0x100UL) /*!< FEN (Bitfield-Mask: 0x01) */ 217 #define MEC_I2C_SMB_CONFIG_RESET_Pos (9UL) /*!< RESET (Bit 9) */ 218 #define MEC_I2C_SMB_CONFIG_RESET_Msk (0x200UL) /*!< RESET (Bitfield-Mask: 0x01) */ 219 #define MEC_I2C_SMB_CONFIG_ENAB_Pos (10UL) /*!< ENAB (Bit 10) */ 220 #define MEC_I2C_SMB_CONFIG_ENAB_Msk (0x400UL) /*!< ENAB (Bitfield-Mask: 0x01) */ 221 #define MEC_I2C_SMB_CONFIG_DSA_Pos (11UL) /*!< DSA (Bit 11) */ 222 #define MEC_I2C_SMB_CONFIG_DSA_Msk (0x800UL) /*!< DSA (Bitfield-Mask: 0x01) */ 223 #define MEC_I2C_SMB_CONFIG_MCTP_FEN_Pos (12UL) /*!< MCTP_FEN (Bit 12) */ 224 #define MEC_I2C_SMB_CONFIG_MCTP_FEN_Msk (0x1000UL) /*!< MCTP_FEN (Bitfield-Mask: 0x01) */ 225 #define MEC_I2C_SMB_CONFIG_GC_DIS_Pos (14UL) /*!< GC_DIS (Bit 14) */ 226 #define MEC_I2C_SMB_CONFIG_GC_DIS_Msk (0x4000UL) /*!< GC_DIS (Bitfield-Mask: 0x01) */ 227 #define MEC_I2C_SMB_CONFIG_PROMEN_Pos (15UL) /*!< PROMEN (Bit 15) */ 228 #define MEC_I2C_SMB_CONFIG_PROMEN_Msk (0x8000UL) /*!< PROMEN (Bitfield-Mask: 0x01) */ 229 #define MEC_I2C_SMB_CONFIG_FLUSH_TM_TXB_Pos (16UL) /*!< FLUSH_TM_TXB (Bit 16) */ 230 #define MEC_I2C_SMB_CONFIG_FLUSH_TM_TXB_Msk (0x10000UL) /*!< FLUSH_TM_TXB (Bitfield-Mask: 0x01) */ 231 #define MEC_I2C_SMB_CONFIG_FLUSH_TM_RXB_Pos (17UL) /*!< FLUSH_TM_RXB (Bit 17) */ 232 #define MEC_I2C_SMB_CONFIG_FLUSH_TM_RXB_Msk (0x20000UL) /*!< FLUSH_TM_RXB (Bitfield-Mask: 0x01) */ 233 #define MEC_I2C_SMB_CONFIG_FLUSH_CTXB_Pos (18UL) /*!< FLUSH_CTXB (Bit 18) */ 234 #define MEC_I2C_SMB_CONFIG_FLUSH_CTXB_Msk (0x40000UL) /*!< FLUSH_CTXB (Bitfield-Mask: 0x01) */ 235 #define MEC_I2C_SMB_CONFIG_FLUSH_CRXB_Pos (19UL) /*!< FLUSH_CRXB (Bit 19) */ 236 #define MEC_I2C_SMB_CONFIG_FLUSH_CRXB_Msk (0x80000UL) /*!< FLUSH_CRXB (Bitfield-Mask: 0x01) */ 237 #define MEC_I2C_SMB_CONFIG_ENI_AAT_Pos (28UL) /*!< ENI_AAT (Bit 28) */ 238 #define MEC_I2C_SMB_CONFIG_ENI_AAT_Msk (0x10000000UL) /*!< ENI_AAT (Bitfield-Mask: 0x01) */ 239 #define MEC_I2C_SMB_CONFIG_ENI_IDLE_Pos (29UL) /*!< ENI_IDLE (Bit 29) */ 240 #define MEC_I2C_SMB_CONFIG_ENI_IDLE_Msk (0x20000000UL) /*!< ENI_IDLE (Bitfield-Mask: 0x01) */ 241 #define MEC_I2C_SMB_CONFIG_ENMI_Pos (30UL) /*!< ENMI (Bit 30) */ 242 #define MEC_I2C_SMB_CONFIG_ENMI_Msk (0x40000000UL) /*!< ENMI (Bitfield-Mask: 0x01) */ 243 #define MEC_I2C_SMB_CONFIG_ENSI_Pos (31UL) /*!< ENSI (Bit 31) */ 244 #define MEC_I2C_SMB_CONFIG_ENSI_Msk (0x80000000UL) /*!< ENSI (Bitfield-Mask: 0x01) */ 245 /* ======================================================== BUSCLK ========================================================= */ 246 #define MEC_I2C_SMB_BUSCLK_LOPER_Pos (0UL) /*!< LOPER (Bit 0) */ 247 #define MEC_I2C_SMB_BUSCLK_LOPER_Msk (0xffUL) /*!< LOPER (Bitfield-Mask: 0xff) */ 248 #define MEC_I2C_SMB_BUSCLK_HIPER_Pos (8UL) /*!< HIPER (Bit 8) */ 249 #define MEC_I2C_SMB_BUSCLK_HIPER_Msk (0xff00UL) /*!< HIPER (Bitfield-Mask: 0xff) */ 250 /* ========================================================= BLKID ========================================================= */ 251 /* ======================================================== BLKREV ========================================================= */ 252 /* ======================================================== BBCTRL ========================================================= */ 253 #define MEC_I2C_SMB_BBCTRL_BBEN_Pos (0UL) /*!< BBEN (Bit 0) */ 254 #define MEC_I2C_SMB_BBCTRL_BBEN_Msk (0x1UL) /*!< BBEN (Bitfield-Mask: 0x01) */ 255 #define MEC_I2C_SMB_BBCTRL_CLDIR_Pos (1UL) /*!< CLDIR (Bit 1) */ 256 #define MEC_I2C_SMB_BBCTRL_CLDIR_Msk (0x2UL) /*!< CLDIR (Bitfield-Mask: 0x01) */ 257 #define MEC_I2C_SMB_BBCTRL_DADIR_Pos (2UL) /*!< DADIR (Bit 2) */ 258 #define MEC_I2C_SMB_BBCTRL_DADIR_Msk (0x4UL) /*!< DADIR (Bitfield-Mask: 0x01) */ 259 #define MEC_I2C_SMB_BBCTRL_BBCLK_Pos (3UL) /*!< BBCLK (Bit 3) */ 260 #define MEC_I2C_SMB_BBCTRL_BBCLK_Msk (0x8UL) /*!< BBCLK (Bitfield-Mask: 0x01) */ 261 #define MEC_I2C_SMB_BBCTRL_BBDAT_Pos (4UL) /*!< BBDAT (Bit 4) */ 262 #define MEC_I2C_SMB_BBCTRL_BBDAT_Msk (0x10UL) /*!< BBDAT (Bitfield-Mask: 0x01) */ 263 #define MEC_I2C_SMB_BBCTRL_BBCLKI_Pos (5UL) /*!< BBCLKI (Bit 5) */ 264 #define MEC_I2C_SMB_BBCTRL_BBCLKI_Msk (0x20UL) /*!< BBCLKI (Bitfield-Mask: 0x01) */ 265 #define MEC_I2C_SMB_BBCTRL_BBDATI_Pos (6UL) /*!< BBDATI (Bit 6) */ 266 #define MEC_I2C_SMB_BBCTRL_BBDATI_Msk (0x40UL) /*!< BBDATI (Bitfield-Mask: 0x01) */ 267 /* ======================================================== MCHPR3C ======================================================== */ 268 /* ======================================================== DATATM ========================================================= */ 269 #define MEC_I2C_SMB_DATATM_DHOLD_Pos (0UL) /*!< DHOLD (Bit 0) */ 270 #define MEC_I2C_SMB_DATATM_DHOLD_Msk (0xffUL) /*!< DHOLD (Bitfield-Mask: 0xff) */ 271 #define MEC_I2C_SMB_DATATM_RSS_Pos (8UL) /*!< RSS (Bit 8) */ 272 #define MEC_I2C_SMB_DATATM_RSS_Msk (0xff00UL) /*!< RSS (Bitfield-Mask: 0xff) */ 273 #define MEC_I2C_SMB_DATATM_STPS_Pos (16UL) /*!< STPS (Bit 16) */ 274 #define MEC_I2C_SMB_DATATM_STPS_Msk (0xff0000UL) /*!< STPS (Bitfield-Mask: 0xff) */ 275 #define MEC_I2C_SMB_DATATM_FSHLD_Pos (24UL) /*!< FSHLD (Bit 24) */ 276 #define MEC_I2C_SMB_DATATM_FSHLD_Msk (0xff000000UL) /*!< FSHLD (Bitfield-Mask: 0xff) */ 277 /* ======================================================== TMOUTSC ======================================================== */ 278 #define MEC_I2C_SMB_TMOUTSC_CHTO_Pos (0UL) /*!< CHTO (Bit 0) */ 279 #define MEC_I2C_SMB_TMOUTSC_CHTO_Msk (0xffUL) /*!< CHTO (Bitfield-Mask: 0xff) */ 280 #define MEC_I2C_SMB_TMOUTSC_DCTO_Pos (8UL) /*!< DCTO (Bit 8) */ 281 #define MEC_I2C_SMB_TMOUTSC_DCTO_Msk (0xff00UL) /*!< DCTO (Bitfield-Mask: 0xff) */ 282 #define MEC_I2C_SMB_TMOUTSC_CCTO_Pos (16UL) /*!< CCTO (Bit 16) */ 283 #define MEC_I2C_SMB_TMOUTSC_CCTO_Msk (0xff0000UL) /*!< CCTO (Bitfield-Mask: 0xff) */ 284 #define MEC_I2C_SMB_TMOUTSC_BIMIN_Pos (24UL) /*!< BIMIN (Bit 24) */ 285 #define MEC_I2C_SMB_TMOUTSC_BIMIN_Msk (0xff000000UL) /*!< BIMIN (Bitfield-Mask: 0xff) */ 286 /* ======================================================== TM_TXB ========================================================= */ 287 /* ======================================================== TM_RXB ========================================================= */ 288 /* ======================================================== CM_TXB ========================================================= */ 289 /* ======================================================== CM_RXB ========================================================= */ 290 /* ======================================================== FSM_I2C ======================================================== */ 291 #define MEC_I2C_SMB_FSM_I2C_CM_STATE_Pos (0UL) /*!< CM_STATE (Bit 0) */ 292 #define MEC_I2C_SMB_FSM_I2C_CM_STATE_Msk (0xffUL) /*!< CM_STATE (Bitfield-Mask: 0xff) */ 293 #define MEC_I2C_SMB_FSM_I2C_TM_STATE_Pos (8UL) /*!< TM_STATE (Bit 8) */ 294 #define MEC_I2C_SMB_FSM_I2C_TM_STATE_Msk (0xff00UL) /*!< TM_STATE (Bitfield-Mask: 0xff) */ 295 #define MEC_I2C_SMB_FSM_I2C_PHY_STATE_Pos (16UL) /*!< PHY_STATE (Bit 16) */ 296 #define MEC_I2C_SMB_FSM_I2C_PHY_STATE_Msk (0xf0000UL) /*!< PHY_STATE (Bitfield-Mask: 0x0f) */ 297 #define MEC_I2C_SMB_FSM_I2C_CM_CTO_Pos (20UL) /*!< CM_CTO (Bit 20) */ 298 #define MEC_I2C_SMB_FSM_I2C_CM_CTO_Msk (0xf00000UL) /*!< CM_CTO (Bitfield-Mask: 0x0f) */ 299 #define MEC_I2C_SMB_FSM_I2C_TM_CTO_Pos (24UL) /*!< TM_CTO (Bit 24) */ 300 #define MEC_I2C_SMB_FSM_I2C_TM_CTO_Msk (0x1f000000UL) /*!< TM_CTO (Bitfield-Mask: 0x1f) */ 301 #define MEC_I2C_SMB_FSM_I2C_CM_BI_Pos (29UL) /*!< CM_BI (Bit 29) */ 302 #define MEC_I2C_SMB_FSM_I2C_CM_BI_Msk (0xe0000000UL) /*!< CM_BI (Bitfield-Mask: 0x07) */ 303 /* ======================================================== FSM_SNL ======================================================== */ 304 #define MEC_I2C_SMB_FSM_SNL_CM_STATE_Pos (0UL) /*!< CM_STATE (Bit 0) */ 305 #define MEC_I2C_SMB_FSM_SNL_CM_STATE_Msk (0xffUL) /*!< CM_STATE (Bitfield-Mask: 0xff) */ 306 #define MEC_I2C_SMB_FSM_SNL_TM_STATE_Pos (8UL) /*!< TM_STATE (Bit 8) */ 307 #define MEC_I2C_SMB_FSM_SNL_TM_STATE_Msk (0xff00UL) /*!< TM_STATE (Bitfield-Mask: 0xff) */ 308 #define MEC_I2C_SMB_FSM_SNL_MCTP_FAIR_Pos (16UL) /*!< MCTP_FAIR (Bit 16) */ 309 #define MEC_I2C_SMB_FSM_SNL_MCTP_FAIR_Msk (0xff0000UL) /*!< MCTP_FAIR (Bitfield-Mask: 0xff) */ 310 /* ======================================================= WAKE_STS ======================================================== */ 311 #define MEC_I2C_SMB_WAKE_STS_START_DET_Pos (0UL) /*!< START_DET (Bit 0) */ 312 #define MEC_I2C_SMB_WAKE_STS_START_DET_Msk (0x1UL) /*!< START_DET (Bitfield-Mask: 0x01) */ 313 /* ======================================================== WAKE_EN ======================================================== */ 314 #define MEC_I2C_SMB_WAKE_EN_START_DET_Pos (0UL) /*!< START_DET (Bit 0) */ 315 #define MEC_I2C_SMB_WAKE_EN_START_DET_Msk (0x1UL) /*!< START_DET (Bitfield-Mask: 0x01) */ 316 /* ====================================================== FAST_RSYNC ======================================================= */ 317 /* ======================================================= SHAD_ADDR ======================================================= */ 318 /* ======================================================= PROM_ARS ======================================================== */ 319 #define MEC_I2C_SMB_PROM_ARS_ARSTS_Pos (0UL) /*!< ARSTS (Bit 0) */ 320 #define MEC_I2C_SMB_PROM_ARS_ARSTS_Msk (0x1UL) /*!< ARSTS (Bitfield-Mask: 0x01) */ 321 /* ======================================================= PROM_IEN ======================================================== */ 322 #define MEC_I2C_SMB_PROM_IEN_ARI_Pos (0UL) /*!< ARI (Bit 0) */ 323 #define MEC_I2C_SMB_PROM_IEN_ARI_Msk (0x1UL) /*!< ARI (Bitfield-Mask: 0x01) */ 324 /* ======================================================= PROM_CTRL ======================================================= */ 325 #define MEC_I2C_SMB_PROM_CTRL_ARACK_Pos (0UL) /*!< ARACK (Bit 0) */ 326 #define MEC_I2C_SMB_PROM_CTRL_ARACK_Msk (0x1UL) /*!< ARACK (Bitfield-Mask: 0x01) */ 327 328 /** @} */ /* End of group PosMask_peripherals */ 329 330 /** @addtogroup EnumValue_peripherals 331 * @{ 332 */ 333 /* ========================================================= CTRL ========================================================== */ 334 /* ============================================= MEC_I2C_SMB0 CTRL ACK [0..0] ============================================== */ 335 typedef enum { /*!< MEC_I2C_SMB0_CTRL_ACK */ 336 MEC_I2C_SMB0_CTRL_ACK_EN = 1, /*!< EN : Generate ACK for addresses matching OWN addresses */ 337 } MEC_I2C_SMB0_CTRL_ACK_Enum; 338 339 /* ============================================= MEC_I2C_SMB0 CTRL STO [1..1] ============================================== */ 340 typedef enum { /*!< MEC_I2C_SMB0_CTRL_STO */ 341 MEC_I2C_SMB0_CTRL_STO_EN = 1, /*!< EN : Generate I2C STOP */ 342 } MEC_I2C_SMB0_CTRL_STO_Enum; 343 344 /* ============================================= MEC_I2C_SMB0 CTRL STA [2..2] ============================================== */ 345 typedef enum { /*!< MEC_I2C_SMB0_CTRL_STA */ 346 MEC_I2C_SMB0_CTRL_STA_EN = 1, /*!< EN : Generate I2C START */ 347 } MEC_I2C_SMB0_CTRL_STA_Enum; 348 349 /* ============================================= MEC_I2C_SMB0 CTRL ENI [3..3] ============================================== */ 350 typedef enum { /*!< MEC_I2C_SMB0_CTRL_ENI */ 351 MEC_I2C_SMB0_CTRL_ENI_EN = 1, /*!< EN : Enable interrupt when PIN bit asserts(active low) */ 352 } MEC_I2C_SMB0_CTRL_ENI_Enum; 353 354 /* ============================================= MEC_I2C_SMB0 CTRL ESO [6..6] ============================================== */ 355 typedef enum { /*!< MEC_I2C_SMB0_CTRL_ESO */ 356 MEC_I2C_SMB0_CTRL_ESO_EN = 1, /*!< EN : Enable SDA pin output */ 357 } MEC_I2C_SMB0_CTRL_ESO_Enum; 358 359 /* ============================================= MEC_I2C_SMB0 CTRL PIN [7..7] ============================================== */ 360 typedef enum { /*!< MEC_I2C_SMB0_CTRL_PIN */ 361 MEC_I2C_SMB0_CTRL_PIN_EN = 1, /*!< EN : Clear I2C status except NBB */ 362 } MEC_I2C_SMB0_CTRL_PIN_Enum; 363 364 /* ======================================================== STATUS ========================================================= */ 365 /* ============================================ MEC_I2C_SMB0 STATUS NBB [0..0] ============================================= */ 366 typedef enum { /*!< MEC_I2C_SMB0_STATUS_NBB */ 367 MEC_I2C_SMB0_STATUS_NBB_ACTIVE = 1, /*!< ACTIVE : Not Bus Busy is active */ 368 } MEC_I2C_SMB0_STATUS_NBB_Enum; 369 370 /* ============================================ MEC_I2C_SMB0 STATUS LAB [1..1] ============================================= */ 371 typedef enum { /*!< MEC_I2C_SMB0_STATUS_LAB */ 372 MEC_I2C_SMB0_STATUS_LAB_ACTIVE = 1, /*!< ACTIVE : Lost bus arbitration status is active */ 373 } MEC_I2C_SMB0_STATUS_LAB_Enum; 374 375 /* ============================================ MEC_I2C_SMB0 STATUS AAS [2..2] ============================================= */ 376 typedef enum { /*!< MEC_I2C_SMB0_STATUS_AAS */ 377 MEC_I2C_SMB0_STATUS_AAS_ACTIVE = 1, /*!< ACTIVE : Addresses as device status is active */ 378 } MEC_I2C_SMB0_STATUS_AAS_Enum; 379 380 /* ============================================ MEC_I2C_SMB0 STATUS LRB [3..3] ============================================= */ 381 typedef enum { /*!< MEC_I2C_SMB0_STATUS_LRB */ 382 MEC_I2C_SMB0_STATUS_LRB_HI = 1, /*!< HI : Last receive state is High */ 383 } MEC_I2C_SMB0_STATUS_LRB_Enum; 384 385 /* ============================================ MEC_I2C_SMB0 STATUS BER [4..4] ============================================= */ 386 typedef enum { /*!< MEC_I2C_SMB0_STATUS_BER */ 387 MEC_I2C_SMB0_STATUS_BER_ACTIVE = 1, /*!< ACTIVE : Bus Error status is active */ 388 } MEC_I2C_SMB0_STATUS_BER_Enum; 389 390 /* ============================================ MEC_I2C_SMB0 STATUS STS [5..5] ============================================= */ 391 typedef enum { /*!< MEC_I2C_SMB0_STATUS_STS */ 392 MEC_I2C_SMB0_STATUS_STS_ACTIVE = 1, /*!< ACTIVE : Externally generated STOP detected status is active */ 393 } MEC_I2C_SMB0_STATUS_STS_Enum; 394 395 /* ============================================ MEC_I2C_SMB0 STATUS SAD [6..6] ============================================= */ 396 typedef enum { /*!< MEC_I2C_SMB0_STATUS_SAD */ 397 MEC_I2C_SMB0_STATUS_SAD_ACTIVE = 1, /*!< ACTIVE : SMBus address detected */ 398 } MEC_I2C_SMB0_STATUS_SAD_Enum; 399 400 /* ============================================ MEC_I2C_SMB0 STATUS PIN [7..7] ============================================= */ 401 typedef enum { /*!< MEC_I2C_SMB0_STATUS_PIN */ 402 MEC_I2C_SMB0_STATUS_PIN_nACTIVE = 1, /*!< nACTIVE : Pending Interrupt is not active */ 403 } MEC_I2C_SMB0_STATUS_PIN_Enum; 404 405 /* ======================================================= OWN_ADDR ======================================================== */ 406 /* ========================================================= DATA ========================================================== */ 407 /* ======================================================== CM_CMD ========================================================= */ 408 /* ============================================ MEC_I2C_SMB0 CM_CMD MRUN [0..0] ============================================ */ 409 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_MRUN */ 410 MEC_I2C_SMB0_CM_CMD_MRUN_START = 1, /*!< START : Start controller mode network layer operation */ 411 } MEC_I2C_SMB0_CM_CMD_MRUN_Enum; 412 413 /* ========================================== MEC_I2C_SMB0 CM_CMD MPROCEED [1..1] ========================================== */ 414 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_MPROCEED */ 415 MEC_I2C_SMB0_CM_CMD_MPROCEED_ON = 1, /*!< ON : Inform network layer FW has finished re-configure and HW 416 can continue */ 417 } MEC_I2C_SMB0_CM_CMD_MPROCEED_Enum; 418 419 /* =========================================== MEC_I2C_SMB0 CM_CMD START0 [8..8] =========================================== */ 420 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_START0 */ 421 MEC_I2C_SMB0_CM_CMD_START0_EN = 1, /*!< EN : Generate an I2C START when operation first initiated */ 422 } MEC_I2C_SMB0_CM_CMD_START0_Enum; 423 424 /* =========================================== MEC_I2C_SMB0 CM_CMD STARTN [9..9] =========================================== */ 425 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_STARTN */ 426 MEC_I2C_SMB0_CM_CMD_STARTN_EN = 1, /*!< EN : Generate an I2C START before last byte of write count */ 427 } MEC_I2C_SMB0_CM_CMD_STARTN_Enum; 428 429 /* =========================================== MEC_I2C_SMB0 CM_CMD STOP [10..10] =========================================== */ 430 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_STOP */ 431 MEC_I2C_SMB0_CM_CMD_STOP_EN = 1, /*!< EN : Generate an I2C STOP after write and read counts are both 432 0 */ 433 } MEC_I2C_SMB0_CM_CMD_STOP_Enum; 434 435 /* ========================================= MEC_I2C_SMB0 CM_CMD PEC_TERM [11..11] ========================================= */ 436 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_PEC_TERM */ 437 MEC_I2C_SMB0_CM_CMD_PEC_TERM_EN = 1, /*!< EN : Transmit PEC after write data is transmitted */ 438 } MEC_I2C_SMB0_CM_CMD_PEC_TERM_Enum; 439 440 /* ========================================== MEC_I2C_SMB0 CM_CMD READM [12..12] =========================================== */ 441 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_READM */ 442 MEC_I2C_SMB0_CM_CMD_READM_EN = 1, /*!< EN : Update read count with last read data value */ 443 } MEC_I2C_SMB0_CM_CMD_READM_Enum; 444 445 /* ========================================= MEC_I2C_SMB0 CM_CMD READ_PEC [13..13] ========================================= */ 446 typedef enum { /*!< MEC_I2C_SMB0_CM_CMD_READ_PEC */ 447 MEC_I2C_SMB0_CM_CMD_READ_PEC_EN = 1, /*!< EN : Read PEC byte from external device when read count reaches 448 0 */ 449 } MEC_I2C_SMB0_CM_CMD_READ_PEC_Enum; 450 451 /* ======================================================== TM_CMD ========================================================= */ 452 /* ============================================ MEC_I2C_SMB0 TM_CMD SRUN [0..0] ============================================ */ 453 typedef enum { /*!< MEC_I2C_SMB0_TM_CMD_SRUN */ 454 MEC_I2C_SMB0_TM_CMD_SRUN_START = 1, /*!< START : Start device mode network layer operation */ 455 } MEC_I2C_SMB0_TM_CMD_SRUN_Enum; 456 457 /* ========================================== MEC_I2C_SMB0 TM_CMD SPROCEED [1..1] ========================================== */ 458 typedef enum { /*!< MEC_I2C_SMB0_TM_CMD_SPROCEED */ 459 MEC_I2C_SMB0_TM_CMD_SPROCEED_ON = 1, /*!< ON : Inform network layer FW has finished re-configure and HW 460 can continue */ 461 } MEC_I2C_SMB0_TM_CMD_SPROCEED_Enum; 462 463 /* =========================================== MEC_I2C_SMB0 TM_CMD TX_PEC [2..2] =========================================== */ 464 typedef enum { /*!< MEC_I2C_SMB0_TM_CMD_TX_PEC */ 465 MEC_I2C_SMB0_TM_CMD_TX_PEC_EN = 1, /*!< EN : Transmit PEC after all write data is transmitted */ 466 } MEC_I2C_SMB0_TM_CMD_TX_PEC_Enum; 467 468 /* ========================================================== PEC ========================================================== */ 469 /* ========================================================= RSHT ========================================================== */ 470 /* ======================================================== EXTLEN ========================================================= */ 471 /* ========================================================= COMPL ========================================================= */ 472 /* ============================================ MEC_I2C_SMB0 COMPL DTEN [2..2] ============================================= */ 473 typedef enum { /*!< MEC_I2C_SMB0_COMPL_DTEN */ 474 MEC_I2C_SMB0_COMPL_DTEN_ON = 1, /*!< ON : Enable */ 475 } MEC_I2C_SMB0_COMPL_DTEN_Enum; 476 477 /* ============================================ MEC_I2C_SMB0 COMPL MCEN [3..3] ============================================= */ 478 typedef enum { /*!< MEC_I2C_SMB0_COMPL_MCEN */ 479 MEC_I2C_SMB0_COMPL_MCEN_ON = 1, /*!< ON : Enable */ 480 } MEC_I2C_SMB0_COMPL_MCEN_Enum; 481 482 /* ============================================ MEC_I2C_SMB0 COMPL SCEN [4..4] ============================================= */ 483 typedef enum { /*!< MEC_I2C_SMB0_COMPL_SCEN */ 484 MEC_I2C_SMB0_COMPL_SCEN_ON = 1, /*!< ON : Enable */ 485 } MEC_I2C_SMB0_COMPL_SCEN_Enum; 486 487 /* ============================================ MEC_I2C_SMB0 COMPL BIDEN [5..5] ============================================ */ 488 typedef enum { /*!< MEC_I2C_SMB0_COMPL_BIDEN */ 489 MEC_I2C_SMB0_COMPL_BIDEN_ON = 1, /*!< ON : Enable */ 490 } MEC_I2C_SMB0_COMPL_BIDEN_Enum; 491 492 /* =========================================== MEC_I2C_SMB0 COMPL TIMERR [6..6] ============================================ */ 493 typedef enum { /*!< MEC_I2C_SMB0_COMPL_TIMERR */ 494 MEC_I2C_SMB0_COMPL_TIMERR_ACTIVE = 1, /*!< ACTIVE : Status active */ 495 } MEC_I2C_SMB0_COMPL_TIMERR_Enum; 496 497 /* ============================================= MEC_I2C_SMB0 COMPL DTO [8..8] ============================================= */ 498 typedef enum { /*!< MEC_I2C_SMB0_COMPL_DTO */ 499 MEC_I2C_SMB0_COMPL_DTO_ACTIVE = 1, /*!< ACTIVE : Status active */ 500 } MEC_I2C_SMB0_COMPL_DTO_Enum; 501 502 /* ============================================ MEC_I2C_SMB0 COMPL MCTO [9..9] ============================================= */ 503 typedef enum { /*!< MEC_I2C_SMB0_COMPL_MCTO */ 504 MEC_I2C_SMB0_COMPL_MCTO_ACTIVE = 1, /*!< ACTIVE : Status active */ 505 } MEC_I2C_SMB0_COMPL_MCTO_Enum; 506 507 /* =========================================== MEC_I2C_SMB0 COMPL SCTO [10..10] ============================================ */ 508 typedef enum { /*!< MEC_I2C_SMB0_COMPL_SCTO */ 509 MEC_I2C_SMB0_COMPL_SCTO_ACTIVE = 1, /*!< ACTIVE : Status active */ 510 } MEC_I2C_SMB0_COMPL_SCTO_Enum; 511 512 /* =========================================== MEC_I2C_SMB0 COMPL CHDL [11..11] ============================================ */ 513 typedef enum { /*!< MEC_I2C_SMB0_COMPL_CHDL */ 514 MEC_I2C_SMB0_COMPL_CHDL_ACTIVE = 1, /*!< ACTIVE : Status active */ 515 } MEC_I2C_SMB0_COMPL_CHDL_Enum; 516 517 /* =========================================== MEC_I2C_SMB0 COMPL CHDH [12..12] ============================================ */ 518 typedef enum { /*!< MEC_I2C_SMB0_COMPL_CHDH */ 519 MEC_I2C_SMB0_COMPL_CHDH_ACTIVE = 1, /*!< ACTIVE : Status active */ 520 } MEC_I2C_SMB0_COMPL_CHDH_Enum; 521 522 /* ========================================== MEC_I2C_SMB0 COMPL BUSERR [13..13] =========================================== */ 523 typedef enum { /*!< MEC_I2C_SMB0_COMPL_BUSERR */ 524 MEC_I2C_SMB0_COMPL_BUSERR_ACTIVE = 1, /*!< ACTIVE : Status active */ 525 } MEC_I2C_SMB0_COMPL_BUSERR_Enum; 526 527 /* ========================================== MEC_I2C_SMB0 COMPL LABSTS [14..14] =========================================== */ 528 typedef enum { /*!< MEC_I2C_SMB0_COMPL_LABSTS */ 529 MEC_I2C_SMB0_COMPL_LABSTS_ACTIVE = 1, /*!< ACTIVE : Status active */ 530 } MEC_I2C_SMB0_COMPL_LABSTS_Enum; 531 532 /* =========================================== MEC_I2C_SMB0 COMPL SNAKR [16..16] =========================================== */ 533 typedef enum { /*!< MEC_I2C_SMB0_COMPL_SNAKR */ 534 MEC_I2C_SMB0_COMPL_SNAKR_ACTIVE = 1, /*!< ACTIVE : Status active */ 535 } MEC_I2C_SMB0_COMPL_SNAKR_Enum; 536 537 /* ============================================ MEC_I2C_SMB0 COMPL STR [17..17] ============================================ */ 538 typedef enum { /*!< MEC_I2C_SMB0_COMPL_STR */ 539 MEC_I2C_SMB0_COMPL_STR_ACTIVE = 1, /*!< ACTIVE : Status active */ 540 } MEC_I2C_SMB0_COMPL_STR_Enum; 541 542 /* =========================================== MEC_I2C_SMB0 COMPL SPROT [19..19] =========================================== */ 543 typedef enum { /*!< MEC_I2C_SMB0_COMPL_SPROT */ 544 MEC_I2C_SMB0_COMPL_SPROT_ACTIVE = 1, /*!< ACTIVE : Status active */ 545 } MEC_I2C_SMB0_COMPL_SPROT_Enum; 546 547 /* =========================================== MEC_I2C_SMB0 COMPL RPTRD [20..20] =========================================== */ 548 typedef enum { /*!< MEC_I2C_SMB0_COMPL_RPTRD */ 549 MEC_I2C_SMB0_COMPL_RPTRD_ACTIVE = 1, /*!< ACTIVE : Status active */ 550 } MEC_I2C_SMB0_COMPL_RPTRD_Enum; 551 552 /* =========================================== MEC_I2C_SMB0 COMPL RPTWR [21..21] =========================================== */ 553 typedef enum { /*!< MEC_I2C_SMB0_COMPL_RPTWR */ 554 MEC_I2C_SMB0_COMPL_RPTWR_ACTIVE = 1, /*!< ACTIVE : Status active */ 555 } MEC_I2C_SMB0_COMPL_RPTWR_Enum; 556 557 /* =========================================== MEC_I2C_SMB0 COMPL MNAKX [24..24] =========================================== */ 558 typedef enum { /*!< MEC_I2C_SMB0_COMPL_MNAKX */ 559 MEC_I2C_SMB0_COMPL_MNAKX_ACTIVE = 1, /*!< ACTIVE : Status active */ 560 } MEC_I2C_SMB0_COMPL_MNAKX_Enum; 561 562 /* ============================================ MEC_I2C_SMB0 COMPL MTR [25..25] ============================================ */ 563 typedef enum { /*!< MEC_I2C_SMB0_COMPL_MTR */ 564 MEC_I2C_SMB0_COMPL_MTR_ACTIVE = 1, /*!< ACTIVE : Status active */ 565 } MEC_I2C_SMB0_COMPL_MTR_Enum; 566 567 /* =========================================== MEC_I2C_SMB0 COMPL IDLE [29..29] ============================================ */ 568 typedef enum { /*!< MEC_I2C_SMB0_COMPL_IDLE */ 569 MEC_I2C_SMB0_COMPL_IDLE_ACTIVE = 1, /*!< ACTIVE : Status active */ 570 } MEC_I2C_SMB0_COMPL_IDLE_Enum; 571 572 /* =========================================== MEC_I2C_SMB0 COMPL MDONE [30..30] =========================================== */ 573 typedef enum { /*!< MEC_I2C_SMB0_COMPL_MDONE */ 574 MEC_I2C_SMB0_COMPL_MDONE_ACTIVE = 1, /*!< ACTIVE : Status active */ 575 } MEC_I2C_SMB0_COMPL_MDONE_Enum; 576 577 /* =========================================== MEC_I2C_SMB0 COMPL SDONE [31..31] =========================================== */ 578 typedef enum { /*!< MEC_I2C_SMB0_COMPL_SDONE */ 579 MEC_I2C_SMB0_COMPL_SDONE_ACTIVE = 1, /*!< ACTIVE : Status active */ 580 } MEC_I2C_SMB0_COMPL_SDONE_Enum; 581 582 /* ======================================================== IDLESC ========================================================= */ 583 /* ======================================================== CONFIG ========================================================= */ 584 /* ========================================== MEC_I2C_SMB0 CONFIG PORT_SEL [0..3] ========================================== */ 585 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_PORT_SEL */ 586 MEC_I2C_SMB0_CONFIG_PORT_SEL_P0 = 0, /*!< P0 : Port 0 */ 587 MEC_I2C_SMB0_CONFIG_PORT_SEL_P1 = 1, /*!< P1 : Port 1 */ 588 MEC_I2C_SMB0_CONFIG_PORT_SEL_P2 = 2, /*!< P2 : Port 2 */ 589 MEC_I2C_SMB0_CONFIG_PORT_SEL_P3 = 3, /*!< P3 : Port 3 */ 590 MEC_I2C_SMB0_CONFIG_PORT_SEL_P4 = 4, /*!< P4 : Port 4 */ 591 MEC_I2C_SMB0_CONFIG_PORT_SEL_P5 = 5, /*!< P5 : Port 5 */ 592 MEC_I2C_SMB0_CONFIG_PORT_SEL_P6 = 6, /*!< P6 : Port 6 */ 593 MEC_I2C_SMB0_CONFIG_PORT_SEL_P7 = 7, /*!< P7 : Port 7 */ 594 MEC_I2C_SMB0_CONFIG_PORT_SEL_P8 = 8, /*!< P8 : Port 8 */ 595 MEC_I2C_SMB0_CONFIG_PORT_SEL_P9 = 9, /*!< P9 : Port 9 */ 596 MEC_I2C_SMB0_CONFIG_PORT_SEL_P10 = 10, /*!< P10 : Port 10 */ 597 MEC_I2C_SMB0_CONFIG_PORT_SEL_P11 = 11, /*!< P11 : Port 11 */ 598 MEC_I2C_SMB0_CONFIG_PORT_SEL_P12 = 12, /*!< P12 : Port 12 */ 599 MEC_I2C_SMB0_CONFIG_PORT_SEL_P13 = 13, /*!< P13 : Port 13 */ 600 MEC_I2C_SMB0_CONFIG_PORT_SEL_P14 = 14, /*!< P14 : Port 14 */ 601 MEC_I2C_SMB0_CONFIG_PORT_SEL_P15 = 15, /*!< P15 : Port 15 */ 602 } MEC_I2C_SMB0_CONFIG_PORT_SEL_Enum; 603 604 /* ============================================ MEC_I2C_SMB0 CONFIG TCEN [4..4] ============================================ */ 605 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_TCEN */ 606 MEC_I2C_SMB0_CONFIG_TCEN_ON = 1, /*!< ON : Enable */ 607 } MEC_I2C_SMB0_CONFIG_TCEN_Enum; 608 609 /* ========================================== MEC_I2C_SMB0 CONFIG SLOW_CLK [5..5] ========================================== */ 610 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_SLOW_CLK */ 611 MEC_I2C_SMB0_CONFIG_SLOW_CLK_EN = 1, /*!< EN : Enable */ 612 } MEC_I2C_SMB0_CONFIG_SLOW_CLK_Enum; 613 614 /* ============================================ MEC_I2C_SMB0 CONFIG PCEN [7..7] ============================================ */ 615 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_PCEN */ 616 MEC_I2C_SMB0_CONFIG_PCEN_ON = 1, /*!< ON : Enable */ 617 } MEC_I2C_SMB0_CONFIG_PCEN_Enum; 618 619 /* ============================================ MEC_I2C_SMB0 CONFIG FEN [8..8] ============================================= */ 620 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_FEN */ 621 MEC_I2C_SMB0_CONFIG_FEN_ON = 1, /*!< ON : Enable */ 622 } MEC_I2C_SMB0_CONFIG_FEN_Enum; 623 624 /* =========================================== MEC_I2C_SMB0 CONFIG RESET [9..9] ============================================ */ 625 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_RESET */ 626 MEC_I2C_SMB0_CONFIG_RESET_EN = 1, /*!< EN : Enable */ 627 } MEC_I2C_SMB0_CONFIG_RESET_Enum; 628 629 /* =========================================== MEC_I2C_SMB0 CONFIG ENAB [10..10] =========================================== */ 630 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_ENAB */ 631 MEC_I2C_SMB0_CONFIG_ENAB_ON = 1, /*!< ON : Enable */ 632 } MEC_I2C_SMB0_CONFIG_ENAB_Enum; 633 634 /* =========================================== MEC_I2C_SMB0 CONFIG DSA [11..11] ============================================ */ 635 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_DSA */ 636 MEC_I2C_SMB0_CONFIG_DSA_EN = 1, /*!< EN : Enable */ 637 } MEC_I2C_SMB0_CONFIG_DSA_Enum; 638 639 /* ========================================= MEC_I2C_SMB0 CONFIG MCTP_FEN [12..12] ========================================= */ 640 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_MCTP_FEN */ 641 MEC_I2C_SMB0_CONFIG_MCTP_FEN_ON = 1, /*!< ON : Enable */ 642 } MEC_I2C_SMB0_CONFIG_MCTP_FEN_Enum; 643 644 /* ========================================== MEC_I2C_SMB0 CONFIG GC_DIS [14..14] ========================================== */ 645 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_GC_DIS */ 646 MEC_I2C_SMB0_CONFIG_GC_DIS_ON = 1, /*!< ON : Enable */ 647 } MEC_I2C_SMB0_CONFIG_GC_DIS_Enum; 648 649 /* ========================================== MEC_I2C_SMB0 CONFIG PROMEN [15..15] ========================================== */ 650 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_PROMEN */ 651 MEC_I2C_SMB0_CONFIG_PROMEN_ON = 1, /*!< ON : Enable */ 652 } MEC_I2C_SMB0_CONFIG_PROMEN_Enum; 653 654 /* ======================================= MEC_I2C_SMB0 CONFIG FLUSH_TM_TXB [16..16] ======================================= */ 655 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_FLUSH_TM_TXB */ 656 MEC_I2C_SMB0_CONFIG_FLUSH_TM_TXB_EN = 1, /*!< EN : Enable */ 657 } MEC_I2C_SMB0_CONFIG_FLUSH_TM_TXB_Enum; 658 659 /* ======================================= MEC_I2C_SMB0 CONFIG FLUSH_TM_RXB [17..17] ======================================= */ 660 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_FLUSH_TM_RXB */ 661 MEC_I2C_SMB0_CONFIG_FLUSH_TM_RXB_EN = 1, /*!< EN : Enable */ 662 } MEC_I2C_SMB0_CONFIG_FLUSH_TM_RXB_Enum; 663 664 /* ======================================== MEC_I2C_SMB0 CONFIG FLUSH_CTXB [18..18] ======================================== */ 665 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_FLUSH_CTXB */ 666 MEC_I2C_SMB0_CONFIG_FLUSH_CTXB_EN = 1, /*!< EN : Enable */ 667 } MEC_I2C_SMB0_CONFIG_FLUSH_CTXB_Enum; 668 669 /* ======================================== MEC_I2C_SMB0 CONFIG FLUSH_CRXB [19..19] ======================================== */ 670 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_FLUSH_CRXB */ 671 MEC_I2C_SMB0_CONFIG_FLUSH_CRXB_EN = 1, /*!< EN : Enable */ 672 } MEC_I2C_SMB0_CONFIG_FLUSH_CRXB_Enum; 673 674 /* ========================================= MEC_I2C_SMB0 CONFIG ENI_AAS [28..28] ========================================== */ 675 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_ENI_AAS */ 676 MEC_I2C_SMB0_CONFIG_ENI_AAS_EN = 1, /*!< EN : Enable */ 677 } MEC_I2C_SMB0_CONFIG_ENI_AAS_Enum; 678 679 /* ========================================= MEC_I2C_SMB0 CONFIG ENI_IDLE [29..29] ========================================= */ 680 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_ENI_IDLE */ 681 MEC_I2C_SMB0_CONFIG_ENI_IDLE_EN = 1, /*!< EN : Enable */ 682 } MEC_I2C_SMB0_CONFIG_ENI_IDLE_Enum; 683 684 /* =========================================== MEC_I2C_SMB0 CONFIG ENMI [30..30] =========================================== */ 685 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_ENMI */ 686 MEC_I2C_SMB0_CONFIG_ENMI_EN = 1, /*!< EN : Enable */ 687 } MEC_I2C_SMB0_CONFIG_ENMI_Enum; 688 689 /* =========================================== MEC_I2C_SMB0 CONFIG ENSI [31..31] =========================================== */ 690 typedef enum { /*!< MEC_I2C_SMB0_CONFIG_ENSI */ 691 MEC_I2C_SMB0_CONFIG_ENSI_EN = 1, /*!< EN : Enable */ 692 } MEC_I2C_SMB0_CONFIG_ENSI_Enum; 693 694 /* ======================================================== BUSCLK ========================================================= */ 695 /* ========================================================= BLKID ========================================================= */ 696 /* ======================================================== BLKREV ========================================================= */ 697 /* ======================================================== BBCTRL ========================================================= */ 698 /* ============================================ MEC_I2C_SMB0 BBCTRL BBEN [0..0] ============================================ */ 699 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_BBEN */ 700 MEC_I2C_SMB0_BBCTRL_BBEN_ON = 1, /*!< ON : Enable */ 701 } MEC_I2C_SMB0_BBCTRL_BBEN_Enum; 702 703 /* =========================================== MEC_I2C_SMB0 BBCTRL CLDIR [1..1] ============================================ */ 704 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_CLDIR */ 705 MEC_I2C_SMB0_BBCTRL_CLDIR_OUT = 1, /*!< OUT : SCL pin is output(driven) otherwise tri-stated */ 706 } MEC_I2C_SMB0_BBCTRL_CLDIR_Enum; 707 708 /* =========================================== MEC_I2C_SMB0 BBCTRL DADIR [2..2] ============================================ */ 709 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_DADIR */ 710 MEC_I2C_SMB0_BBCTRL_DADIR_OUT = 1, /*!< OUT : SDA pin is output(driven) otherwise tri-stated */ 711 } MEC_I2C_SMB0_BBCTRL_DADIR_Enum; 712 713 /* =========================================== MEC_I2C_SMB0 BBCTRL BBCLK [3..3] ============================================ */ 714 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_BBCLK */ 715 MEC_I2C_SMB0_BBCTRL_BBCLK_HI = 1, /*!< HI : SCL pin output state is high */ 716 } MEC_I2C_SMB0_BBCTRL_BBCLK_Enum; 717 718 /* =========================================== MEC_I2C_SMB0 BBCTRL BBDAT [4..4] ============================================ */ 719 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_BBDAT */ 720 MEC_I2C_SMB0_BBCTRL_BBDAT_HI = 1, /*!< HI : SDA pin output state is high */ 721 } MEC_I2C_SMB0_BBCTRL_BBDAT_Enum; 722 723 /* =========================================== MEC_I2C_SMB0 BBCTRL BBCLKI [5..5] =========================================== */ 724 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_BBCLKI */ 725 MEC_I2C_SMB0_BBCTRL_BBCLKI_HI = 1, /*!< HI : SCL pin state read as high */ 726 } MEC_I2C_SMB0_BBCTRL_BBCLKI_Enum; 727 728 /* =========================================== MEC_I2C_SMB0 BBCTRL BBDATI [6..6] =========================================== */ 729 typedef enum { /*!< MEC_I2C_SMB0_BBCTRL_BBDATI */ 730 MEC_I2C_SMB0_BBCTRL_BBDATI_HI = 1, /*!< HI : SDA pin state read as high */ 731 } MEC_I2C_SMB0_BBCTRL_BBDATI_Enum; 732 733 /* ======================================================== MCHPR3C ======================================================== */ 734 /* ======================================================== DATATM ========================================================= */ 735 /* ======================================================== TMOUTSC ======================================================== */ 736 /* ======================================================== TM_TXB ========================================================= */ 737 /* ======================================================== TM_RXB ========================================================= */ 738 /* ======================================================== CM_TXB ========================================================= */ 739 /* ======================================================== CM_RXB ========================================================= */ 740 /* ======================================================== FSM_I2C ======================================================== */ 741 /* ========================================= MEC_I2C_SMB0 FSM_I2C CM_STATE [0..7] ========================================== */ 742 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_CM_STATE */ 743 MEC_I2C_SMB0_FSM_I2C_CM_STATE_IDLE = 0, /*!< IDLE : CM in Idle state */ 744 MEC_I2C_SMB0_FSM_I2C_CM_STATE_W4_START = 1, /*!< W4_START : CM waiting on phy to complete START on pins */ 745 MEC_I2C_SMB0_FSM_I2C_CM_STATE_ADDR = 2, /*!< ADDR : CM target address transmit */ 746 MEC_I2C_SMB0_FSM_I2C_CM_STATE_CHK_ACK = 3, /*!< CHK_ACK : CM sample SDA on 9th clock for ACK state */ 747 MEC_I2C_SMB0_FSM_I2C_CM_STATE_RX_DATA = 4, /*!< RX_DATA : CM generate clocks and sample SDA for data from target */ 748 MEC_I2C_SMB0_FSM_I2C_CM_STATE_RX_DATA_ACK = 5,/*!< RX_DATA_ACK : CM generate ACK/NACK on 9th clock */ 749 MEC_I2C_SMB0_FSM_I2C_CM_STATE_TX = 6, /*!< TX : CM generate clocks and shift data onto SDA */ 750 MEC_I2C_SMB0_FSM_I2C_CM_STATE_TX_ACK = 7, /*!< TX_ACK : CM generate 9th clock and sample SDA for ACK/NACK from 751 target */ 752 MEC_I2C_SMB0_FSM_I2C_CM_STATE_WAIT_ACK = 8, /*!< WAIT_ACK : CM wait for ACK if target clock stretching */ 753 MEC_I2C_SMB0_FSM_I2C_CM_STATE_W4_STOP = 9, /*!< W4_STOP : CM wait for phy to complete STOP signalling */ 754 MEC_I2C_SMB0_FSM_I2C_CM_STATE_LOST_ARB = 10, /*!< LOST_ARB : CM lost arbitration */ 755 MEC_I2C_SMB0_FSM_I2C_CM_STATE_LOST_ARB_SR = 11,/*!< LOST_ARB_SR : CM lost arbitration SR */ 756 MEC_I2C_SMB0_FSM_I2C_CM_STATE_LOST_ARB_SR_D1 = 12,/*!< LOST_ARB_SR_D1 : CM lost arbitration SRD1 */ 757 MEC_I2C_SMB0_FSM_I2C_CM_STATE_LOST_ARB_SR_D2 = 13,/*!< LOST_ARB_SR_D2 : CM lost arbitration SRD2 */ 758 MEC_I2C_SMB0_FSM_I2C_CM_STATE_W4_START_HOLD = 14,/*!< W4_START_HOLD : CM enforce delay after STOP before issuing another 759 START */ 760 } MEC_I2C_SMB0_FSM_I2C_CM_STATE_Enum; 761 762 /* ========================================= MEC_I2C_SMB0 FSM_I2C TM_STATE [8..15] ========================================= */ 763 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_TM_STATE */ 764 MEC_I2C_SMB0_FSM_I2C_TM_STATE_IDLE = 0, /*!< IDLE : TM FSM idle */ 765 MEC_I2C_SMB0_FSM_I2C_TM_STATE_HDR_ACK = 1, /*!< HDR_ACK : TM ACK/NACK address from external Controller */ 766 MEC_I2C_SMB0_FSM_I2C_TM_STATE_TX_DATA = 2, /*!< TX_DATA : TM transmit data on SDA to external controller */ 767 MEC_I2C_SMB0_FSM_I2C_TM_STATE_WAIT_ACK = 3, /*!< WAIT_ACK : TM wait for 9th clock ACK/NACK from external controller */ 768 MEC_I2C_SMB0_FSM_I2C_TM_STATE_RX_DATA = 4, /*!< RX_DATA : TM samples data on SDA from external controller */ 769 MEC_I2C_SMB0_FSM_I2C_TM_STATE_ACK_DATA = 5, /*!< ACK_DATA : TM ACK/NACK data received from external controller */ 770 } MEC_I2C_SMB0_FSM_I2C_TM_STATE_Enum; 771 772 /* ======================================== MEC_I2C_SMB0 FSM_I2C PHY_STATE [16..19] ======================================== */ 773 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_PHY_STATE */ 774 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_IDLE = 0, /*!< IDLE : Phy is idle */ 775 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_CLKHI = 1, /*!< CLKHI : Phy released SCL to go high */ 776 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_SS = 2, /*!< SS : Phy sample state */ 777 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_CLKLO = 3, /*!< CLKLO : Phy drive SCL low */ 778 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_SDAT_CTRL = 4, /*!< SDAT_CTRL : Phy driving/releasing SDAT */ 779 MEC_I2C_SMB0_FSM_I2C_PHY_STATE_ARB_LOSS = 5, /*!< ARB_LOSS : Phy detected arbitration loss */ 780 } MEC_I2C_SMB0_FSM_I2C_PHY_STATE_Enum; 781 782 /* ========================================= MEC_I2C_SMB0 FSM_I2C CM_CTO [20..23] ========================================== */ 783 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_CM_CTO */ 784 MEC_I2C_SMB0_FSM_I2C_CM_CTO_NOT_COUNTING = 0, /*!< NOT_COUNTING : CM CTO is not counting */ 785 MEC_I2C_SMB0_FSM_I2C_CM_CTO_COUNTING = 1, /*!< COUNTING : CM CTO is counting */ 786 } MEC_I2C_SMB0_FSM_I2C_CM_CTO_Enum; 787 788 /* ========================================= MEC_I2C_SMB0 FSM_I2C TM_CTO [24..28] ========================================== */ 789 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_TM_CTO */ 790 MEC_I2C_SMB0_FSM_I2C_TM_CTO_NOT_COUNTING = 0, /*!< NOT_COUNTING : TM CTO is not counting */ 791 MEC_I2C_SMB0_FSM_I2C_TM_CTO_COUNTING = 1, /*!< COUNTING : TM CTO is counting */ 792 } MEC_I2C_SMB0_FSM_I2C_TM_CTO_Enum; 793 794 /* ========================================== MEC_I2C_SMB0 FSM_I2C CM_BI [29..31] ========================================== */ 795 typedef enum { /*!< MEC_I2C_SMB0_FSM_I2C_CM_BI */ 796 MEC_I2C_SMB0_FSM_I2C_CM_BI_NOT_COUNTING = 0, /*!< NOT_COUNTING : CM BI is not counting */ 797 MEC_I2C_SMB0_FSM_I2C_CM_BI_COUNTING = 1, /*!< COUNTING : CM BI is counting */ 798 } MEC_I2C_SMB0_FSM_I2C_CM_BI_Enum; 799 800 /* ======================================================== FSM_SNL ======================================================== */ 801 /* ========================================= MEC_I2C_SMB0 FSM_SNL CM_STATE [0..7] ========================================== */ 802 typedef enum { /*!< MEC_I2C_SMB0_FSM_SNL_CM_STATE */ 803 MEC_I2C_SMB0_FSM_SNL_CM_STATE_IDLE = 0, /*!< IDLE : SNL CM state is idle */ 804 MEC_I2C_SMB0_FSM_SNL_CM_STATE_SOP = 1, /*!< SOP : SNL CM SOP state */ 805 MEC_I2C_SMB0_FSM_SNL_CM_STATE_START = 2, /*!< START : SNL CM start state */ 806 MEC_I2C_SMB0_FSM_SNL_CM_STATE_START_PIN = 3, /*!< START_PIN : SNL CM start pin state */ 807 MEC_I2C_SMB0_FSM_SNL_CM_STATE_WDATA = 4, /*!< WDATA : SNL CM transmit data state */ 808 MEC_I2C_SMB0_FSM_SNL_CM_STATE_WPEC = 5, /*!< WPEC : SNL CM transmit PEC byte state */ 809 MEC_I2C_SMB0_FSM_SNL_CM_STATE_RSTART = 6, /*!< RSTART : SNL CM receive start state */ 810 MEC_I2C_SMB0_FSM_SNL_CM_STATE_RSTART_PIN = 7, /*!< RSTART_PIN : SNL CM receive start pin state */ 811 MEC_I2C_SMB0_FSM_SNL_CM_STATE_RDATA_IN = 8, /*!< RDATA_IN : SNL CM receive data input state */ 812 MEC_I2C_SMB0_FSM_SNL_CM_STATE_RDATA_PEC = 9, /*!< RDATA_PEC : SNL CM receive data pec state */ 813 MEC_I2C_SMB0_FSM_SNL_CM_STATE_RPEC = 10, /*!< RPEC : SNL CM receive data check pec state */ 814 MEC_I2C_SMB0_FSM_SNL_CM_STATE_PAUSE = 11, /*!< PAUSE : SNL CM pause state */ 815 MEC_I2C_SMB0_FSM_SNL_CM_STATE_STOP = 12, /*!< STOP : SNL CM stop state */ 816 MEC_I2C_SMB0_FSM_SNL_CM_STATE_EOP = 13, /*!< EOP : SNL CM EOP state */ 817 } MEC_I2C_SMB0_FSM_SNL_CM_STATE_Enum; 818 819 /* ========================================= MEC_I2C_SMB0 FSM_SNL TM_STATE [8..15] ========================================= */ 820 typedef enum { /*!< MEC_I2C_SMB0_FSM_SNL_TM_STATE */ 821 MEC_I2C_SMB0_FSM_SNL_TM_STATE_IDLE = 0, /*!< IDLE : SNL TM idle state */ 822 MEC_I2C_SMB0_FSM_SNL_TM_STATE_ADDR = 1, /*!< ADDR : SNL TM address state */ 823 MEC_I2C_SMB0_FSM_SNL_TM_STATE_WPIN = 2, /*!< WPIN : SNL TM WPIN state */ 824 MEC_I2C_SMB0_FSM_SNL_TM_STATE_RPIN = 3, /*!< RPIN : SNL TM RPIN state */ 825 MEC_I2C_SMB0_FSM_SNL_TM_STATE_WDATA = 4, /*!< WDATA : SNL TM transmit data state */ 826 MEC_I2C_SMB0_FSM_SNL_TM_STATE_RDATA = 5, /*!< RDATA : SNL TM receive data state */ 827 MEC_I2C_SMB0_FSM_SNL_TM_STATE_RBE = 6, /*!< RBE : SNL TM RBE state */ 828 MEC_I2C_SMB0_FSM_SNL_TM_STATE_TM_RPEC = 7, /*!< TM_RPEC : SNL TM receive PEC state */ 829 MEC_I2C_SMB0_FSM_SNL_TM_STATE_TM_RPEC_RPT = 8,/*!< TM_RPEC_RPT : SNL TM check receive PEC state */ 830 } MEC_I2C_SMB0_FSM_SNL_TM_STATE_Enum; 831 832 /* ======================================== MEC_I2C_SMB0 FSM_SNL MCTP_FAIR [16..23] ======================================== */ 833 typedef enum { /*!< MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR */ 834 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_IDLE = 0, /*!< IDLE : MCTP fairness FSM is idle */ 835 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_BUSY = 1, /*!< BUSY : MCTP fairness FSM is busy */ 836 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_WINDOW = 2, /*!< WINDOW : MCTP fairness in window */ 837 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_DELAY = 3, /*!< DELAY : MCTP fairness delay state */ 838 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_WAIT = 4, /*!< WAIT : MCTP fairness wait state */ 839 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_WAIT_DONE = 5, /*!< WAIT_DONE : MCTP fairness wait done state */ 840 MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_ACTIVE = 6, /*!< ACTIVE : MCTP fairness active state */ 841 } MEC_I2C_SMB0_FSM_SNL_MCTP_FAIR_Enum; 842 843 /* ======================================================= WAKE_STS ======================================================== */ 844 /* ======================================== MEC_I2C_SMB0 WAKE_STS START_DET [0..0] ========================================= */ 845 typedef enum { /*!< MEC_I2C_SMB0_WAKE_STS_START_DET */ 846 MEC_I2C_SMB0_WAKE_STS_START_DET_ACTIVE = 1, /*!< ACTIVE : Active */ 847 } MEC_I2C_SMB0_WAKE_STS_START_DET_Enum; 848 849 /* ======================================================== WAKE_EN ======================================================== */ 850 /* ========================================= MEC_I2C_SMB0 WAKE_EN START_DET [0..0] ========================================= */ 851 typedef enum { /*!< MEC_I2C_SMB0_WAKE_EN_START_DET */ 852 MEC_I2C_SMB0_WAKE_EN_START_DET_IEN = 1, /*!< IEN : Enable */ 853 } MEC_I2C_SMB0_WAKE_EN_START_DET_Enum; 854 855 /* ====================================================== FAST_RSYNC ======================================================= */ 856 /* ======================================================= SHAD_ADDR ======================================================= */ 857 /* ======================================================= PROM_ARS ======================================================== */ 858 /* ========================================== MEC_I2C_SMB0 PROM_ARS ARSTS [0..0] =========================================== */ 859 typedef enum { /*!< MEC_I2C_SMB0_PROM_ARS_ARSTS */ 860 MEC_I2C_SMB0_PROM_ARS_ARSTS_ACTIVE = 1, /*!< ACTIVE : Active */ 861 } MEC_I2C_SMB0_PROM_ARS_ARSTS_Enum; 862 863 /* ======================================================= PROM_IEN ======================================================== */ 864 /* =========================================== MEC_I2C_SMB0 PROM_IEN ARI [0..0] ============================================ */ 865 typedef enum { /*!< MEC_I2C_SMB0_PROM_IEN_ARI */ 866 MEC_I2C_SMB0_PROM_IEN_ARI_EN = 1, /*!< EN : Enable */ 867 } MEC_I2C_SMB0_PROM_IEN_ARI_Enum; 868 869 /* ======================================================= PROM_CTRL ======================================================= */ 870 /* ========================================== MEC_I2C_SMB0 PROM_CTRL ARACK [0..0] ========================================== */ 871 typedef enum { /*!< MEC_I2C_SMB0_PROM_CTRL_ARACK */ 872 MEC_I2C_SMB0_PROM_CTRL_ARACK_GEN = 1, /*!< GEN : Generate ACK */ 873 } MEC_I2C_SMB0_PROM_CTRL_ARACK_Enum; 874 875 /** @} */ /* End of group EnumValue_peripherals */ 876 877 #endif /* _MEC5_I2C_SMB_V3_7_H */ 878
