1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_ESPI_TAF_V1_4_H 7 #define _MEC5_ESPI_TAF_V1_4_H 8 9 /** @addtogroup Device_Peripheral_clusters 10 * @{ 11 */ 12 13 /** 14 * @brief MEC_ESPI_TAF_PR [PR] (TAF 17 Flash Protection Regions) 15 */ 16 typedef struct mec_espi_taf_pr_regs { 17 __IOM uint32_t START; /*!< (@ 0x00000000) TAF Flash Protection Region n start flash address */ 18 __IOM uint32_t LIMIT; /*!< (@ 0x00000004) TAF Flash Protection Region n limit address */ 19 __IOM uint32_t WRBM; /*!< (@ 0x00000008) TAF Flash Protection Region write protect Host 20 ID bitmap */ 21 __IOM uint32_t RDBM; /*!< (@ 0x0000000C) TAF Flash Protection Region read protect Host 22 ID bitmap */ 23 } MEC_ESPI_TAF_PR_Type; /*!< Size = 16 (0x10) */ 24 /** @} */ /* End of group Device_Peripheral_clusters */ 25 26 /** @addtogroup Device_Peripheral_peripherals 27 * @{ 28 */ 29 /** 30 * @brief eSPI TAF Communication Logic (MEC_ESPI_TAF_COMM) 31 */ 32 33 typedef struct mec_espi_taf_comm_regs { /*!< (@ 0x40071000) MEC_ESPI_TAF_COMM Structure */ 34 __IM uint32_t RESERVED[174]; 35 __IOM uint32_t COMM_MODE; /*!< (@ 0x000002B8) eSPI TAF Communication Mode register */ 36 } MEC_ESPI_TAF_COMM_Type; /*!< Size = 700 (0x2bc) */ 37 38 /** 39 * @brief eSPI TAF (MEC_ESPI_TAF) 40 */ 41 42 typedef struct mec_espi_taf_regs { /*!< (@ 0x40008000) MEC_ESPI_TAF Structure */ 43 __IM uint32_t RESERVED[6]; 44 __IOM uint32_t ECP_CMD; /*!< (@ 0x00000018) eSPI TAF EC Portal Command register */ 45 __IOM uint32_t ECP_FADDR; /*!< (@ 0x0000001C) eSPI TAF EC Portal Flash Address register */ 46 __IOM uint32_t ECP_START; /*!< (@ 0x00000020) eSPI TAF EC Portal Start register */ 47 __IOM uint32_t ECP_BADDR; /*!< (@ 0x00000024) eSPI TAF EC Portal Buffer Address. Must be 32-bit 48 aligned */ 49 __IOM uint32_t ECP_STS; /*!< (@ 0x00000028) eSPI TAF EC Portal Status register */ 50 __IOM uint32_t ECP_IEN; /*!< (@ 0x0000002C) eSPI TAF EC Portal Interrupt Enable register */ 51 __IOM uint32_t FC_SZ_LIM; /*!< (@ 0x00000030) eSPI TAF Flash Configuration Size Limit register */ 52 __IOM uint32_t FC_THR; /*!< (@ 0x00000034) eSPI TAF Flash Configuration Threshold register */ 53 __IOM uint32_t FC_MISC; /*!< (@ 0x00000038) eSPI TAF Flash Configuration Miscellaneous register */ 54 __IOM uint32_t MON_STS; /*!< (@ 0x0000003C) eSPI TAF Monitor Status register */ 55 __IOM uint32_t MON_IEN; /*!< (@ 0x00000040) eSPI TAF Monitor Interrupt Enable register */ 56 __IM uint32_t ECP_BUSY_STS; /*!< (@ 0x00000044) eSPI TAF EC Busy register */ 57 __IM uint32_t RESERVED1; 58 __IOM uint32_t CS0_OPA; /*!< (@ 0x0000004C) Chip select 0 Opcode A flash commands register */ 59 __IOM uint32_t CS0_OPB; /*!< (@ 0x00000050) Chip select 0 Opcode B flash commands register */ 60 __IOM uint32_t CS0_OPC; /*!< (@ 0x00000054) Chip select 0 Opcode C flash commands register */ 61 __IOM uint32_t CS0_OP_DESCR; /*!< (@ 0x00000058) TAF chip select 0 opcode start descriptor indices */ 62 __IOM uint32_t CS1_OPA; /*!< (@ 0x0000005C) Chip select 1 Opcode A flash commands register */ 63 __IOM uint32_t CS1_OPB; /*!< (@ 0x00000060) Chip select 1 Opcode B flash commands register */ 64 __IOM uint32_t CS1_OPC; /*!< (@ 0x00000064) Chip select 1 Opcode C flash commands register */ 65 __IOM uint32_t CS1_OP_DESCR; /*!< (@ 0x00000068) TAF chip select 1 opcode start descriptor indices */ 66 __IOM uint32_t GEN_DESCR; /*!< (@ 0x0000006C) TAF Flash Configuration Generate descriptor indices 67 register */ 68 __IOM uint32_t PR_LOCK; /*!< (@ 0x00000070) TAF Protection Region Lock Flash register */ 69 __IOM uint32_t PR_DIRTY; /*!< (@ 0x00000074) TAF Protection Region Dirty Status */ 70 __IOM uint32_t TAG_MAP0; /*!< (@ 0x00000078) TAF Tag Map 0 register */ 71 __IOM uint32_t TAG_MAP1; /*!< (@ 0x0000007C) TAF Tag Map 1 register */ 72 __IOM uint32_t TAG_MAP2; /*!< (@ 0x00000080) TAF Tag Map 2 register */ 73 __IOM MEC_ESPI_TAF_PR_Type PR[17]; /*!< (@ 0x00000084) TAF 17 Flash Protection Regions */ 74 __IOM uint32_t POLL_TIMEOUT; /*!< (@ 0x00000194) TAF flash poll timeout in units of 32KHz clock 75 periods */ 76 __IOM uint32_t POLL_INTERVAL; /*!< (@ 0x00000198) TAF flash poll interval in units of 48MHz clock 77 periods */ 78 __IOM uint32_t SR_INTERVAL; /*!< (@ 0x0000019C) TAF flash suspend/resume interval in units of 79 32KHz clock periods */ 80 __IOM uint32_t CRD_TIMEOUT; /*!< (@ 0x000001A0) TAF flash consecutive read timeout in units of 81 48MHz clock periods */ 82 __IOM uint32_t POLL2_MSKS; /*!< (@ 0x000001A4) TAF enging flash configuration poll2 mask register */ 83 __IOM uint32_t FC_SMODE; /*!< (@ 0x000001A8) TAF enging flash configuration special mode register */ 84 __IOM uint32_t SUS_CHK_DLY; /*!< (@ 0x000001AC) TAF suspend check delay in units of 48MHz clock 85 periods */ 86 __IOM uint32_t FC_CM_PREFIX; /*!< (@ 0x000001B0) Flash Configuration continuous mode prefix */ 87 __IOM uint32_t DNX_PR_BYP; /*!< (@ 0x000001B4) TAF DNF Protection Bypass */ 88 __IOM uint32_t ACT_CNT_RLOAD; /*!< (@ 0x000001B8) TAF Activity Count Reload register */ 89 __IOM uint32_t PD_CTRL; /*!< (@ 0x000001BC) TAF Power Down Control register */ 90 __IOM uint32_t PD_STS; /*!< (@ 0x000001C0) TAF Flash Power Down Status register */ 91 __IOM uint32_t CS0_OPD; /*!< (@ 0x000001C4) TAF Config CS0 opcode D register */ 92 __IOM uint32_t CS1_OPD; /*!< (@ 0x000001C8) TAF Config CS1 opcode D register */ 93 __IOM uint32_t PUD_TIMEOUT; /*!< (@ 0x000001CC) TAF Flash power up/down timeout register in units 94 of 48MHz clock periods */ 95 __IM uint32_t RESERVED2[12]; 96 __IOM uint32_t CLKDIV_CS0; /*!< (@ 0x00000200) TAF chip select 0 clock divider register */ 97 __IOM uint32_t CLKDIV_CS1; /*!< (@ 0x00000204) TAF chip select 1 clock divider register */ 98 __IOM uint32_t RPMC_OP2_HOST_RESULT; /*!< (@ 0x00000208) TAF RPMC OP2 eSPI Host result register */ 99 __IOM uint32_t RPMC_OP2_EC0_RESULT; /*!< (@ 0x0000020C) TAF RPMC OP2 EC0 result register */ 100 __IOM uint32_t RPMC_OP2_EC1_RESULT; /*!< (@ 0x00000210) TAF RPMC OP2 EC1 result register */ 101 } MEC_ESPI_TAF_Type; /*!< Size = 532 (0x214) */ 102 103 /** @} */ /* End of group Device_Peripheral_peripherals */ 104 105 /** @addtogroup PosMask_clusters 106 * @{ 107 */ 108 /* ================ PR ================ */ 109 /* ========================================================= WRBM ========================================================== */ 110 #define MEC_ESPI_TAF_PR_WRBM_CTL0_Pos (0UL) /*!< CTL0 (Bit 0) */ 111 #define MEC_ESPI_TAF_PR_WRBM_CTL0_Msk (0x1UL) /*!< CTL0 (Bitfield-Mask: 0x01) */ 112 #define MEC_ESPI_TAF_PR_WRBM_CTL1_Pos (1UL) /*!< CTL1 (Bit 1) */ 113 #define MEC_ESPI_TAF_PR_WRBM_CTL1_Msk (0x2UL) /*!< CTL1 (Bitfield-Mask: 0x01) */ 114 #define MEC_ESPI_TAF_PR_WRBM_CTL2_Pos (2UL) /*!< CTL2 (Bit 2) */ 115 #define MEC_ESPI_TAF_PR_WRBM_CTL2_Msk (0x4UL) /*!< CTL2 (Bitfield-Mask: 0x01) */ 116 #define MEC_ESPI_TAF_PR_WRBM_CTL3_Pos (3UL) /*!< CTL3 (Bit 3) */ 117 #define MEC_ESPI_TAF_PR_WRBM_CTL3_Msk (0x8UL) /*!< CTL3 (Bitfield-Mask: 0x01) */ 118 #define MEC_ESPI_TAF_PR_WRBM_CTL4_Pos (4UL) /*!< CTL4 (Bit 4) */ 119 #define MEC_ESPI_TAF_PR_WRBM_CTL4_Msk (0x10UL) /*!< CTL4 (Bitfield-Mask: 0x01) */ 120 #define MEC_ESPI_TAF_PR_WRBM_CTL5_Pos (5UL) /*!< CTL5 (Bit 5) */ 121 #define MEC_ESPI_TAF_PR_WRBM_CTL5_Msk (0x20UL) /*!< CTL5 (Bitfield-Mask: 0x01) */ 122 #define MEC_ESPI_TAF_PR_WRBM_CTL6_Pos (6UL) /*!< CTL6 (Bit 6) */ 123 #define MEC_ESPI_TAF_PR_WRBM_CTL6_Msk (0x40UL) /*!< CTL6 (Bitfield-Mask: 0x01) */ 124 #define MEC_ESPI_TAF_PR_WRBM_CTL7_Pos (7UL) /*!< CTL7 (Bit 7) */ 125 #define MEC_ESPI_TAF_PR_WRBM_CTL7_Msk (0x80UL) /*!< CTL7 (Bitfield-Mask: 0x01) */ 126 /* ========================================================= RDBM ========================================================== */ 127 #define MEC_ESPI_TAF_PR_RDBM_CTL0_Pos (0UL) /*!< CTL0 (Bit 0) */ 128 #define MEC_ESPI_TAF_PR_RDBM_CTL0_Msk (0x1UL) /*!< CTL0 (Bitfield-Mask: 0x01) */ 129 #define MEC_ESPI_TAF_PR_RDBM_CTL1_Pos (1UL) /*!< CTL1 (Bit 1) */ 130 #define MEC_ESPI_TAF_PR_RDBM_CTL1_Msk (0x2UL) /*!< CTL1 (Bitfield-Mask: 0x01) */ 131 #define MEC_ESPI_TAF_PR_RDBM_CTL2_Pos (2UL) /*!< CTL2 (Bit 2) */ 132 #define MEC_ESPI_TAF_PR_RDBM_CTL2_Msk (0x4UL) /*!< CTL2 (Bitfield-Mask: 0x01) */ 133 #define MEC_ESPI_TAF_PR_RDBM_CTL3_Pos (3UL) /*!< CTL3 (Bit 3) */ 134 #define MEC_ESPI_TAF_PR_RDBM_CTL3_Msk (0x8UL) /*!< CTL3 (Bitfield-Mask: 0x01) */ 135 #define MEC_ESPI_TAF_PR_RDBM_CTL4_Pos (4UL) /*!< CTL4 (Bit 4) */ 136 #define MEC_ESPI_TAF_PR_RDBM_CTL4_Msk (0x10UL) /*!< CTL4 (Bitfield-Mask: 0x01) */ 137 #define MEC_ESPI_TAF_PR_RDBM_CTL5_Pos (5UL) /*!< CTL5 (Bit 5) */ 138 #define MEC_ESPI_TAF_PR_RDBM_CTL5_Msk (0x20UL) /*!< CTL5 (Bitfield-Mask: 0x01) */ 139 #define MEC_ESPI_TAF_PR_RDBM_CTL6_Pos (6UL) /*!< CTL6 (Bit 6) */ 140 #define MEC_ESPI_TAF_PR_RDBM_CTL6_Msk (0x40UL) /*!< CTL6 (Bitfield-Mask: 0x01) */ 141 #define MEC_ESPI_TAF_PR_RDBM_CTL7_Pos (7UL) /*!< CTL7 (Bit 7) */ 142 #define MEC_ESPI_TAF_PR_RDBM_CTL7_Msk (0x80UL) /*!< CTL7 (Bitfield-Mask: 0x01) */ 143 144 /** @} */ /* End of group PosMask_clusters */ 145 146 /** @addtogroup PosMask_peripherals 147 * @{ 148 */ 149 /* ================ MEC_ESPI_TAF_COMM ================ */ 150 /* ======================================================= COMM_MODE ======================================================= */ 151 #define MEC_ESPI_TAF_COMM_COMM_MODE_PREFETCH_EN_Pos (0UL) /*!< PREFETCH_EN (Bit 0) */ 152 #define MEC_ESPI_TAF_COMM_COMM_MODE_PREFETCH_EN_Msk (0x1UL) /*!< PREFETCH_EN (Bitfield-Mask: 0x01) */ 153 154 /* ================ MEC_ESPI_TAF ================ */ 155 /* ======================================================== ECP_CMD ======================================================== */ 156 #define MEC_ESPI_TAF_ECP_CMD_EC_PUT_CMD_Pos (0UL) /*!< EC_PUT_CMD (Bit 0) */ 157 #define MEC_ESPI_TAF_ECP_CMD_EC_PUT_CMD_Msk (0xffUL) /*!< EC_PUT_CMD (Bitfield-Mask: 0xff) */ 158 #define MEC_ESPI_TAF_ECP_CMD_EC_CMD_Pos (8UL) /*!< EC_CMD (Bit 8) */ 159 #define MEC_ESPI_TAF_ECP_CMD_EC_CMD_Msk (0xff00UL) /*!< EC_CMD (Bitfield-Mask: 0xff) */ 160 #define MEC_ESPI_TAF_ECP_CMD_LEN_Pos (24UL) /*!< LEN (Bit 24) */ 161 #define MEC_ESPI_TAF_ECP_CMD_LEN_Msk (0xff000000UL) /*!< LEN (Bitfield-Mask: 0xff) */ 162 /* ======================================================= ECP_FADDR ======================================================= */ 163 /* ======================================================= ECP_START ======================================================= */ 164 #define MEC_ESPI_TAF_ECP_START_START_Pos (0UL) /*!< START (Bit 0) */ 165 #define MEC_ESPI_TAF_ECP_START_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ 166 /* ======================================================= ECP_BADDR ======================================================= */ 167 /* ======================================================== ECP_STS ======================================================== */ 168 #define MEC_ESPI_TAF_ECP_STS_DONE_Pos (0UL) /*!< DONE (Bit 0) */ 169 #define MEC_ESPI_TAF_ECP_STS_DONE_Msk (0x1UL) /*!< DONE (Bitfield-Mask: 0x01) */ 170 #define MEC_ESPI_TAF_ECP_STS_DONE_ACK_Pos (1UL) /*!< DONE_ACK (Bit 1) */ 171 #define MEC_ESPI_TAF_ECP_STS_DONE_ACK_Msk (0x2UL) /*!< DONE_ACK (Bitfield-Mask: 0x01) */ 172 #define MEC_ESPI_TAF_ECP_STS_TIMEOUT_Pos (2UL) /*!< TIMEOUT (Bit 2) */ 173 #define MEC_ESPI_TAF_ECP_STS_TIMEOUT_Msk (0x4UL) /*!< TIMEOUT (Bitfield-Mask: 0x01) */ 174 #define MEC_ESPI_TAF_ECP_STS_OOR_ERR_Pos (3UL) /*!< OOR_ERR (Bit 3) */ 175 #define MEC_ESPI_TAF_ECP_STS_OOR_ERR_Msk (0x8UL) /*!< OOR_ERR (Bitfield-Mask: 0x01) */ 176 #define MEC_ESPI_TAF_ECP_STS_ACCV_ERR_Pos (4UL) /*!< ACCV_ERR (Bit 4) */ 177 #define MEC_ESPI_TAF_ECP_STS_ACCV_ERR_Msk (0x10UL) /*!< ACCV_ERR (Bitfield-Mask: 0x01) */ 178 #define MEC_ESPI_TAF_ECP_STS_4KB_ERR_Pos (5UL) /*!< 4KB_ERR (Bit 5) */ 179 #define MEC_ESPI_TAF_ECP_STS_4KB_ERR_Msk (0x20UL) /*!< 4KB_ERR (Bitfield-Mask: 0x01) */ 180 #define MEC_ESPI_TAF_ECP_STS_ERSZ_ERR_Pos (6UL) /*!< ERSZ_ERR (Bit 6) */ 181 #define MEC_ESPI_TAF_ECP_STS_ERSZ_ERR_Msk (0x40UL) /*!< ERSZ_ERR (Bitfield-Mask: 0x01) */ 182 #define MEC_ESPI_TAF_ECP_STS_START_OVFL_ERR_Pos (7UL) /*!< START_OVFL_ERR (Bit 7) */ 183 #define MEC_ESPI_TAF_ECP_STS_START_OVFL_ERR_Msk (0x80UL) /*!< START_OVFL_ERR (Bitfield-Mask: 0x01) */ 184 #define MEC_ESPI_TAF_ECP_STS_BAD_REQ_ERR_Pos (8UL) /*!< BAD_REQ_ERR (Bit 8) */ 185 #define MEC_ESPI_TAF_ECP_STS_BAD_REQ_ERR_Msk (0x100UL) /*!< BAD_REQ_ERR (Bitfield-Mask: 0x01) */ 186 /* ======================================================== ECP_IEN ======================================================== */ 187 #define MEC_ESPI_TAF_ECP_IEN_DONE_Pos (0UL) /*!< DONE (Bit 0) */ 188 #define MEC_ESPI_TAF_ECP_IEN_DONE_Msk (0x1UL) /*!< DONE (Bitfield-Mask: 0x01) */ 189 /* ======================================================= FC_SZ_LIM ======================================================= */ 190 /* ======================================================== FC_THR ========================================================= */ 191 /* ======================================================== FC_MISC ======================================================== */ 192 #define MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE_Pos (0UL) /*!< PREFETCH_MODE (Bit 0) */ 193 #define MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE_Msk (0x3UL) /*!< PREFETCH_MODE (Bitfield-Mask: 0x03) */ 194 #define MEC_ESPI_TAF_FC_MISC_CS0_PRF_CANCEL_Pos (2UL) /*!< CS0_PRF_CANCEL (Bit 2) */ 195 #define MEC_ESPI_TAF_FC_MISC_CS0_PRF_CANCEL_Msk (0x4UL) /*!< CS0_PRF_CANCEL (Bitfield-Mask: 0x01) */ 196 #define MEC_ESPI_TAF_FC_MISC_CS1_PRF_CANCEL_Pos (3UL) /*!< CS1_PRF_CANCEL (Bit 3) */ 197 #define MEC_ESPI_TAF_FC_MISC_CS1_PRF_CANCEL_Msk (0x8UL) /*!< CS1_PRF_CANCEL (Bitfield-Mask: 0x01) */ 198 #define MEC_ESPI_TAF_FC_MISC_CS0_4B_ADDR_MODE_Pos (4UL) /*!< CS0_4B_ADDR_MODE (Bit 4) */ 199 #define MEC_ESPI_TAF_FC_MISC_CS0_4B_ADDR_MODE_Msk (0x10UL) /*!< CS0_4B_ADDR_MODE (Bitfield-Mask: 0x01) */ 200 #define MEC_ESPI_TAF_FC_MISC_CS1_4B_ADDR_MODE_Pos (5UL) /*!< CS1_4B_ADDR_MODE (Bit 5) */ 201 #define MEC_ESPI_TAF_FC_MISC_CS1_4B_ADDR_MODE_Msk (0x20UL) /*!< CS1_4B_ADDR_MODE (Bitfield-Mask: 0x01) */ 202 #define MEC_ESPI_TAF_FC_MISC_CS0_CONT_PREFIX_Pos (6UL) /*!< CS0_CONT_PREFIX (Bit 6) */ 203 #define MEC_ESPI_TAF_FC_MISC_CS0_CONT_PREFIX_Msk (0x40UL) /*!< CS0_CONT_PREFIX (Bitfield-Mask: 0x01) */ 204 #define MEC_ESPI_TAF_FC_MISC_CS1_CONT_PREFIX_Pos (7UL) /*!< CS1_CONT_PREFIX (Bit 7) */ 205 #define MEC_ESPI_TAF_FC_MISC_CS1_CONT_PREFIX_Msk (0x80UL) /*!< CS1_CONT_PREFIX (Bitfield-Mask: 0x01) */ 206 #define MEC_ESPI_TAF_FC_MISC_TAF_EN_Pos (12UL) /*!< TAF_EN (Bit 12) */ 207 #define MEC_ESPI_TAF_FC_MISC_TAF_EN_Msk (0x1000UL) /*!< TAF_EN (Bitfield-Mask: 0x01) */ 208 #define MEC_ESPI_TAF_FC_MISC_TAF_LOCK_Pos (13UL) /*!< TAF_LOCK (Bit 13) */ 209 #define MEC_ESPI_TAF_FC_MISC_TAF_LOCK_Msk (0x2000UL) /*!< TAF_LOCK (Bitfield-Mask: 0x01) */ 210 #define MEC_ESPI_TAF_FC_MISC_LPF_LSLP_Pos (16UL) /*!< LPF_LSLP (Bit 16) */ 211 #define MEC_ESPI_TAF_FC_MISC_LPF_LSLP_Msk (0x10000UL) /*!< LPF_LSLP (Bitfield-Mask: 0x01) */ 212 #define MEC_ESPI_TAF_FC_MISC_LPF_HSLP_Pos (17UL) /*!< LPF_HSLP (Bit 17) */ 213 #define MEC_ESPI_TAF_FC_MISC_LPF_HSLP_Msk (0x20000UL) /*!< LPF_HSLP (Bitfield-Mask: 0x01) */ 214 #define MEC_ESPI_TAF_FC_MISC_LPF_SAC_Pos (18UL) /*!< LPF_SAC (Bit 18) */ 215 #define MEC_ESPI_TAF_FC_MISC_LPF_SAC_Msk (0x40000UL) /*!< LPF_SAC (Bitfield-Mask: 0x01) */ 216 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_ESPI_Pos (20UL) /*!< RLD_SAC_ESPI (Bit 20) */ 217 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_ESPI_Msk (0x100000UL) /*!< RLD_SAC_ESPI (Bitfield-Mask: 0x01) */ 218 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_EC0_Pos (21UL) /*!< RLD_SAC_EC0 (Bit 21) */ 219 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_EC0_Msk (0x200000UL) /*!< RLD_SAC_EC0 (Bitfield-Mask: 0x01) */ 220 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_EC1_Pos (22UL) /*!< RLD_SAC_EC1 (Bit 22) */ 221 #define MEC_ESPI_TAF_FC_MISC_RLD_SAC_EC1_Msk (0x400000UL) /*!< RLD_SAC_EC1 (Bitfield-Mask: 0x01) */ 222 #define MEC_ESPI_TAF_FC_MISC_FORCE_RPMC_SUCC_Pos (24UL) /*!< FORCE_RPMC_SUCC (Bit 24) */ 223 #define MEC_ESPI_TAF_FC_MISC_FORCE_RPMC_SUCC_Msk (0x1000000UL) /*!< FORCE_RPMC_SUCC (Bitfield-Mask: 0x01) */ 224 /* ======================================================== MON_STS ======================================================== */ 225 #define MEC_ESPI_TAF_MON_STS_TMOUT_ERR_Pos (0UL) /*!< TMOUT_ERR (Bit 0) */ 226 #define MEC_ESPI_TAF_MON_STS_TMOUT_ERR_Msk (0x1UL) /*!< TMOUT_ERR (Bitfield-Mask: 0x01) */ 227 #define MEC_ESPI_TAF_MON_STS_OOR_ERR_Pos (1UL) /*!< OOR_ERR (Bit 1) */ 228 #define MEC_ESPI_TAF_MON_STS_OOR_ERR_Msk (0x2UL) /*!< OOR_ERR (Bitfield-Mask: 0x01) */ 229 #define MEC_ESPI_TAF_MON_STS_ACCV_ERR_Pos (2UL) /*!< ACCV_ERR (Bit 2) */ 230 #define MEC_ESPI_TAF_MON_STS_ACCV_ERR_Msk (0x4UL) /*!< ACCV_ERR (Bitfield-Mask: 0x01) */ 231 #define MEC_ESPI_TAF_MON_STS_4KB_ERR_Pos (3UL) /*!< 4KB_ERR (Bit 3) */ 232 #define MEC_ESPI_TAF_MON_STS_4KB_ERR_Msk (0x8UL) /*!< 4KB_ERR (Bitfield-Mask: 0x01) */ 233 #define MEC_ESPI_TAF_MON_STS_ERSZ_ERR_Pos (4UL) /*!< ERSZ_ERR (Bit 4) */ 234 #define MEC_ESPI_TAF_MON_STS_ERSZ_ERR_Msk (0x10UL) /*!< ERSZ_ERR (Bitfield-Mask: 0x01) */ 235 /* ======================================================== MON_IEN ======================================================== */ 236 #define MEC_ESPI_TAF_MON_IEN_TMOUT_ERR_Pos (0UL) /*!< TMOUT_ERR (Bit 0) */ 237 #define MEC_ESPI_TAF_MON_IEN_TMOUT_ERR_Msk (0x1UL) /*!< TMOUT_ERR (Bitfield-Mask: 0x01) */ 238 #define MEC_ESPI_TAF_MON_IEN_OOR_ERR_Pos (1UL) /*!< OOR_ERR (Bit 1) */ 239 #define MEC_ESPI_TAF_MON_IEN_OOR_ERR_Msk (0x2UL) /*!< OOR_ERR (Bitfield-Mask: 0x01) */ 240 #define MEC_ESPI_TAF_MON_IEN_ACCV_ERR_Pos (2UL) /*!< ACCV_ERR (Bit 2) */ 241 #define MEC_ESPI_TAF_MON_IEN_ACCV_ERR_Msk (0x4UL) /*!< ACCV_ERR (Bitfield-Mask: 0x01) */ 242 #define MEC_ESPI_TAF_MON_IEN_4KB_ERR_Pos (3UL) /*!< 4KB_ERR (Bit 3) */ 243 #define MEC_ESPI_TAF_MON_IEN_4KB_ERR_Msk (0x8UL) /*!< 4KB_ERR (Bitfield-Mask: 0x01) */ 244 #define MEC_ESPI_TAF_MON_IEN_ERSZ_ERR_Pos (4UL) /*!< ERSZ_ERR (Bit 4) */ 245 #define MEC_ESPI_TAF_MON_IEN_ERSZ_ERR_Msk (0x10UL) /*!< ERSZ_ERR (Bitfield-Mask: 0x01) */ 246 /* ===================================================== ECP_BUSY_STS ====================================================== */ 247 #define MEC_ESPI_TAF_ECP_BUSY_STS_EC0_Pos (0UL) /*!< EC0 (Bit 0) */ 248 #define MEC_ESPI_TAF_ECP_BUSY_STS_EC0_Msk (0x1UL) /*!< EC0 (Bitfield-Mask: 0x01) */ 249 #define MEC_ESPI_TAF_ECP_BUSY_STS_EC1_Pos (1UL) /*!< EC1 (Bit 1) */ 250 #define MEC_ESPI_TAF_ECP_BUSY_STS_EC1_Msk (0x2UL) /*!< EC1 (Bitfield-Mask: 0x01) */ 251 /* ======================================================== CS0_OPA ======================================================== */ 252 #define MEC_ESPI_TAF_CS0_OPA_OP_WE_Pos (0UL) /*!< OP_WE (Bit 0) */ 253 #define MEC_ESPI_TAF_CS0_OPA_OP_WE_Msk (0xffUL) /*!< OP_WE (Bitfield-Mask: 0xff) */ 254 #define MEC_ESPI_TAF_CS0_OPA_OP_SUS_Pos (8UL) /*!< OP_SUS (Bit 8) */ 255 #define MEC_ESPI_TAF_CS0_OPA_OP_SUS_Msk (0xff00UL) /*!< OP_SUS (Bitfield-Mask: 0xff) */ 256 #define MEC_ESPI_TAF_CS0_OPA_OP_RSM_Pos (16UL) /*!< OP_RSM (Bit 16) */ 257 #define MEC_ESPI_TAF_CS0_OPA_OP_RSM_Msk (0xff0000UL) /*!< OP_RSM (Bitfield-Mask: 0xff) */ 258 #define MEC_ESPI_TAF_CS0_OPA_OP_POLL1_Pos (24UL) /*!< OP_POLL1 (Bit 24) */ 259 #define MEC_ESPI_TAF_CS0_OPA_OP_POLL1_Msk (0xff000000UL) /*!< OP_POLL1 (Bitfield-Mask: 0xff) */ 260 /* ======================================================== CS0_OPB ======================================================== */ 261 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE0_Pos (0UL) /*!< OP_ERASE0 (Bit 0) */ 262 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE0_Msk (0xffUL) /*!< OP_ERASE0 (Bitfield-Mask: 0xff) */ 263 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE1_Pos (8UL) /*!< OP_ERASE1 (Bit 8) */ 264 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE1_Msk (0xff00UL) /*!< OP_ERASE1 (Bitfield-Mask: 0xff) */ 265 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE2_Pos (16UL) /*!< OP_ERASE2 (Bit 16) */ 266 #define MEC_ESPI_TAF_CS0_OPB_OP_ERASE2_Msk (0xff0000UL) /*!< OP_ERASE2 (Bitfield-Mask: 0xff) */ 267 #define MEC_ESPI_TAF_CS0_OPB_OP_PROG_Pos (24UL) /*!< OP_PROG (Bit 24) */ 268 #define MEC_ESPI_TAF_CS0_OPB_OP_PROG_Msk (0xff000000UL) /*!< OP_PROG (Bitfield-Mask: 0xff) */ 269 /* ======================================================== CS0_OPC ======================================================== */ 270 #define MEC_ESPI_TAF_CS0_OPC_OP_READ_Pos (0UL) /*!< OP_READ (Bit 0) */ 271 #define MEC_ESPI_TAF_CS0_OPC_OP_READ_Msk (0xffUL) /*!< OP_READ (Bitfield-Mask: 0xff) */ 272 #define MEC_ESPI_TAF_CS0_OPC_MODE_NONC_Pos (8UL) /*!< MODE_NONC (Bit 8) */ 273 #define MEC_ESPI_TAF_CS0_OPC_MODE_NONC_Msk (0xff00UL) /*!< MODE_NONC (Bitfield-Mask: 0xff) */ 274 #define MEC_ESPI_TAF_CS0_OPC_MODE_CONT_Pos (16UL) /*!< MODE_CONT (Bit 16) */ 275 #define MEC_ESPI_TAF_CS0_OPC_MODE_CONT_Msk (0xff0000UL) /*!< MODE_CONT (Bitfield-Mask: 0xff) */ 276 #define MEC_ESPI_TAF_CS0_OPC_OP_POLL2_Pos (24UL) /*!< OP_POLL2 (Bit 24) */ 277 #define MEC_ESPI_TAF_CS0_OPC_OP_POLL2_Msk (0xff000000UL) /*!< OP_POLL2 (Bitfield-Mask: 0xff) */ 278 /* ===================================================== CS0_OP_DESCR ====================================================== */ 279 #define MEC_ESPI_TAF_CS0_OP_DESCR_ENTER_CONT_Pos (0UL) /*!< ENTER_CONT (Bit 0) */ 280 #define MEC_ESPI_TAF_CS0_OP_DESCR_ENTER_CONT_Msk (0xfUL) /*!< ENTER_CONT (Bitfield-Mask: 0x0f) */ 281 #define MEC_ESPI_TAF_CS0_OP_DESCR_READ_CONT_Pos (8UL) /*!< READ_CONT (Bit 8) */ 282 #define MEC_ESPI_TAF_CS0_OP_DESCR_READ_CONT_Msk (0xf00UL) /*!< READ_CONT (Bitfield-Mask: 0x0f) */ 283 #define MEC_ESPI_TAF_CS0_OP_DESCR_SIZE_CONT_Pos (12UL) /*!< SIZE_CONT (Bit 12) */ 284 #define MEC_ESPI_TAF_CS0_OP_DESCR_SIZE_CONT_Msk (0xf000UL) /*!< SIZE_CONT (Bitfield-Mask: 0x0f) */ 285 /* ======================================================== CS1_OPA ======================================================== */ 286 #define MEC_ESPI_TAF_CS1_OPA_OP_WE_Pos (0UL) /*!< OP_WE (Bit 0) */ 287 #define MEC_ESPI_TAF_CS1_OPA_OP_WE_Msk (0xffUL) /*!< OP_WE (Bitfield-Mask: 0xff) */ 288 #define MEC_ESPI_TAF_CS1_OPA_OP_SUS_Pos (8UL) /*!< OP_SUS (Bit 8) */ 289 #define MEC_ESPI_TAF_CS1_OPA_OP_SUS_Msk (0xff00UL) /*!< OP_SUS (Bitfield-Mask: 0xff) */ 290 #define MEC_ESPI_TAF_CS1_OPA_OP_RSM_Pos (16UL) /*!< OP_RSM (Bit 16) */ 291 #define MEC_ESPI_TAF_CS1_OPA_OP_RSM_Msk (0xff0000UL) /*!< OP_RSM (Bitfield-Mask: 0xff) */ 292 #define MEC_ESPI_TAF_CS1_OPA_OP_POLL1_Pos (24UL) /*!< OP_POLL1 (Bit 24) */ 293 #define MEC_ESPI_TAF_CS1_OPA_OP_POLL1_Msk (0xff000000UL) /*!< OP_POLL1 (Bitfield-Mask: 0xff) */ 294 /* ======================================================== CS1_OPB ======================================================== */ 295 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE0_Pos (0UL) /*!< OP_ERASE0 (Bit 0) */ 296 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE0_Msk (0xffUL) /*!< OP_ERASE0 (Bitfield-Mask: 0xff) */ 297 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE1_Pos (8UL) /*!< OP_ERASE1 (Bit 8) */ 298 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE1_Msk (0xff00UL) /*!< OP_ERASE1 (Bitfield-Mask: 0xff) */ 299 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE2_Pos (16UL) /*!< OP_ERASE2 (Bit 16) */ 300 #define MEC_ESPI_TAF_CS1_OPB_OP_ERASE2_Msk (0xff0000UL) /*!< OP_ERASE2 (Bitfield-Mask: 0xff) */ 301 #define MEC_ESPI_TAF_CS1_OPB_OP_PROG_Pos (24UL) /*!< OP_PROG (Bit 24) */ 302 #define MEC_ESPI_TAF_CS1_OPB_OP_PROG_Msk (0xff000000UL) /*!< OP_PROG (Bitfield-Mask: 0xff) */ 303 /* ======================================================== CS1_OPC ======================================================== */ 304 #define MEC_ESPI_TAF_CS1_OPC_OP_READ_Pos (0UL) /*!< OP_READ (Bit 0) */ 305 #define MEC_ESPI_TAF_CS1_OPC_OP_READ_Msk (0xffUL) /*!< OP_READ (Bitfield-Mask: 0xff) */ 306 #define MEC_ESPI_TAF_CS1_OPC_MODE_NONC_Pos (8UL) /*!< MODE_NONC (Bit 8) */ 307 #define MEC_ESPI_TAF_CS1_OPC_MODE_NONC_Msk (0xff00UL) /*!< MODE_NONC (Bitfield-Mask: 0xff) */ 308 #define MEC_ESPI_TAF_CS1_OPC_MODE_CONT_Pos (16UL) /*!< MODE_CONT (Bit 16) */ 309 #define MEC_ESPI_TAF_CS1_OPC_MODE_CONT_Msk (0xff0000UL) /*!< MODE_CONT (Bitfield-Mask: 0xff) */ 310 #define MEC_ESPI_TAF_CS1_OPC_OP_POLL2_Pos (24UL) /*!< OP_POLL2 (Bit 24) */ 311 #define MEC_ESPI_TAF_CS1_OPC_OP_POLL2_Msk (0xff000000UL) /*!< OP_POLL2 (Bitfield-Mask: 0xff) */ 312 /* ===================================================== CS1_OP_DESCR ====================================================== */ 313 #define MEC_ESPI_TAF_CS1_OP_DESCR_ENTER_CONT_Pos (0UL) /*!< ENTER_CONT (Bit 0) */ 314 #define MEC_ESPI_TAF_CS1_OP_DESCR_ENTER_CONT_Msk (0xfUL) /*!< ENTER_CONT (Bitfield-Mask: 0x0f) */ 315 #define MEC_ESPI_TAF_CS1_OP_DESCR_READ_CONT_Pos (8UL) /*!< READ_CONT (Bit 8) */ 316 #define MEC_ESPI_TAF_CS1_OP_DESCR_READ_CONT_Msk (0xf00UL) /*!< READ_CONT (Bitfield-Mask: 0x0f) */ 317 #define MEC_ESPI_TAF_CS1_OP_DESCR_SIZE_CONT_Pos (12UL) /*!< SIZE_CONT (Bit 12) */ 318 #define MEC_ESPI_TAF_CS1_OP_DESCR_SIZE_CONT_Msk (0xf000UL) /*!< SIZE_CONT (Bitfield-Mask: 0x0f) */ 319 /* ======================================================= GEN_DESCR ======================================================= */ 320 #define MEC_ESPI_TAF_GEN_DESCR_EXIT_CONT_Pos (0UL) /*!< EXIT_CONT (Bit 0) */ 321 #define MEC_ESPI_TAF_GEN_DESCR_EXIT_CONT_Msk (0xfUL) /*!< EXIT_CONT (Bitfield-Mask: 0x0f) */ 322 #define MEC_ESPI_TAF_GEN_DESCR_POLL1_Pos (8UL) /*!< POLL1 (Bit 8) */ 323 #define MEC_ESPI_TAF_GEN_DESCR_POLL1_Msk (0xf00UL) /*!< POLL1 (Bitfield-Mask: 0x0f) */ 324 #define MEC_ESPI_TAF_GEN_DESCR_POLL2_Pos (12UL) /*!< POLL2 (Bit 12) */ 325 #define MEC_ESPI_TAF_GEN_DESCR_POLL2_Msk (0xf000UL) /*!< POLL2 (Bitfield-Mask: 0x0f) */ 326 /* ======================================================== PR_LOCK ======================================================== */ 327 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG0_Pos (0UL) /*!< PROT_REG0 (Bit 0) */ 328 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG0_Msk (0x1UL) /*!< PROT_REG0 (Bitfield-Mask: 0x01) */ 329 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG1_Pos (1UL) /*!< PROT_REG1 (Bit 1) */ 330 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG1_Msk (0x2UL) /*!< PROT_REG1 (Bitfield-Mask: 0x01) */ 331 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG2_Pos (2UL) /*!< PROT_REG2 (Bit 2) */ 332 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG2_Msk (0x4UL) /*!< PROT_REG2 (Bitfield-Mask: 0x01) */ 333 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG3_Pos (3UL) /*!< PROT_REG3 (Bit 3) */ 334 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG3_Msk (0x8UL) /*!< PROT_REG3 (Bitfield-Mask: 0x01) */ 335 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG4_Pos (4UL) /*!< PROT_REG4 (Bit 4) */ 336 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG4_Msk (0x10UL) /*!< PROT_REG4 (Bitfield-Mask: 0x01) */ 337 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG5_Pos (5UL) /*!< PROT_REG5 (Bit 5) */ 338 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG5_Msk (0x20UL) /*!< PROT_REG5 (Bitfield-Mask: 0x01) */ 339 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG6_Pos (6UL) /*!< PROT_REG6 (Bit 6) */ 340 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG6_Msk (0x40UL) /*!< PROT_REG6 (Bitfield-Mask: 0x01) */ 341 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG7_Pos (7UL) /*!< PROT_REG7 (Bit 7) */ 342 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG7_Msk (0x80UL) /*!< PROT_REG7 (Bitfield-Mask: 0x01) */ 343 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG8_Pos (8UL) /*!< PROT_REG8 (Bit 8) */ 344 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG8_Msk (0x100UL) /*!< PROT_REG8 (Bitfield-Mask: 0x01) */ 345 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG9_Pos (9UL) /*!< PROT_REG9 (Bit 9) */ 346 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG9_Msk (0x200UL) /*!< PROT_REG9 (Bitfield-Mask: 0x01) */ 347 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG10_Pos (10UL) /*!< PROT_REG10 (Bit 10) */ 348 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG10_Msk (0x400UL) /*!< PROT_REG10 (Bitfield-Mask: 0x01) */ 349 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG11_Pos (11UL) /*!< PROT_REG11 (Bit 11) */ 350 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG11_Msk (0x800UL) /*!< PROT_REG11 (Bitfield-Mask: 0x01) */ 351 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG12_Pos (12UL) /*!< PROT_REG12 (Bit 12) */ 352 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG12_Msk (0x1000UL) /*!< PROT_REG12 (Bitfield-Mask: 0x01) */ 353 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG13_Pos (13UL) /*!< PROT_REG13 (Bit 13) */ 354 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG13_Msk (0x2000UL) /*!< PROT_REG13 (Bitfield-Mask: 0x01) */ 355 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG14_Pos (14UL) /*!< PROT_REG14 (Bit 14) */ 356 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG14_Msk (0x4000UL) /*!< PROT_REG14 (Bitfield-Mask: 0x01) */ 357 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG15_Pos (15UL) /*!< PROT_REG15 (Bit 15) */ 358 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG15_Msk (0x8000UL) /*!< PROT_REG15 (Bitfield-Mask: 0x01) */ 359 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG16_Pos (16UL) /*!< PROT_REG16 (Bit 16) */ 360 #define MEC_ESPI_TAF_PR_LOCK_PROT_REG16_Msk (0x10000UL) /*!< PROT_REG16 (Bitfield-Mask: 0x01) */ 361 /* ======================================================= PR_DIRTY ======================================================== */ 362 #define MEC_ESPI_TAF_PR_DIRTY_PR0_Pos (0UL) /*!< PR0 (Bit 0) */ 363 #define MEC_ESPI_TAF_PR_DIRTY_PR0_Msk (0x1UL) /*!< PR0 (Bitfield-Mask: 0x01) */ 364 #define MEC_ESPI_TAF_PR_DIRTY_PR1_Pos (1UL) /*!< PR1 (Bit 1) */ 365 #define MEC_ESPI_TAF_PR_DIRTY_PR1_Msk (0x2UL) /*!< PR1 (Bitfield-Mask: 0x01) */ 366 #define MEC_ESPI_TAF_PR_DIRTY_PR2_Pos (2UL) /*!< PR2 (Bit 2) */ 367 #define MEC_ESPI_TAF_PR_DIRTY_PR2_Msk (0x4UL) /*!< PR2 (Bitfield-Mask: 0x01) */ 368 #define MEC_ESPI_TAF_PR_DIRTY_PR3_Pos (3UL) /*!< PR3 (Bit 3) */ 369 #define MEC_ESPI_TAF_PR_DIRTY_PR3_Msk (0x8UL) /*!< PR3 (Bitfield-Mask: 0x01) */ 370 #define MEC_ESPI_TAF_PR_DIRTY_PR4_Pos (4UL) /*!< PR4 (Bit 4) */ 371 #define MEC_ESPI_TAF_PR_DIRTY_PR4_Msk (0x10UL) /*!< PR4 (Bitfield-Mask: 0x01) */ 372 #define MEC_ESPI_TAF_PR_DIRTY_PR5_Pos (5UL) /*!< PR5 (Bit 5) */ 373 #define MEC_ESPI_TAF_PR_DIRTY_PR5_Msk (0x20UL) /*!< PR5 (Bitfield-Mask: 0x01) */ 374 #define MEC_ESPI_TAF_PR_DIRTY_PR6_Pos (6UL) /*!< PR6 (Bit 6) */ 375 #define MEC_ESPI_TAF_PR_DIRTY_PR6_Msk (0x40UL) /*!< PR6 (Bitfield-Mask: 0x01) */ 376 #define MEC_ESPI_TAF_PR_DIRTY_PR7_Pos (7UL) /*!< PR7 (Bit 7) */ 377 #define MEC_ESPI_TAF_PR_DIRTY_PR7_Msk (0x80UL) /*!< PR7 (Bitfield-Mask: 0x01) */ 378 #define MEC_ESPI_TAF_PR_DIRTY_PR8_Pos (8UL) /*!< PR8 (Bit 8) */ 379 #define MEC_ESPI_TAF_PR_DIRTY_PR8_Msk (0x100UL) /*!< PR8 (Bitfield-Mask: 0x01) */ 380 #define MEC_ESPI_TAF_PR_DIRTY_PR9_Pos (9UL) /*!< PR9 (Bit 9) */ 381 #define MEC_ESPI_TAF_PR_DIRTY_PR9_Msk (0x200UL) /*!< PR9 (Bitfield-Mask: 0x01) */ 382 #define MEC_ESPI_TAF_PR_DIRTY_PR10_Pos (10UL) /*!< PR10 (Bit 10) */ 383 #define MEC_ESPI_TAF_PR_DIRTY_PR10_Msk (0x400UL) /*!< PR10 (Bitfield-Mask: 0x01) */ 384 #define MEC_ESPI_TAF_PR_DIRTY_PR11_Pos (11UL) /*!< PR11 (Bit 11) */ 385 #define MEC_ESPI_TAF_PR_DIRTY_PR11_Msk (0x800UL) /*!< PR11 (Bitfield-Mask: 0x01) */ 386 /* ======================================================= TAG_MAP0 ======================================================== */ 387 #define MEC_ESPI_TAF_TAG_MAP0_STM0_Pos (0UL) /*!< STM0 (Bit 0) */ 388 #define MEC_ESPI_TAF_TAG_MAP0_STM0_Msk (0x7UL) /*!< STM0 (Bitfield-Mask: 0x07) */ 389 #define MEC_ESPI_TAF_TAG_MAP0_STM1_Pos (4UL) /*!< STM1 (Bit 4) */ 390 #define MEC_ESPI_TAF_TAG_MAP0_STM1_Msk (0x70UL) /*!< STM1 (Bitfield-Mask: 0x07) */ 391 #define MEC_ESPI_TAF_TAG_MAP0_STM2_Pos (8UL) /*!< STM2 (Bit 8) */ 392 #define MEC_ESPI_TAF_TAG_MAP0_STM2_Msk (0x700UL) /*!< STM2 (Bitfield-Mask: 0x07) */ 393 #define MEC_ESPI_TAF_TAG_MAP0_STM3_Pos (12UL) /*!< STM3 (Bit 12) */ 394 #define MEC_ESPI_TAF_TAG_MAP0_STM3_Msk (0x7000UL) /*!< STM3 (Bitfield-Mask: 0x07) */ 395 #define MEC_ESPI_TAF_TAG_MAP0_STM4_Pos (16UL) /*!< STM4 (Bit 16) */ 396 #define MEC_ESPI_TAF_TAG_MAP0_STM4_Msk (0x70000UL) /*!< STM4 (Bitfield-Mask: 0x07) */ 397 #define MEC_ESPI_TAF_TAG_MAP0_STM5_Pos (20UL) /*!< STM5 (Bit 20) */ 398 #define MEC_ESPI_TAF_TAG_MAP0_STM5_Msk (0x700000UL) /*!< STM5 (Bitfield-Mask: 0x07) */ 399 #define MEC_ESPI_TAF_TAG_MAP0_STM6_Pos (24UL) /*!< STM6 (Bit 24) */ 400 #define MEC_ESPI_TAF_TAG_MAP0_STM6_Msk (0x7000000UL) /*!< STM6 (Bitfield-Mask: 0x07) */ 401 #define MEC_ESPI_TAF_TAG_MAP0_STM7_Pos (28UL) /*!< STM7 (Bit 28) */ 402 #define MEC_ESPI_TAF_TAG_MAP0_STM7_Msk (0x70000000UL) /*!< STM7 (Bitfield-Mask: 0x07) */ 403 /* ======================================================= TAG_MAP1 ======================================================== */ 404 #define MEC_ESPI_TAF_TAG_MAP1_STM8_Pos (0UL) /*!< STM8 (Bit 0) */ 405 #define MEC_ESPI_TAF_TAG_MAP1_STM8_Msk (0x7UL) /*!< STM8 (Bitfield-Mask: 0x07) */ 406 #define MEC_ESPI_TAF_TAG_MAP1_STM9_Pos (4UL) /*!< STM9 (Bit 4) */ 407 #define MEC_ESPI_TAF_TAG_MAP1_STM9_Msk (0x70UL) /*!< STM9 (Bitfield-Mask: 0x07) */ 408 #define MEC_ESPI_TAF_TAG_MAP1_STM10_Pos (8UL) /*!< STM10 (Bit 8) */ 409 #define MEC_ESPI_TAF_TAG_MAP1_STM10_Msk (0x700UL) /*!< STM10 (Bitfield-Mask: 0x07) */ 410 #define MEC_ESPI_TAF_TAG_MAP1_STM11_Pos (12UL) /*!< STM11 (Bit 12) */ 411 #define MEC_ESPI_TAF_TAG_MAP1_STM11_Msk (0x7000UL) /*!< STM11 (Bitfield-Mask: 0x07) */ 412 #define MEC_ESPI_TAF_TAG_MAP1_STM12_Pos (16UL) /*!< STM12 (Bit 16) */ 413 #define MEC_ESPI_TAF_TAG_MAP1_STM12_Msk (0x70000UL) /*!< STM12 (Bitfield-Mask: 0x07) */ 414 #define MEC_ESPI_TAF_TAG_MAP1_STM13_Pos (20UL) /*!< STM13 (Bit 20) */ 415 #define MEC_ESPI_TAF_TAG_MAP1_STM13_Msk (0x700000UL) /*!< STM13 (Bitfield-Mask: 0x07) */ 416 #define MEC_ESPI_TAF_TAG_MAP1_STM14_Pos (24UL) /*!< STM14 (Bit 24) */ 417 #define MEC_ESPI_TAF_TAG_MAP1_STM14_Msk (0x7000000UL) /*!< STM14 (Bitfield-Mask: 0x07) */ 418 #define MEC_ESPI_TAF_TAG_MAP1_STM15_Pos (28UL) /*!< STM15 (Bit 28) */ 419 #define MEC_ESPI_TAF_TAG_MAP1_STM15_Msk (0x70000000UL) /*!< STM15 (Bitfield-Mask: 0x07) */ 420 /* ======================================================= TAG_MAP2 ======================================================== */ 421 #define MEC_ESPI_TAF_TAG_MAP2_STM_EC_Pos (0UL) /*!< STM_EC (Bit 0) */ 422 #define MEC_ESPI_TAF_TAG_MAP2_STM_EC_Msk (0x7UL) /*!< STM_EC (Bitfield-Mask: 0x07) */ 423 #define MEC_ESPI_TAF_TAG_MAP2_LOCK_Pos (31UL) /*!< LOCK (Bit 31) */ 424 #define MEC_ESPI_TAF_TAG_MAP2_LOCK_Msk (0x80000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ 425 /* ===================================================== POLL_TIMEOUT ====================================================== */ 426 #define MEC_ESPI_TAF_POLL_TIMEOUT_VAL_Pos (0UL) /*!< VAL (Bit 0) */ 427 #define MEC_ESPI_TAF_POLL_TIMEOUT_VAL_Msk (0x3ffffUL) /*!< VAL (Bitfield-Mask: 0x3ffff) */ 428 /* ===================================================== POLL_INTERVAL ===================================================== */ 429 /* ====================================================== SR_INTERVAL ====================================================== */ 430 /* ====================================================== CRD_TIMEOUT ====================================================== */ 431 /* ====================================================== POLL2_MSKS ======================================================= */ 432 #define MEC_ESPI_TAF_POLL2_MSKS_CS0_Pos (0UL) /*!< CS0 (Bit 0) */ 433 #define MEC_ESPI_TAF_POLL2_MSKS_CS0_Msk (0xffffUL) /*!< CS0 (Bitfield-Mask: 0xffff) */ 434 #define MEC_ESPI_TAF_POLL2_MSKS_CS1_Pos (16UL) /*!< CS1 (Bit 16) */ 435 #define MEC_ESPI_TAF_POLL2_MSKS_CS1_Msk (0xffff0000UL) /*!< CS1 (Bitfield-Mask: 0xffff) */ 436 /* ======================================================= FC_SMODE ======================================================== */ 437 #define MEC_ESPI_TAF_FC_SMODE_CS0_DSER_Pos (0UL) /*!< CS0_DSER (Bit 0) */ 438 #define MEC_ESPI_TAF_FC_SMODE_CS0_DSER_Msk (0x1UL) /*!< CS0_DSER (Bitfield-Mask: 0x01) */ 439 #define MEC_ESPI_TAF_FC_SMODE_CS1_DSER_Pos (1UL) /*!< CS1_DSER (Bit 1) */ 440 #define MEC_ESPI_TAF_FC_SMODE_CS1_DSER_Msk (0x2UL) /*!< CS1_DSER (Bitfield-Mask: 0x01) */ 441 #define MEC_ESPI_TAF_FC_SMODE_CS0_DSWR_Pos (2UL) /*!< CS0_DSWR (Bit 2) */ 442 #define MEC_ESPI_TAF_FC_SMODE_CS0_DSWR_Msk (0x4UL) /*!< CS0_DSWR (Bitfield-Mask: 0x01) */ 443 #define MEC_ESPI_TAF_FC_SMODE_CS1_DSWR_Pos (3UL) /*!< CS1_DSWR (Bit 3) */ 444 #define MEC_ESPI_TAF_FC_SMODE_CS1_DSWR_Msk (0x8UL) /*!< CS1_DSWR (Bitfield-Mask: 0x01) */ 445 /* ====================================================== SUS_CHK_DLY ====================================================== */ 446 /* ===================================================== FC_CM_PREFIX ====================================================== */ 447 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS0_OP_Pos (0UL) /*!< CS0_OP (Bit 0) */ 448 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS0_OP_Msk (0xffUL) /*!< CS0_OP (Bitfield-Mask: 0xff) */ 449 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS0_DAT_Pos (8UL) /*!< CS0_DAT (Bit 8) */ 450 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS0_DAT_Msk (0xff00UL) /*!< CS0_DAT (Bitfield-Mask: 0xff) */ 451 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS1_OP_Pos (16UL) /*!< CS1_OP (Bit 16) */ 452 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS1_OP_Msk (0xff0000UL) /*!< CS1_OP (Bitfield-Mask: 0xff) */ 453 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS1_DAT_Pos (24UL) /*!< CS1_DAT (Bit 24) */ 454 #define MEC_ESPI_TAF_FC_CM_PREFIX_CS1_DAT_Msk (0xff000000UL) /*!< CS1_DAT (Bitfield-Mask: 0xff) */ 455 /* ====================================================== DNX_PR_BYP ======================================================= */ 456 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG0_Pos (0UL) /*!< TAG0 (Bit 0) */ 457 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG0_Msk (0x1UL) /*!< TAG0 (Bitfield-Mask: 0x01) */ 458 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG1_Pos (1UL) /*!< TAG1 (Bit 1) */ 459 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG1_Msk (0x2UL) /*!< TAG1 (Bitfield-Mask: 0x01) */ 460 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG2_Pos (2UL) /*!< TAG2 (Bit 2) */ 461 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG2_Msk (0x4UL) /*!< TAG2 (Bitfield-Mask: 0x01) */ 462 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG3_Pos (3UL) /*!< TAG3 (Bit 3) */ 463 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG3_Msk (0x8UL) /*!< TAG3 (Bitfield-Mask: 0x01) */ 464 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG4_Pos (4UL) /*!< TAG4 (Bit 4) */ 465 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG4_Msk (0x10UL) /*!< TAG4 (Bitfield-Mask: 0x01) */ 466 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG5_Pos (5UL) /*!< TAG5 (Bit 5) */ 467 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG5_Msk (0x20UL) /*!< TAG5 (Bitfield-Mask: 0x01) */ 468 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG6_Pos (6UL) /*!< TAG6 (Bit 6) */ 469 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG6_Msk (0x40UL) /*!< TAG6 (Bitfield-Mask: 0x01) */ 470 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG7_Pos (7UL) /*!< TAG7 (Bit 7) */ 471 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG7_Msk (0x80UL) /*!< TAG7 (Bitfield-Mask: 0x01) */ 472 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG8_Pos (8UL) /*!< TAG8 (Bit 8) */ 473 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG8_Msk (0x100UL) /*!< TAG8 (Bitfield-Mask: 0x01) */ 474 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG9_Pos (9UL) /*!< TAG9 (Bit 9) */ 475 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG9_Msk (0x200UL) /*!< TAG9 (Bitfield-Mask: 0x01) */ 476 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG10_Pos (10UL) /*!< TAG10 (Bit 10) */ 477 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG10_Msk (0x400UL) /*!< TAG10 (Bitfield-Mask: 0x01) */ 478 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG11_Pos (11UL) /*!< TAG11 (Bit 11) */ 479 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG11_Msk (0x800UL) /*!< TAG11 (Bitfield-Mask: 0x01) */ 480 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG12_Pos (12UL) /*!< TAG12 (Bit 12) */ 481 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG12_Msk (0x1000UL) /*!< TAG12 (Bitfield-Mask: 0x01) */ 482 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG13_Pos (13UL) /*!< TAG13 (Bit 13) */ 483 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG13_Msk (0x2000UL) /*!< TAG13 (Bitfield-Mask: 0x01) */ 484 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG14_Pos (14UL) /*!< TAG14 (Bit 14) */ 485 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG14_Msk (0x4000UL) /*!< TAG14 (Bitfield-Mask: 0x01) */ 486 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG15_Pos (15UL) /*!< TAG15 (Bit 15) */ 487 #define MEC_ESPI_TAF_DNX_PR_BYP_TAG15_Msk (0x8000UL) /*!< TAG15 (Bitfield-Mask: 0x01) */ 488 #define MEC_ESPI_TAF_DNX_PR_BYP_DS_Pos (20UL) /*!< DS (Bit 20) */ 489 #define MEC_ESPI_TAF_DNX_PR_BYP_DS_Msk (0x100000UL) /*!< DS (Bitfield-Mask: 0x01) */ 490 #define MEC_ESPI_TAF_DNX_PR_BYP_DM_Pos (24UL) /*!< DM (Bit 24) */ 491 #define MEC_ESPI_TAF_DNX_PR_BYP_DM_Msk (0x1000000UL) /*!< DM (Bitfield-Mask: 0x01) */ 492 #define MEC_ESPI_TAF_DNX_PR_BYP_LOCK_Pos (28UL) /*!< LOCK (Bit 28) */ 493 #define MEC_ESPI_TAF_DNX_PR_BYP_LOCK_Msk (0x10000000UL) /*!< LOCK (Bitfield-Mask: 0x01) */ 494 /* ===================================================== ACT_CNT_RLOAD ===================================================== */ 495 /* ======================================================== PD_CTRL ======================================================== */ 496 #define MEC_ESPI_TAF_PD_CTRL_CS0_PD_EN_Pos (0UL) /*!< CS0_PD_EN (Bit 0) */ 497 #define MEC_ESPI_TAF_PD_CTRL_CS0_PD_EN_Msk (0x1UL) /*!< CS0_PD_EN (Bitfield-Mask: 0x01) */ 498 #define MEC_ESPI_TAF_PD_CTRL_CS1_PD_EN_Pos (1UL) /*!< CS1_PD_EN (Bit 1) */ 499 #define MEC_ESPI_TAF_PD_CTRL_CS1_PD_EN_Msk (0x2UL) /*!< CS1_PD_EN (Bitfield-Mask: 0x01) */ 500 #define MEC_ESPI_TAF_PD_CTRL_CS0_WAKE_EN_Pos (2UL) /*!< CS0_WAKE_EN (Bit 2) */ 501 #define MEC_ESPI_TAF_PD_CTRL_CS0_WAKE_EN_Msk (0x4UL) /*!< CS0_WAKE_EN (Bitfield-Mask: 0x01) */ 502 #define MEC_ESPI_TAF_PD_CTRL_CS1_WAKE_EN_Pos (3UL) /*!< CS1_WAKE_EN (Bit 3) */ 503 #define MEC_ESPI_TAF_PD_CTRL_CS1_WAKE_EN_Msk (0x8UL) /*!< CS1_WAKE_EN (Bitfield-Mask: 0x01) */ 504 /* ======================================================== PD_STS ========================================================= */ 505 #define MEC_ESPI_TAF_PD_STS_CS0_Pos (0UL) /*!< CS0 (Bit 0) */ 506 #define MEC_ESPI_TAF_PD_STS_CS0_Msk (0x1UL) /*!< CS0 (Bitfield-Mask: 0x01) */ 507 #define MEC_ESPI_TAF_PD_STS_CS1_Pos (1UL) /*!< CS1 (Bit 1) */ 508 #define MEC_ESPI_TAF_PD_STS_CS1_Msk (0x2UL) /*!< CS1 (Bitfield-Mask: 0x01) */ 509 /* ======================================================== CS0_OPD ======================================================== */ 510 #define MEC_ESPI_TAF_CS0_OPD_ENTER_PD_Pos (0UL) /*!< ENTER_PD (Bit 0) */ 511 #define MEC_ESPI_TAF_CS0_OPD_ENTER_PD_Msk (0xffUL) /*!< ENTER_PD (Bitfield-Mask: 0xff) */ 512 #define MEC_ESPI_TAF_CS0_OPD_EXIT_PD_Pos (8UL) /*!< EXIT_PD (Bit 8) */ 513 #define MEC_ESPI_TAF_CS0_OPD_EXIT_PD_Msk (0xff00UL) /*!< EXIT_PD (Bitfield-Mask: 0xff) */ 514 #define MEC_ESPI_TAF_CS0_OPD_RPMC_OP2_Pos (16UL) /*!< RPMC_OP2 (Bit 16) */ 515 #define MEC_ESPI_TAF_CS0_OPD_RPMC_OP2_Msk (0xff0000UL) /*!< RPMC_OP2 (Bitfield-Mask: 0xff) */ 516 /* ======================================================== CS1_OPD ======================================================== */ 517 #define MEC_ESPI_TAF_CS1_OPD_ENTER_PD_Pos (0UL) /*!< ENTER_PD (Bit 0) */ 518 #define MEC_ESPI_TAF_CS1_OPD_ENTER_PD_Msk (0xffUL) /*!< ENTER_PD (Bitfield-Mask: 0xff) */ 519 #define MEC_ESPI_TAF_CS1_OPD_EXIT_PD_Pos (8UL) /*!< EXIT_PD (Bit 8) */ 520 #define MEC_ESPI_TAF_CS1_OPD_EXIT_PD_Msk (0xff00UL) /*!< EXIT_PD (Bitfield-Mask: 0xff) */ 521 #define MEC_ESPI_TAF_CS1_OPD_RPMC_OP2_Pos (16UL) /*!< RPMC_OP2 (Bit 16) */ 522 #define MEC_ESPI_TAF_CS1_OPD_RPMC_OP2_Msk (0xff0000UL) /*!< RPMC_OP2 (Bitfield-Mask: 0xff) */ 523 /* ====================================================== PUD_TIMEOUT ====================================================== */ 524 /* ====================================================== CLKDIV_CS0 ======================================================= */ 525 #define MEC_ESPI_TAF_CLKDIV_CS0_READ_Pos (0UL) /*!< READ (Bit 0) */ 526 #define MEC_ESPI_TAF_CLKDIV_CS0_READ_Msk (0xffffUL) /*!< READ (Bitfield-Mask: 0xffff) */ 527 #define MEC_ESPI_TAF_CLKDIV_CS0_NON_READ_Pos (16UL) /*!< NON_READ (Bit 16) */ 528 #define MEC_ESPI_TAF_CLKDIV_CS0_NON_READ_Msk (0xffff0000UL) /*!< NON_READ (Bitfield-Mask: 0xffff) */ 529 /* ====================================================== CLKDIV_CS1 ======================================================= */ 530 #define MEC_ESPI_TAF_CLKDIV_CS1_READ_Pos (0UL) /*!< READ (Bit 0) */ 531 #define MEC_ESPI_TAF_CLKDIV_CS1_READ_Msk (0xffffUL) /*!< READ (Bitfield-Mask: 0xffff) */ 532 #define MEC_ESPI_TAF_CLKDIV_CS1_NON_READ_Pos (16UL) /*!< NON_READ (Bit 16) */ 533 #define MEC_ESPI_TAF_CLKDIV_CS1_NON_READ_Msk (0xffff0000UL) /*!< NON_READ (Bitfield-Mask: 0xffff) */ 534 535 /** @} */ /* End of group PosMask_peripherals */ 536 537 /** @addtogroup EnumValue_peripherals 538 * @{ 539 */ 540 /* ================ MEC_ESPI_TAF ================ */ 541 /* ======================================================== ECP_CMD ======================================================== */ 542 /* ========================================== MEC_ESPI_TAF ECP_CMD EC_CMD [8..15] ========================================== */ 543 typedef enum { /*!< MEC_ESPI_TAF_ECP_CMD_EC_CMD */ 544 MEC_ESPI_TAF_ECP_CMD_EC_CMD_READ = 0, /*!< READ : Perform read of flash devices */ 545 MEC_ESPI_TAF_ECP_CMD_EC_CMD_WRITE = 1, /*!< WRITE : Perform write(program) of flash devices */ 546 MEC_ESPI_TAF_ECP_CMD_EC_CMD_ERASE = 2, /*!< ERASE : Perform region erase of flash devices */ 547 MEC_ESPI_TAF_ECP_CMD_EC_CMD_RPMC_OP1_CS0 = 3, /*!< RPMC_OP1_CS0 : Perform RPMC OP1 operation on flash at CS0 */ 548 MEC_ESPI_TAF_ECP_CMD_EC_CMD_RPMC_OP2_CS0 = 4, /*!< RPMC_OP2_CS0 : Perform RPMC OP2 operation on flash at CS0 */ 549 MEC_ESPI_TAF_ECP_CMD_EC_CMD_RPMC_OP1_CS1 = 131,/*!< RPMC_OP1_CS1 : Perform RPMC OP1 operation on flash at CS1 */ 550 MEC_ESPI_TAF_ECP_CMD_EC_CMD_RPMC_OP2_CS1 = 132,/*!< RPMC_OP2_CS1 : Perform RPMC OP2 operation on flash at CS1 */ 551 } MEC_ESPI_TAF_ECP_CMD_EC_CMD_Enum; 552 553 /* =========================================== MEC_ESPI_TAF ECP_CMD LEN [24..31] =========================================== */ 554 typedef enum { /*!< MEC_ESPI_TAF_ECP_CMD_LEN */ 555 MEC_ESPI_TAF_ECP_CMD_LEN_ERASE_4K = 0, /*!< ERASE_4K : Erase 4KB sector encoding */ 556 MEC_ESPI_TAF_ECP_CMD_LEN_ERASE_32K = 1, /*!< ERASE_32K : Erase 32KB sector encoding */ 557 MEC_ESPI_TAF_ECP_CMD_LEN_ERASE_64K = 2, /*!< ERASE_64K : Erase 64KB sector encoding */ 558 } MEC_ESPI_TAF_ECP_CMD_LEN_Enum; 559 560 /* ======================================================== FC_MISC ======================================================== */ 561 /* ======================================= MEC_ESPI_TAF FC_MISC PREFETCH_MODE [0..1] ======================================= */ 562 typedef enum { /*!< MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE */ 563 MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE_DEFAULT = 0,/*!< DEFAULT : Default prefetch method defined in eSPI TAF specification */ 564 MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE_EXPEDITED = 3,/*!< EXPEDITED : Expedited prefetch methods */ 565 } MEC_ESPI_TAF_FC_MISC_PREFETCH_MODE_Enum; 566 567 /* ===================================================== POLL_TIMEOUT ====================================================== */ 568 /* ========================================= MEC_ESPI_TAF POLL_TIMEOUT VAL [0..17] ========================================= */ 569 typedef enum { /*!< MEC_ESPI_TAF_POLL_TIMEOUT_VAL */ 570 MEC_ESPI_TAF_POLL_TIMEOUT_VAL_5SEC = 163840,/*!< 5SEC : Recommend flash POLL1 timeout is 5 seconds */ 571 } MEC_ESPI_TAF_POLL_TIMEOUT_VAL_Enum; 572 573 /** @} */ /* End of group EnumValue_peripherals */ 574 575 #endif /* _MEC5_ESPI_TAF_V1_4_H */ 576
