1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_ESPI_MEM_V1_4_H 7 #define _MEC5_ESPI_MEM_V1_4_H 8 9 /** @addtogroup Device_Peripheral_clusters 10 * @{ 11 */ 12 13 /** 14 * @brief MEC_ESPI_MEM_EC_MEM_BAR [EC_MEM_BAR] (Memory BAR LDN and memory address mask. EC-only access) 15 */ 16 typedef struct mec_espi_mem_ec_mem_bar_regs { 17 __IM uint16_t LDN_MSK; /*!< (@ 0x00000000) eSPI Memory BAR LDN and address mask (EC-only 18 access) */ 19 __IM uint16_t RSVD_H1; /*!< (@ 0x00000002) Bits[31:16] reserved */ 20 __IM uint16_t RSVD_H2; /*!< (@ 0x00000004) Bits[47:32] reserved */ 21 __IM uint16_t RSVD_H3; /*!< (@ 0x00000006) Bits[63:48] reserved */ 22 __IM uint16_t RSVD_H4; /*!< (@ 0x00000008) Bits[79:64] reserved */ 23 } MEC_ESPI_MEM_EC_MEM_BAR_Type; /*!< Size = 10 (0xa) */ 24 25 26 /** 27 * @brief MEC_ESPI_MEM_EC_SRAM_BAR [EC_SRAM_BAR] (SRAM Memory BAR valid, access, size, and EC memory base. EC-only access) 28 */ 29 typedef struct mec_espi_mem_ec_sram_bar_regs { 30 __IOM uint16_t VASZ; /*!< (@ 0x00000000) 16-bit register with valid(enable), access mode, 31 and size */ 32 __IOM uint16_t EC_SRAM_ADDR_15_0; /*!< (@ 0x00000002) EC SRAM region base address[15:0] */ 33 __IOM uint16_t EC_SRAM_ADDR_31_16; /*!< (@ 0x00000004) EC SRAM region base address[31:16] */ 34 __IM uint16_t RESERVED[2]; 35 } MEC_ESPI_MEM_EC_SRAM_BAR_Type; /*!< Size = 10 (0xa) */ 36 37 38 /** 39 * @brief MEC_ESPI_MEM_HOST_MEM_BAR [HOST_MEM_BAR] (Memory BAR Host memory address mask. Host and EC access) 40 */ 41 typedef struct mec_espi_mem_host_mem_bar_regs { 42 __IOM uint16_t VALID; /*!< (@ 0x00000000) eSPI Memory Host memory valid enable */ 43 __IOM uint16_t HOST_MEM_ADDR_B15_0; /*!< (@ 0x00000002) Host memory address bits[15:0] */ 44 __IOM uint16_t HOST_MEM_ADDR_B31_16; /*!< (@ 0x00000004) Host memory address bits[31:16] */ 45 __IOM uint16_t RSVD_H3; /*!< (@ 0x00000006) Bits[63:48] reserved */ 46 __IOM uint16_t RSVD_H4; /*!< (@ 0x00000008) Bits[79:64] reserved */ 47 } MEC_ESPI_MEM_HOST_MEM_BAR_Type; /*!< Size = 10 (0xa) */ 48 49 50 /** 51 * @brief MEC_ESPI_MEM_HOST_SRAM_BAR [HOST_SRAM_BAR] (SRAM Memory BAR valid, access, size, and EC memory base. EC-only access) 52 */ 53 typedef struct mec_espi_mem_host_sram_bar_regs { 54 __IM uint16_t VASZ; /*!< (@ 0x00000000) 16-bit register with valid(enable), access mode, 55 and size */ 56 __IOM uint16_t HOST_ADDR_15_0; /*!< (@ 0x00000002) Host address[15:0] for accessing the EC SRAM 57 region */ 58 __IOM uint16_t HOST_ADDR_31_16; /*!< (@ 0x00000004) Host address[31:16] for access the EC SRAM region */ 59 __IM uint16_t RESERVED[2]; 60 } MEC_ESPI_MEM_HOST_SRAM_BAR_Type; /*!< Size = 10 (0xa) */ 61 62 /** @} */ /* End of group Device_Peripheral_clusters */ 63 64 /** @addtogroup Device_Peripheral_peripherals 65 * @{ 66 */ 67 68 /** 69 * @brief eSPI Memory component (MEC_ESPI_MEM) 70 */ 71 72 typedef struct mec_espi_mem_regs { /*!< (@ 0x400F3800) MEC_ESPI_MEM Structure */ 73 __IM uint32_t RESERVED[76]; 74 __IM MEC_ESPI_MEM_EC_MEM_BAR_Type EC_MEM_BAR[10];/*!< (@ 0x00000130) Memory BAR LDN and memory address mask. EC-only 75 access */ 76 __IM uint32_t RESERVED1[6]; 77 __IOM MEC_ESPI_MEM_EC_SRAM_BAR_Type EC_SRAM_BAR[2];/*!< (@ 0x000001AC) SRAM Memory BAR valid, access, size, and EC memory 78 base. EC-only access */ 79 __IM uint32_t RESERVED2[16]; 80 __IOM uint32_t BM_STATUS; /*!< (@ 0x00000200) eSPI Memory Component Bus Master Status register */ 81 __IOM uint32_t BM_IEN; /*!< (@ 0x00000204) eSPI Memory Component Bus Master Interrupt Enable 82 register */ 83 __IOM uint32_t BM_CONFIG; /*!< (@ 0x00000208) eSPI Memory Component Bus Master Configuration 84 register */ 85 __IM uint32_t RESERVED3; 86 __IOM uint32_t BM_CTRL1; /*!< (@ 0x00000210) eSPI Memory Component Bus Master Control 1 register */ 87 __IOM uint32_t BM1_HADDR_LSW; /*!< (@ 0x00000214) eSPI Memory Component Bus Master 1 Host Address 88 b[31:0] */ 89 __IOM uint32_t BM1_HADDR_MSW; /*!< (@ 0x00000218) eSPI Memory Component Bus Master 1 Host Address 90 b[63:32] */ 91 __IOM uint32_t BM1_EC_ADDR_LSW; /*!< (@ 0x0000021C) eSPI Memory Component Bus Master 1 EC SRAM Address 92 b[31:0] */ 93 __IOM uint32_t BM1_EC_ADDR_MSW; /*!< (@ 0x00000220) eSPI Memory Component Bus Master 1 EC SRAM Address 94 b[63:32] */ 95 __IOM uint32_t BM_CTRL2; /*!< (@ 0x00000224) eSPI Memory Component Bus Master Control 2 register */ 96 __IOM uint32_t BM2_HADDR_LSW; /*!< (@ 0x00000228) eSPI Memory Component Bus Master 2 Host Address 97 b[31:0] */ 98 __IOM uint32_t BM2_HADDR_MSW; /*!< (@ 0x0000022C) eSPI Memory Component Bus Master 2 Host Address 99 b[63:32] */ 100 __IOM uint32_t BM2_EC_ADDR_LSW; /*!< (@ 0x00000230) eSPI Memory Component Bus Master 2 EC SRAM Address 101 b[31:0] */ 102 __IOM uint32_t BM2_EC_ADDR_MSW; /*!< (@ 0x00000234) eSPI Memory Component Bus Master 2 EC SRAM Address 103 b[63:32] */ 104 __IM uint32_t RESERVED4[62]; 105 __IOM MEC_ESPI_MEM_HOST_MEM_BAR_Type HOST_MEM_BAR[10];/*!< (@ 0x00000330) Memory BAR Host memory address mask. Host and 106 EC access */ 107 __IM uint32_t RESERVED5[5]; 108 __IOM uint32_t MBAR_HOST_EXTEND; /*!< (@ 0x000003A8) Host and EC access: Provides Host memory address 109 bits[47:32] for all Logical Device memory 110 BARs */ 111 __IOM MEC_ESPI_MEM_HOST_SRAM_BAR_Type HOST_SRAM_BAR[2];/*!< (@ 0x000003AC) SRAM Memory BAR valid, access, size, and EC memory 112 base. EC-only access */ 113 __IM uint32_t RESERVED6[15]; 114 __IOM uint32_t SRAM_BAR_HOST_EXTEND; /*!< (@ 0x000003FC) Host and EC access: provides Host memory address 115 bits[47:32]. Applies to both SRAM memory 116 BARs */ 117 } MEC_ESPI_MEM_Type; /*!< Size = 1024 (0x400) */ 118 119 /** @} */ /* End of group Device_Peripheral_peripherals */ 120 121 /** @addtogroup PosMask_clusters 122 * @{ 123 */ 124 /* ================ EC_MEM_BAR ================ */ 125 /* ======================================================== LDN_MSK ======================================================== */ 126 #define MEC_ESPI_MEM_EC_MEM_BAR_LDN_MSK_LDN_Pos (0UL) /*!< LDN (Bit 0) */ 127 #define MEC_ESPI_MEM_EC_MEM_BAR_LDN_MSK_LDN_Msk (0xffUL) /*!< LDN (Bitfield-Mask: 0xff) */ 128 #define MEC_ESPI_MEM_EC_MEM_BAR_LDN_MSK_MSK_Pos (8UL) /*!< MSK (Bit 8) */ 129 #define MEC_ESPI_MEM_EC_MEM_BAR_LDN_MSK_MSK_Msk (0x3f00UL) /*!< MSK (Bitfield-Mask: 0x3f) */ 130 131 /* ========================================================= VASZ ========================================================== */ 132 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID_Pos (0UL) /*!< VALID (Bit 0) */ 133 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID_Msk (0x1UL) /*!< VALID (Bitfield-Mask: 0x01) */ 134 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_Pos (1UL) /*!< ACCESS (Bit 1) */ 135 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_Msk (0x6UL) /*!< ACCESS (Bitfield-Mask: 0x03) */ 136 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ 137 #define MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ 138 139 /* ========================================================= VALID ========================================================= */ 140 #define MEC_ESPI_MEM_HOST_MEM_BAR_VALID_EN_Pos (0UL) /*!< EN (Bit 0) */ 141 #define MEC_ESPI_MEM_HOST_MEM_BAR_VALID_EN_Msk (0x1UL) /*!< EN (Bitfield-Mask: 0x01) */ 142 143 /* ================ HOST_SRAM_BAR ================ */ 144 /* ========================================================= VASZ ========================================================== */ 145 #define MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_Pos (1UL) /*!< ACCESS (Bit 1) */ 146 #define MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_Msk (0x6UL) /*!< ACCESS (Bitfield-Mask: 0x03) */ 147 #define MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_Pos (4UL) /*!< SIZE (Bit 4) */ 148 #define MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_Msk (0xf0UL) /*!< SIZE (Bitfield-Mask: 0x0f) */ 149 150 151 /** @} */ /* End of group PosMask_clusters */ 152 153 /** @addtogroup PosMask_peripherals 154 * @{ 155 */ 156 /* ======================================================= BM_STATUS ======================================================= */ 157 #define MEC_ESPI_MEM_BM_STATUS_BM1_XFR_DONE_Pos (0UL) /*!< BM1_XFR_DONE (Bit 0) */ 158 #define MEC_ESPI_MEM_BM_STATUS_BM1_XFR_DONE_Msk (0x1UL) /*!< BM1_XFR_DONE (Bitfield-Mask: 0x01) */ 159 #define MEC_ESPI_MEM_BM_STATUS_BM1_BUSY_Pos (1UL) /*!< BM1_BUSY (Bit 1) */ 160 #define MEC_ESPI_MEM_BM_STATUS_BM1_BUSY_Msk (0x2UL) /*!< BM1_BUSY (Bitfield-Mask: 0x01) */ 161 #define MEC_ESPI_MEM_BM_STATUS_BM1_EC_ABORT_Pos (2UL) /*!< BM1_EC_ABORT (Bit 2) */ 162 #define MEC_ESPI_MEM_BM_STATUS_BM1_EC_ABORT_Msk (0x4UL) /*!< BM1_EC_ABORT (Bitfield-Mask: 0x01) */ 163 #define MEC_ESPI_MEM_BM_STATUS_BM1_HOST_ABORT_Pos (3UL) /*!< BM1_HOST_ABORT (Bit 3) */ 164 #define MEC_ESPI_MEM_BM_STATUS_BM1_HOST_ABORT_Msk (0x8UL) /*!< BM1_HOST_ABORT (Bitfield-Mask: 0x01) */ 165 #define MEC_ESPI_MEM_BM_STATUS_BM1_CH2_ERR_ABORT_Pos (4UL) /*!< BM1_CH2_ERR_ABORT (Bit 4) */ 166 #define MEC_ESPI_MEM_BM_STATUS_BM1_CH2_ERR_ABORT_Msk (0x10UL) /*!< BM1_CH2_ERR_ABORT (Bitfield-Mask: 0x01) */ 167 #define MEC_ESPI_MEM_BM_STATUS_BM1_START_OVRFL_Pos (5UL) /*!< BM1_START_OVRFL (Bit 5) */ 168 #define MEC_ESPI_MEM_BM_STATUS_BM1_START_OVRFL_Msk (0x20UL) /*!< BM1_START_OVRFL (Bitfield-Mask: 0x01) */ 169 #define MEC_ESPI_MEM_BM_STATUS_BM1_DATA_OVRUN_Pos (6UL) /*!< BM1_DATA_OVRUN (Bit 6) */ 170 #define MEC_ESPI_MEM_BM_STATUS_BM1_DATA_OVRUN_Msk (0x40UL) /*!< BM1_DATA_OVRUN (Bitfield-Mask: 0x01) */ 171 #define MEC_ESPI_MEM_BM_STATUS_BM1_INCOMPL_Pos (7UL) /*!< BM1_INCOMPL (Bit 7) */ 172 #define MEC_ESPI_MEM_BM_STATUS_BM1_INCOMPL_Msk (0x80UL) /*!< BM1_INCOMPL (Bitfield-Mask: 0x01) */ 173 #define MEC_ESPI_MEM_BM_STATUS_BM1_FAIL_Pos (8UL) /*!< BM1_FAIL (Bit 8) */ 174 #define MEC_ESPI_MEM_BM_STATUS_BM1_FAIL_Msk (0x100UL) /*!< BM1_FAIL (Bitfield-Mask: 0x01) */ 175 #define MEC_ESPI_MEM_BM_STATUS_BM1_AHB_BUS_ERR_Pos (9UL) /*!< BM1_AHB_BUS_ERR (Bit 9) */ 176 #define MEC_ESPI_MEM_BM_STATUS_BM1_AHB_BUS_ERR_Msk (0x200UL) /*!< BM1_AHB_BUS_ERR (Bitfield-Mask: 0x01) */ 177 #define MEC_ESPI_MEM_BM_STATUS_BM1_BAD_REQ_Pos (11UL) /*!< BM1_BAD_REQ (Bit 11) */ 178 #define MEC_ESPI_MEM_BM_STATUS_BM1_BAD_REQ_Msk (0x800UL) /*!< BM1_BAD_REQ (Bitfield-Mask: 0x01) */ 179 #define MEC_ESPI_MEM_BM_STATUS_BM2_XFR_DONE_Pos (16UL) /*!< BM2_XFR_DONE (Bit 16) */ 180 #define MEC_ESPI_MEM_BM_STATUS_BM2_XFR_DONE_Msk (0x10000UL) /*!< BM2_XFR_DONE (Bitfield-Mask: 0x01) */ 181 #define MEC_ESPI_MEM_BM_STATUS_BM2_BUSY_Pos (17UL) /*!< BM2_BUSY (Bit 17) */ 182 #define MEC_ESPI_MEM_BM_STATUS_BM2_BUSY_Msk (0x20000UL) /*!< BM2_BUSY (Bitfield-Mask: 0x01) */ 183 #define MEC_ESPI_MEM_BM_STATUS_BM2_EC_ABORT_Pos (18UL) /*!< BM2_EC_ABORT (Bit 18) */ 184 #define MEC_ESPI_MEM_BM_STATUS_BM2_EC_ABORT_Msk (0x40000UL) /*!< BM2_EC_ABORT (Bitfield-Mask: 0x01) */ 185 #define MEC_ESPI_MEM_BM_STATUS_BM2_HOST_ABORT_Pos (19UL) /*!< BM2_HOST_ABORT (Bit 19) */ 186 #define MEC_ESPI_MEM_BM_STATUS_BM2_HOST_ABORT_Msk (0x80000UL) /*!< BM2_HOST_ABORT (Bitfield-Mask: 0x01) */ 187 #define MEC_ESPI_MEM_BM_STATUS_BM2_CH1_ERR_ABORT_Pos (20UL) /*!< BM2_CH1_ERR_ABORT (Bit 20) */ 188 #define MEC_ESPI_MEM_BM_STATUS_BM2_CH1_ERR_ABORT_Msk (0x100000UL) /*!< BM2_CH1_ERR_ABORT (Bitfield-Mask: 0x01) */ 189 #define MEC_ESPI_MEM_BM_STATUS_BM2_START_OVRFL_Pos (21UL) /*!< BM2_START_OVRFL (Bit 21) */ 190 #define MEC_ESPI_MEM_BM_STATUS_BM2_START_OVRFL_Msk (0x200000UL) /*!< BM2_START_OVRFL (Bitfield-Mask: 0x01) */ 191 #define MEC_ESPI_MEM_BM_STATUS_BM2_DATA_OVRUN_Pos (22UL) /*!< BM2_DATA_OVRUN (Bit 22) */ 192 #define MEC_ESPI_MEM_BM_STATUS_BM2_DATA_OVRUN_Msk (0x400000UL) /*!< BM2_DATA_OVRUN (Bitfield-Mask: 0x01) */ 193 #define MEC_ESPI_MEM_BM_STATUS_BM2_INCOMPL_Pos (23UL) /*!< BM2_INCOMPL (Bit 23) */ 194 #define MEC_ESPI_MEM_BM_STATUS_BM2_INCOMPL_Msk (0x800000UL) /*!< BM2_INCOMPL (Bitfield-Mask: 0x01) */ 195 #define MEC_ESPI_MEM_BM_STATUS_BM2_FAIL_Pos (24UL) /*!< BM2_FAIL (Bit 24) */ 196 #define MEC_ESPI_MEM_BM_STATUS_BM2_FAIL_Msk (0x1000000UL) /*!< BM2_FAIL (Bitfield-Mask: 0x01) */ 197 #define MEC_ESPI_MEM_BM_STATUS_BM2_AHB_BUS_ERR_Pos (25UL) /*!< BM2_AHB_BUS_ERR (Bit 25) */ 198 #define MEC_ESPI_MEM_BM_STATUS_BM2_AHB_BUS_ERR_Msk (0x2000000UL) /*!< BM2_AHB_BUS_ERR (Bitfield-Mask: 0x01) */ 199 #define MEC_ESPI_MEM_BM_STATUS_BM2_BAD_REQ_Pos (27UL) /*!< BM2_BAD_REQ (Bit 27) */ 200 #define MEC_ESPI_MEM_BM_STATUS_BM2_BAD_REQ_Msk (0x8000000UL) /*!< BM2_BAD_REQ (Bitfield-Mask: 0x01) */ 201 /* ======================================================== BM_IEN ========================================================= */ 202 #define MEC_ESPI_MEM_BM_IEN_BM1_XFR_DONE_IEN_Pos (0UL) /*!< BM1_XFR_DONE_IEN (Bit 0) */ 203 #define MEC_ESPI_MEM_BM_IEN_BM1_XFR_DONE_IEN_Msk (0x1UL) /*!< BM1_XFR_DONE_IEN (Bitfield-Mask: 0x01) */ 204 #define MEC_ESPI_MEM_BM_IEN_BM2_XFR_DONE_IEN_Pos (16UL) /*!< BM2_XFR_DONE_IEN (Bit 16) */ 205 #define MEC_ESPI_MEM_BM_IEN_BM2_XFR_DONE_IEN_Msk (0x10000UL) /*!< BM2_XFR_DONE_IEN (Bitfield-Mask: 0x01) */ 206 /* ======================================================= BM_CONFIG ======================================================= */ 207 #define MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_Pos (0UL) /*!< BM1_TAG (Bit 0) */ 208 #define MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_Msk (0xfUL) /*!< BM1_TAG (Bitfield-Mask: 0x0f) */ 209 #define MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_Pos (16UL) /*!< BM2_TAG (Bit 16) */ 210 #define MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_Msk (0xf0000UL) /*!< BM2_TAG (Bitfield-Mask: 0x0f) */ 211 /* ======================================================= BM_CTRL1 ======================================================== */ 212 #define MEC_ESPI_MEM_BM_CTRL1_START_Pos (0UL) /*!< START (Bit 0) */ 213 #define MEC_ESPI_MEM_BM_CTRL1_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ 214 #define MEC_ESPI_MEM_BM_CTRL1_ABORT_Pos (1UL) /*!< ABORT (Bit 1) */ 215 #define MEC_ESPI_MEM_BM_CTRL1_ABORT_Msk (0x2UL) /*!< ABORT (Bitfield-Mask: 0x01) */ 216 #define MEC_ESPI_MEM_BM_CTRL1_INCR_AHB_ADDR_Pos (2UL) /*!< INCR_AHB_ADDR (Bit 2) */ 217 #define MEC_ESPI_MEM_BM_CTRL1_INCR_AHB_ADDR_Msk (0x4UL) /*!< INCR_AHB_ADDR (Bitfield-Mask: 0x01) */ 218 #define MEC_ESPI_MEM_BM_CTRL1_WAIT_BM2_NOT_BUSY_Pos (3UL) /*!< WAIT_BM2_NOT_BUSY (Bit 3) */ 219 #define MEC_ESPI_MEM_BM_CTRL1_WAIT_BM2_NOT_BUSY_Msk (0x8UL) /*!< WAIT_BM2_NOT_BUSY (Bitfield-Mask: 0x01) */ 220 #define MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_Pos (8UL) /*!< CYCLE_TYPE (Bit 8) */ 221 #define MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_Msk (0x300UL) /*!< CYCLE_TYPE (Bitfield-Mask: 0x03) */ 222 #define MEC_ESPI_MEM_BM_CTRL1_LEN_Pos (16UL) /*!< LEN (Bit 16) */ 223 #define MEC_ESPI_MEM_BM_CTRL1_LEN_Msk (0x1fff0000UL) /*!< LEN (Bitfield-Mask: 0x1fff) */ 224 /* ===================================================== BM1_HADDR_LSW ===================================================== */ 225 /* ===================================================== BM1_HADDR_MSW ===================================================== */ 226 /* ==================================================== BM1_EC_ADDR_LSW ==================================================== */ 227 /* ==================================================== BM1_EC_ADDR_MSW ==================================================== */ 228 /* ======================================================= BM_CTRL2 ======================================================== */ 229 #define MEC_ESPI_MEM_BM_CTRL2_START_Pos (0UL) /*!< START (Bit 0) */ 230 #define MEC_ESPI_MEM_BM_CTRL2_START_Msk (0x1UL) /*!< START (Bitfield-Mask: 0x01) */ 231 #define MEC_ESPI_MEM_BM_CTRL2_ABORT_Pos (1UL) /*!< ABORT (Bit 1) */ 232 #define MEC_ESPI_MEM_BM_CTRL2_ABORT_Msk (0x2UL) /*!< ABORT (Bitfield-Mask: 0x01) */ 233 #define MEC_ESPI_MEM_BM_CTRL2_INCR_AHB_ADDR_Pos (2UL) /*!< INCR_AHB_ADDR (Bit 2) */ 234 #define MEC_ESPI_MEM_BM_CTRL2_INCR_AHB_ADDR_Msk (0x4UL) /*!< INCR_AHB_ADDR (Bitfield-Mask: 0x01) */ 235 #define MEC_ESPI_MEM_BM_CTRL2_WAIT_BM2_NOT_BUSY_Pos (3UL) /*!< WAIT_BM2_NOT_BUSY (Bit 3) */ 236 #define MEC_ESPI_MEM_BM_CTRL2_WAIT_BM2_NOT_BUSY_Msk (0x8UL) /*!< WAIT_BM2_NOT_BUSY (Bitfield-Mask: 0x01) */ 237 #define MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_Pos (8UL) /*!< CYCLE_TYPE (Bit 8) */ 238 #define MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_Msk (0x300UL) /*!< CYCLE_TYPE (Bitfield-Mask: 0x03) */ 239 #define MEC_ESPI_MEM_BM_CTRL2_LEN_Pos (16UL) /*!< LEN (Bit 16) */ 240 #define MEC_ESPI_MEM_BM_CTRL2_LEN_Msk (0x1fff0000UL) /*!< LEN (Bitfield-Mask: 0x1fff) */ 241 /** @} */ /* End of group PosMask_peripherals */ 242 243 /** @addtogroup EnumValue_clusters 244 * @{ 245 */ 246 /* ====================================================== EC_MEM_BAR ====================================================== */ 247 typedef enum { /*!< MEC_ESPI_MEM_EC_MEM_BAR */ 248 MEC_ESPI_MEM_EC_MEM_BAR_MBOX = 0, /*!< MBOX : Mailbox LDN and memory address mask */ 249 MEC_ESPI_MEM_EC_MEM_BAR_ACPI_EC0 = 1, /*!< ACPI_EC0 : eSPI ACPI EC0 LDN and memory address mask */ 250 MEC_ESPI_MEM_EC_MEM_BAR_ACPI_EC1 = 2, /*!< ACPI_EC1 : eSPI ACPI EC1 LDN and memory address mask */ 251 MEC_ESPI_MEM_EC_MEM_BAR_ACPI_EC2 = 3, /*!< ACPI_EC2 : eSPI ACPI EC2 LDN and memory address mask */ 252 MEC_ESPI_MEM_EC_MEM_BAR_ACPI_EC3 = 4, /*!< ACPI_EC3 : eSPI ACPI EC3 LDN and memory address mask */ 253 MEC_ESPI_MEM_EC_MEM_BAR_ACPI_EC4 = 5, /*!< ACPI_EC4 : eSPI ACPI EC4 LDN and memory address mask */ 254 MEC_ESPI_MEM_EC_MEM_BAR_EMI0 = 6, /*!< EMI0 : eSPI EMI0 LDN and memory address mask */ 255 MEC_ESPI_MEM_EC_MEM_BAR_EMI1 = 7, /*!< EMI1 : eSPI EMI1 LDN and memory address mask */ 256 MEC_ESPI_MEM_EC_MEM_BAR_EMI2 = 8, /*!< EMI2 : eSPI EMI2 LDN and memory address mask */ 257 MEC_ESPI_MEM_EC_MEM_BAR_RSVD9 = 9, /*!< RSVD9 : eSPI Reserved LDN and memory address mask */ 258 } MEC_ESPI_MEM_EC_MEM_BAR_Enum; 259 260 /* ================ EC_SRAM_BAR ================ */ 261 /* ============================================= EC_SRAM_BAR VASZ VALID [0..0] ============================================= */ 262 typedef enum { /*!< MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID */ 263 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID_EN = 1, /*!< EN : Enable BAR to participate in eSPI memory address matches */ 264 } MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_VALID_Enum; 265 266 /* ============================================ EC_SRAM_BAR VASZ ACCESS [1..2] ============================================= */ 267 typedef enum { /*!< MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS */ 268 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_NONE = 0,/*!< NONE : Host has no access to this region */ 269 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_RO = 1, /*!< RO : Host has read-only access to this region */ 270 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_WO = 2, /*!< WO : Host has write-only access to this region */ 271 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_RW = 3, /*!< RW : Host has read-write access to this region */ 272 } MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_ACCESS_Enum; 273 274 /* ============================================= EC_SRAM_BAR VASZ SIZE [4..7] ============================================== */ 275 typedef enum { /*!< MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE */ 276 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_1B = 0, /*!< 1B : Size is one byte */ 277 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_2B = 1, /*!< 2B : Size is two bytes */ 278 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_4B = 2, /*!< 4B : Size is four bytes */ 279 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_8B = 3, /*!< 8B : Size is eight bytes */ 280 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_16B = 4, /*!< 16B : Size is 16 bytes */ 281 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_32B = 5, /*!< 32B : Size is 32 bytes */ 282 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_64B = 6, /*!< 64B : Size is 64 bytes */ 283 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_128B = 7, /*!< 128B : Size is 128 bytes */ 284 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_256B = 8, /*!< 256B : Size is 256 bytes */ 285 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_512B = 9, /*!< 512B : Size is 512 bytes */ 286 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_1KB = 10, /*!< 1KB : Size is 1KB */ 287 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_2KB = 11, /*!< 2KB : Size is 2KB */ 288 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_4KB = 12, /*!< 4KB : Size is 4KB */ 289 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_8KB = 13, /*!< 8KB : Size is 8KB */ 290 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_16KB = 14, /*!< 16KB : Size is 16KB */ 291 MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_32KB = 15, /*!< 32KB : Size is 32KB */ 292 } MEC_ESPI_MEM_EC_SRAM_BAR_VASZ_SIZE_Enum; 293 294 /* ================ HOST_MEM_BAR ================ */ 295 typedef enum { /*!< MEC_ESPI_MEM_HOST_MEM_BAR */ 296 MEC_ESPI_MEM_HOST_MEM_BAR_MBOX = 0, /*!< MBOX : Mailbox memory address bits[31:0] and valid bit */ 297 MEC_ESPI_MEM_HOST_MEM_BAR_ACPI_EC0 = 1, /*!< ACPI_EC0 : ACPI EC0 memory address bits[31:0] and valid bit */ 298 MEC_ESPI_MEM_HOST_MEM_BAR_ACPI_EC1 = 2, /*!< ACPI_EC1 : ACPI EC1 memory address bits[31:0] and valid bit */ 299 MEC_ESPI_MEM_HOST_MEM_BAR_ACPI_EC2 = 3, /*!< ACPI_EC2 : ACPI EC2 memory address bits[31:0] and valid bit */ 300 MEC_ESPI_MEM_HOST_MEM_BAR_ACPI_EC3 = 4, /*!< ACPI_EC3 : ACPI EC3 memory address bits[31:0] and valid bit */ 301 MEC_ESPI_MEM_HOST_MEM_BAR_ACPI_EC4 = 5, /*!< ACPI_EC4 : ACPI EC4 memory address bits[31:0] and valid bit */ 302 MEC_ESPI_MEM_HOST_MEM_BAR_EMI0 = 6, /*!< EMI0 : EMI0 memory address bits[31:0] and valid bit */ 303 MEC_ESPI_MEM_HOST_MEM_BAR_EMI1 = 7, /*!< EMI1 : EMI1 memory address bits[31:0] and valid bit */ 304 MEC_ESPI_MEM_HOST_MEM_BAR_EMI2 = 8, /*!< EMI2 : EMI2 memory address bits[31:0] and valid bit */ 305 MEC_ESPI_MEM_HOST_MEM_BAR_RSVD9 = 9, /*!< RSVD9 : eSPI Reserved memory address bits[31:0] and valid bit */ 306 } MEC_ESPI_MEM_HOST_MEM_BAR_Enum; 307 308 /* ================ HOST_SRAM_BAR ================ */ 309 /* =========================================== HOST_SRAM_BAR VASZ ACCESS [1..2] ============================================ */ 310 typedef enum { /*!< MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS */ 311 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_NONE = 0,/*!< NONE : Host has no access to this region */ 312 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_RO = 1,/*!< RO : Host has read-only access to this region */ 313 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_WO = 2,/*!< WO : Host has write-only access to this region */ 314 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_RW = 3,/*!< RW : Host has read-write access to this region */ 315 } MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_ACCESS_Enum; 316 317 /* ============================================ HOST_SRAM_BAR VASZ SIZE [4..7] ============================================= */ 318 typedef enum { /*!< MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE */ 319 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_1B = 0, /*!< 1B : Size is one byte */ 320 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_2B = 1, /*!< 2B : Size is two bytes */ 321 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_4B = 2, /*!< 4B : Size is four bytes */ 322 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_8B = 3, /*!< 8B : Size is eight bytes */ 323 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_16B = 4, /*!< 16B : Size is 16 bytes */ 324 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_32B = 5, /*!< 32B : Size is 32 bytes */ 325 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_64B = 6, /*!< 64B : Size is 64 bytes */ 326 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_128B = 7,/*!< 128B : Size is 128 bytes */ 327 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_256B = 8,/*!< 256B : Size is 256 bytes */ 328 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_512B = 9,/*!< 512B : Size is 512 bytes */ 329 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_1KB = 10,/*!< 1KB : Size is 1KB */ 330 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_2KB = 11,/*!< 2KB : Size is 2KB */ 331 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_4KB = 12,/*!< 4KB : Size is 4KB */ 332 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_8KB = 13,/*!< 8KB : Size is 8KB */ 333 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_16KB = 14,/*!< 16KB : Size is 16KB */ 334 MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_32KB = 15,/*!< 32KB : Size is 32KB */ 335 } MEC_ESPI_MEM_HOST_SRAM_BAR_VASZ_SIZE_Enum; 336 337 /** @} */ /* End of group EnumValue_clusters */ 338 339 /** @addtogroup EnumValue_peripherals 340 * @{ 341 */ 342 /* ======================================================= BM_STATUS ======================================================= */ 343 /* ====================================== MEC_ESPI_MEM BM_STATUS BM1_XFR_DONE [0..0] ======================================= */ 344 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_XFR_DONE */ 345 MEC_ESPI_MEM_BM_STATUS_BM1_XFR_DONE_ACTV = 1, /*!< ACTV : Status is active */ 346 } MEC_ESPI_MEM_BM_STATUS_BM1_XFR_DONE_Enum; 347 348 /* ======================================== MEC_ESPI_MEM BM_STATUS BM1_BUSY [1..1] ========================================= */ 349 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_BUSY */ 350 MEC_ESPI_MEM_BM_STATUS_BM1_BUSY_ACTV = 1, /*!< ACTV : Status is active */ 351 } MEC_ESPI_MEM_BM_STATUS_BM1_BUSY_Enum; 352 353 /* ====================================== MEC_ESPI_MEM BM_STATUS BM1_EC_ABORT [2..2] ======================================= */ 354 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_EC_ABORT */ 355 MEC_ESPI_MEM_BM_STATUS_BM1_EC_ABORT_ACTV = 1, /*!< ACTV : Status is active */ 356 } MEC_ESPI_MEM_BM_STATUS_BM1_EC_ABORT_Enum; 357 358 /* ===================================== MEC_ESPI_MEM BM_STATUS BM1_HOST_ABORT [3..3] ====================================== */ 359 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_HOST_ABORT */ 360 MEC_ESPI_MEM_BM_STATUS_BM1_HOST_ABORT_ACTV = 1,/*!< ACTV : Status is active */ 361 } MEC_ESPI_MEM_BM_STATUS_BM1_HOST_ABORT_Enum; 362 363 /* ==================================== MEC_ESPI_MEM BM_STATUS BM1_CH2_ERR_ABORT [4..4] ==================================== */ 364 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_CH2_ERR_ABORT */ 365 MEC_ESPI_MEM_BM_STATUS_BM1_CH2_ERR_ABORT_ACTV = 1,/*!< ACTV : Status is active */ 366 } MEC_ESPI_MEM_BM_STATUS_BM1_CH2_ERR_ABORT_Enum; 367 368 /* ===================================== MEC_ESPI_MEM BM_STATUS BM1_START_OVRFL [5..5] ===================================== */ 369 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_START_OVRFL */ 370 MEC_ESPI_MEM_BM_STATUS_BM1_START_OVRFL_ACTV = 1,/*!< ACTV : Status is active */ 371 } MEC_ESPI_MEM_BM_STATUS_BM1_START_OVRFL_Enum; 372 373 /* ===================================== MEC_ESPI_MEM BM_STATUS BM1_DATA_OVRUN [6..6] ====================================== */ 374 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_DATA_OVRUN */ 375 MEC_ESPI_MEM_BM_STATUS_BM1_DATA_OVRUN_ACTV = 1,/*!< ACTV : Status is active */ 376 } MEC_ESPI_MEM_BM_STATUS_BM1_DATA_OVRUN_Enum; 377 378 /* ======================================= MEC_ESPI_MEM BM_STATUS BM1_INCOMPL [7..7] ======================================= */ 379 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_INCOMPL */ 380 MEC_ESPI_MEM_BM_STATUS_BM1_INCOMPL_ACTV = 1, /*!< ACTV : Status is active */ 381 } MEC_ESPI_MEM_BM_STATUS_BM1_INCOMPL_Enum; 382 383 /* ======================================== MEC_ESPI_MEM BM_STATUS BM1_FAIL [8..8] ========================================= */ 384 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_FAIL */ 385 MEC_ESPI_MEM_BM_STATUS_BM1_FAIL_ACTV = 1, /*!< ACTV : Status is active */ 386 } MEC_ESPI_MEM_BM_STATUS_BM1_FAIL_Enum; 387 388 /* ===================================== MEC_ESPI_MEM BM_STATUS BM1_AHB_BUS_ERR [9..9] ===================================== */ 389 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_AHB_BUS_ERR */ 390 MEC_ESPI_MEM_BM_STATUS_BM1_AHB_BUS_ERR_ACTV = 1,/*!< ACTV : Status is active */ 391 } MEC_ESPI_MEM_BM_STATUS_BM1_AHB_BUS_ERR_Enum; 392 393 /* ====================================== MEC_ESPI_MEM BM_STATUS BM1_BAD_REQ [11..11] ====================================== */ 394 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM1_BAD_REQ */ 395 MEC_ESPI_MEM_BM_STATUS_BM1_BAD_REQ_ACTV = 1, /*!< ACTV : Status is active */ 396 } MEC_ESPI_MEM_BM_STATUS_BM1_BAD_REQ_Enum; 397 398 /* ===================================== MEC_ESPI_MEM BM_STATUS BM2_XFR_DONE [16..16] ====================================== */ 399 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_XFR_DONE */ 400 MEC_ESPI_MEM_BM_STATUS_BM2_XFR_DONE_ACTV = 1, /*!< ACTV : Status is active */ 401 } MEC_ESPI_MEM_BM_STATUS_BM2_XFR_DONE_Enum; 402 403 /* ======================================= MEC_ESPI_MEM BM_STATUS BM2_BUSY [17..17] ======================================== */ 404 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_BUSY */ 405 MEC_ESPI_MEM_BM_STATUS_BM2_BUSY_ACTV = 1, /*!< ACTV : Status is active */ 406 } MEC_ESPI_MEM_BM_STATUS_BM2_BUSY_Enum; 407 408 /* ===================================== MEC_ESPI_MEM BM_STATUS BM2_EC_ABORT [18..18] ====================================== */ 409 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_EC_ABORT */ 410 MEC_ESPI_MEM_BM_STATUS_BM2_EC_ABORT_ACTV = 1, /*!< ACTV : Status is active */ 411 } MEC_ESPI_MEM_BM_STATUS_BM2_EC_ABORT_Enum; 412 413 /* ==================================== MEC_ESPI_MEM BM_STATUS BM2_HOST_ABORT [19..19] ===================================== */ 414 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_HOST_ABORT */ 415 MEC_ESPI_MEM_BM_STATUS_BM2_HOST_ABORT_ACTV = 1,/*!< ACTV : Status is active */ 416 } MEC_ESPI_MEM_BM_STATUS_BM2_HOST_ABORT_Enum; 417 418 /* =================================== MEC_ESPI_MEM BM_STATUS BM2_CH1_ERR_ABORT [20..20] =================================== */ 419 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_CH1_ERR_ABORT */ 420 MEC_ESPI_MEM_BM_STATUS_BM2_CH1_ERR_ABORT_ACTV = 1,/*!< ACTV : Status is active */ 421 } MEC_ESPI_MEM_BM_STATUS_BM2_CH1_ERR_ABORT_Enum; 422 423 /* ==================================== MEC_ESPI_MEM BM_STATUS BM2_START_OVRFL [21..21] ==================================== */ 424 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_START_OVRFL */ 425 MEC_ESPI_MEM_BM_STATUS_BM2_START_OVRFL_ACTV = 1,/*!< ACTV : Status is active */ 426 } MEC_ESPI_MEM_BM_STATUS_BM2_START_OVRFL_Enum; 427 428 /* ==================================== MEC_ESPI_MEM BM_STATUS BM2_DATA_OVRUN [22..22] ===================================== */ 429 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_DATA_OVRUN */ 430 MEC_ESPI_MEM_BM_STATUS_BM2_DATA_OVRUN_ACTV = 1,/*!< ACTV : Status is active */ 431 } MEC_ESPI_MEM_BM_STATUS_BM2_DATA_OVRUN_Enum; 432 433 /* ====================================== MEC_ESPI_MEM BM_STATUS BM2_INCOMPL [23..23] ====================================== */ 434 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_INCOMPL */ 435 MEC_ESPI_MEM_BM_STATUS_BM2_INCOMPL_ACTV = 1, /*!< ACTV : Status is active */ 436 } MEC_ESPI_MEM_BM_STATUS_BM2_INCOMPL_Enum; 437 438 /* ======================================= MEC_ESPI_MEM BM_STATUS BM2_FAIL [24..24] ======================================== */ 439 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_FAIL */ 440 MEC_ESPI_MEM_BM_STATUS_BM2_FAIL_ACTV = 1, /*!< ACTV : Status is active */ 441 } MEC_ESPI_MEM_BM_STATUS_BM2_FAIL_Enum; 442 443 /* ==================================== MEC_ESPI_MEM BM_STATUS BM2_AHB_BUS_ERR [25..25] ==================================== */ 444 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_AHB_BUS_ERR */ 445 MEC_ESPI_MEM_BM_STATUS_BM2_AHB_BUS_ERR_ACTV = 1,/*!< ACTV : Status is active */ 446 } MEC_ESPI_MEM_BM_STATUS_BM2_AHB_BUS_ERR_Enum; 447 448 /* ====================================== MEC_ESPI_MEM BM_STATUS BM2_BAD_REQ [27..27] ====================================== */ 449 typedef enum { /*!< MEC_ESPI_MEM_BM_STATUS_BM2_BAD_REQ */ 450 MEC_ESPI_MEM_BM_STATUS_BM2_BAD_REQ_ACTV = 1, /*!< ACTV : Status is active */ 451 } MEC_ESPI_MEM_BM_STATUS_BM2_BAD_REQ_Enum; 452 453 /* ======================================================== BM_IEN ========================================================= */ 454 /* ====================================== MEC_ESPI_MEM BM_IEN BM1_XFR_DONE_IEN [0..0] ====================================== */ 455 typedef enum { /*!< MEC_ESPI_MEM_BM_IEN_BM1_XFR_DONE_IEN */ 456 MEC_ESPI_MEM_BM_IEN_BM1_XFR_DONE_IEN_EN = 1, /*!< EN : Enable */ 457 } MEC_ESPI_MEM_BM_IEN_BM1_XFR_DONE_IEN_Enum; 458 459 /* ===================================== MEC_ESPI_MEM BM_IEN BM2_XFR_DONE_IEN [16..16] ===================================== */ 460 typedef enum { /*!< MEC_ESPI_MEM_BM_IEN_BM2_XFR_DONE_IEN */ 461 MEC_ESPI_MEM_BM_IEN_BM2_XFR_DONE_IEN_EN = 1, /*!< EN : Enable */ 462 } MEC_ESPI_MEM_BM_IEN_BM2_XFR_DONE_IEN_Enum; 463 464 /* ======================================================= BM_CONFIG ======================================================= */ 465 /* ========================================= MEC_ESPI_MEM BM_CONFIG BM1_TAG [0..3] ========================================= */ 466 typedef enum { /*!< MEC_ESPI_MEM_BM_CONFIG_BM1_TAG */ 467 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG0 = 0, /*!< ESPI_TAG0 : eSPI traffic 4-bit TAG 0 */ 468 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG1 = 1, /*!< ESPI_TAG1 : eSPI traffic 4-bit TAG 1 */ 469 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG2 = 2, /*!< ESPI_TAG2 : eSPI traffic 4-bit TAG 2 */ 470 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG3 = 3, /*!< ESPI_TAG3 : eSPI traffic 4-bit TAG 3 */ 471 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG4 = 4, /*!< ESPI_TAG4 : eSPI traffic 4-bit TAG 4 */ 472 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG5 = 5, /*!< ESPI_TAG5 : eSPI traffic 4-bit TAG 5 */ 473 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG6 = 6, /*!< ESPI_TAG6 : eSPI traffic 4-bit TAG 6 */ 474 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG7 = 7, /*!< ESPI_TAG7 : eSPI traffic 4-bit TAG 7 */ 475 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG8 = 8, /*!< ESPI_TAG8 : eSPI traffic 4-bit TAG 8 */ 476 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG9 = 9, /*!< ESPI_TAG9 : eSPI traffic 4-bit TAG 9 */ 477 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG10 = 10,/*!< ESPI_TAG10 : eSPI traffic 4-bit TAG 10 */ 478 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG11 = 11,/*!< ESPI_TAG11 : eSPI traffic 4-bit TAG 11 */ 479 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG12 = 12,/*!< ESPI_TAG12 : eSPI traffic 4-bit TAG 12 */ 480 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG13 = 13,/*!< ESPI_TAG13 : eSPI traffic 4-bit TAG 13 */ 481 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG14 = 14,/*!< ESPI_TAG14 : eSPI traffic 4-bit TAG 14 */ 482 MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_ESPI_TAG15 = 15,/*!< ESPI_TAG15 : eSPI traffic 4-bit TAG 15 */ 483 } MEC_ESPI_MEM_BM_CONFIG_BM1_TAG_Enum; 484 485 /* ======================================== MEC_ESPI_MEM BM_CONFIG BM2_TAG [16..19] ======================================== */ 486 typedef enum { /*!< MEC_ESPI_MEM_BM_CONFIG_BM2_TAG */ 487 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG0 = 0, /*!< ESPI_TAG0 : eSPI traffic 4-bit TAG 0 */ 488 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG1 = 1, /*!< ESPI_TAG1 : eSPI traffic 4-bit TAG 1 */ 489 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG2 = 2, /*!< ESPI_TAG2 : eSPI traffic 4-bit TAG 2 */ 490 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG3 = 3, /*!< ESPI_TAG3 : eSPI traffic 4-bit TAG 3 */ 491 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG4 = 4, /*!< ESPI_TAG4 : eSPI traffic 4-bit TAG 4 */ 492 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG5 = 5, /*!< ESPI_TAG5 : eSPI traffic 4-bit TAG 5 */ 493 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG6 = 6, /*!< ESPI_TAG6 : eSPI traffic 4-bit TAG 6 */ 494 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG7 = 7, /*!< ESPI_TAG7 : eSPI traffic 4-bit TAG 7 */ 495 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG8 = 8, /*!< ESPI_TAG8 : eSPI traffic 4-bit TAG 8 */ 496 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG9 = 9, /*!< ESPI_TAG9 : eSPI traffic 4-bit TAG 9 */ 497 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG10 = 10,/*!< ESPI_TAG10 : eSPI traffic 4-bit TAG 10 */ 498 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG11 = 11,/*!< ESPI_TAG11 : eSPI traffic 4-bit TAG 11 */ 499 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG12 = 12,/*!< ESPI_TAG12 : eSPI traffic 4-bit TAG 12 */ 500 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG13 = 13,/*!< ESPI_TAG13 : eSPI traffic 4-bit TAG 13 */ 501 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG14 = 14,/*!< ESPI_TAG14 : eSPI traffic 4-bit TAG 14 */ 502 MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_ESPI_TAG15 = 15,/*!< ESPI_TAG15 : eSPI traffic 4-bit TAG 15 */ 503 } MEC_ESPI_MEM_BM_CONFIG_BM2_TAG_Enum; 504 505 /* ======================================================= BM_CTRL1 ======================================================== */ 506 /* ========================================== MEC_ESPI_MEM BM_CTRL1 START [0..0] =========================================== */ 507 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL1_START */ 508 MEC_ESPI_MEM_BM_CTRL1_START_EN = 1, /*!< EN : Enable start value */ 509 } MEC_ESPI_MEM_BM_CTRL1_START_Enum; 510 511 /* ========================================== MEC_ESPI_MEM BM_CTRL1 ABORT [1..1] =========================================== */ 512 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL1_ABORT */ 513 MEC_ESPI_MEM_BM_CTRL1_ABORT_EN = 1, /*!< EN : Enable abort value */ 514 } MEC_ESPI_MEM_BM_CTRL1_ABORT_Enum; 515 516 /* ====================================== MEC_ESPI_MEM BM_CTRL1 INCR_AHB_ADDR [2..2] ======================================= */ 517 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL1_INCR_AHB_ADDR */ 518 MEC_ESPI_MEM_BM_CTRL1_INCR_AHB_ADDR_EN = 1, /*!< EN : AHB address increment enable value */ 519 } MEC_ESPI_MEM_BM_CTRL1_INCR_AHB_ADDR_Enum; 520 521 /* ==================================== MEC_ESPI_MEM BM_CTRL1 WAIT_BM2_NOT_BUSY [3..3] ===================================== */ 522 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL1_WAIT_BM2_NOT_BUSY */ 523 MEC_ESPI_MEM_BM_CTRL1_WAIT_BM2_NOT_BUSY_EN = 1,/*!< EN : Wait for BM2 not busy enable value */ 524 } MEC_ESPI_MEM_BM_CTRL1_WAIT_BM2_NOT_BUSY_Enum; 525 526 /* ======================================== MEC_ESPI_MEM BM_CTRL1 CYCLE_TYPE [8..9] ======================================== */ 527 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE */ 528 MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_RD32 = 0, /*!< RD32 : Memory read using 32-bit address */ 529 MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_WR32 = 1, /*!< WR32 : Memory write using 32-bit address */ 530 MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_RD64 = 2, /*!< RD64 : Memory read using 64-bit address */ 531 MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_WR64 = 3, /*!< WR64 : Memory write using 64-bit address */ 532 } MEC_ESPI_MEM_BM_CTRL1_CYCLE_TYPE_Enum; 533 534 /* ===================================================== BM1_HADDR_LSW ===================================================== */ 535 /* ===================================================== BM1_HADDR_MSW ===================================================== */ 536 /* ==================================================== BM1_EC_ADDR_LSW ==================================================== */ 537 /* ==================================================== BM1_EC_ADDR_MSW ==================================================== */ 538 /* ======================================================= BM_CTRL2 ======================================================== */ 539 /* ========================================== MEC_ESPI_MEM BM_CTRL2 START [0..0] =========================================== */ 540 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL2_START */ 541 MEC_ESPI_MEM_BM_CTRL2_START_EN = 1, /*!< EN : Enable start value */ 542 } MEC_ESPI_MEM_BM_CTRL2_START_Enum; 543 544 /* ========================================== MEC_ESPI_MEM BM_CTRL2 ABORT [1..1] =========================================== */ 545 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL2_ABORT */ 546 MEC_ESPI_MEM_BM_CTRL2_ABORT_EN = 1, /*!< EN : Enable abort value */ 547 } MEC_ESPI_MEM_BM_CTRL2_ABORT_Enum; 548 549 /* ====================================== MEC_ESPI_MEM BM_CTRL2 INCR_AHB_ADDR [2..2] ======================================= */ 550 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL2_INCR_AHB_ADDR */ 551 MEC_ESPI_MEM_BM_CTRL2_INCR_AHB_ADDR_EN = 1, /*!< EN : AHB address increment enable value */ 552 } MEC_ESPI_MEM_BM_CTRL2_INCR_AHB_ADDR_Enum; 553 554 /* ==================================== MEC_ESPI_MEM BM_CTRL2 WAIT_BM2_NOT_BUSY [3..3] ===================================== */ 555 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL2_WAIT_BM2_NOT_BUSY */ 556 MEC_ESPI_MEM_BM_CTRL2_WAIT_BM2_NOT_BUSY_EN = 1,/*!< EN : Wait for BM2 not busy enable value */ 557 } MEC_ESPI_MEM_BM_CTRL2_WAIT_BM2_NOT_BUSY_Enum; 558 559 /* ======================================== MEC_ESPI_MEM BM_CTRL2 CYCLE_TYPE [8..9] ======================================== */ 560 typedef enum { /*!< MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE */ 561 MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_RD32 = 0, /*!< RD32 : Memory read using 32-bit address */ 562 MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_WR32 = 1, /*!< WR32 : Memory write using 32-bit address */ 563 MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_RD64 = 2, /*!< RD64 : Memory read using 64-bit address */ 564 MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_WR64 = 3, /*!< WR64 : Memory write using 64-bit address */ 565 } MEC_ESPI_MEM_BM_CTRL2_CYCLE_TYPE_Enum; 566 567 /** @} */ /* End of group EnumValue_peripherals */ 568 569 #endif /* _MEC5_ESPI_MEM_V1_4_H */ 570
