1 /**************************************************************************//**
2 * @file cmsis_iccarm.h
3 * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file
4 * @version V5.2.0
5 * @date 28. January 2020
6 ******************************************************************************/
7
8 //------------------------------------------------------------------------------
9 //
10 // Copyright (c) 2017-2020 IAR Systems
11 // Copyright (c) 2017-2019 Arm Limited. All rights reserved.
12 //
13 // SPDX-License-Identifier: Apache-2.0
14 //
15 // Licensed under the Apache License, Version 2.0 (the "License")
16 // you may not use this file except in compliance with the License.
17 // You may obtain a copy of the License at
18 // http://www.apache.org/licenses/LICENSE-2.0
19 //
20 // Unless required by applicable law or agreed to in writing, software
21 // distributed under the License is distributed on an "AS IS" BASIS,
22 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 // See the License for the specific language governing permissions and
24 // limitations under the License.
25 //
26 //------------------------------------------------------------------------------
27
28
29 #ifndef __CMSIS_ICCARM_H__
30 #define __CMSIS_ICCARM_H__
31
32 #ifndef __ICCARM__
33 #error This file should only be compiled by ICCARM
34 #endif
35
36 #pragma system_include
37
38 #define __IAR_FT _Pragma("inline=forced") __intrinsic
39
40 #if (__VER__ >= 8000000)
41 #define __ICCARM_V8 1
42 #else
43 #define __ICCARM_V8 0
44 #endif
45
46 #ifndef __ALIGNED
47 #if __ICCARM_V8
48 #define __ALIGNED(x) __attribute__((aligned(x)))
49 #elif (__VER__ >= 7080000)
50 /* Needs IAR language extensions */
51 #define __ALIGNED(x) __attribute__((aligned(x)))
52 #else
53 #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
54 #define __ALIGNED(x)
55 #endif
56 #endif
57
58
59 /* Define compiler macros for CPU architecture, used in CMSIS 5.
60 */
61 #if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
62 /* Macros already defined */
63 #else
64 #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
65 #define __ARM_ARCH_8M_MAIN__ 1
66 #elif defined(__ARM8M_BASELINE__)
67 #define __ARM_ARCH_8M_BASE__ 1
68 #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
69 #if __ARM_ARCH == 6
70 #define __ARM_ARCH_6M__ 1
71 #elif __ARM_ARCH == 7
72 #if __ARM_FEATURE_DSP
73 #define __ARM_ARCH_7EM__ 1
74 #else
75 #define __ARM_ARCH_7M__ 1
76 #endif
77 #endif /* __ARM_ARCH */
78 #endif /* __ARM_ARCH_PROFILE == 'M' */
79 #endif
80
81 /* Alternativ core deduction for older ICCARM's */
82 #if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
83 !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
84 #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
85 #define __ARM_ARCH_6M__ 1
86 #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
87 #define __ARM_ARCH_7M__ 1
88 #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
89 #define __ARM_ARCH_7EM__ 1
90 #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
91 #define __ARM_ARCH_8M_BASE__ 1
92 #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
93 #define __ARM_ARCH_8M_MAIN__ 1
94 #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
95 #define __ARM_ARCH_8M_MAIN__ 1
96 #else
97 #error "Unknown target."
98 #endif
99 #endif
100
101
102
103 #if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
104 #define __IAR_M0_FAMILY 1
105 #elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
106 #define __IAR_M0_FAMILY 1
107 #else
108 #define __IAR_M0_FAMILY 0
109 #endif
110
111
112 #ifndef __ASM
113 #define __ASM __asm
114 #endif
115
116 #ifndef __COMPILER_BARRIER
117 #define __COMPILER_BARRIER() __ASM volatile("":::"memory")
118 #endif
119
120 #ifndef __INLINE
121 #define __INLINE inline
122 #endif
123
124 #ifndef __NO_RETURN
125 #if __ICCARM_V8
126 #define __NO_RETURN __attribute__((__noreturn__))
127 #else
128 #define __NO_RETURN _Pragma("object_attribute=__noreturn")
129 #endif
130 #endif
131
132 #ifndef __PACKED
133 #if __ICCARM_V8
134 #define __PACKED __attribute__((packed, aligned(1)))
135 #else
136 /* Needs IAR language extensions */
137 #define __PACKED __packed
138 #endif
139 #endif
140
141 #ifndef __PACKED_STRUCT
142 #if __ICCARM_V8
143 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
144 #else
145 /* Needs IAR language extensions */
146 #define __PACKED_STRUCT __packed struct
147 #endif
148 #endif
149
150 #ifndef __PACKED_UNION
151 #if __ICCARM_V8
152 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
153 #else
154 /* Needs IAR language extensions */
155 #define __PACKED_UNION __packed union
156 #endif
157 #endif
158
159 #ifndef __RESTRICT
160 #if __ICCARM_V8
161 #define __RESTRICT __restrict
162 #else
163 /* Needs IAR language extensions */
164 #define __RESTRICT restrict
165 #endif
166 #endif
167
168 #ifndef __STATIC_INLINE
169 #define __STATIC_INLINE static inline
170 #endif
171
172 #ifndef __FORCEINLINE
173 #define __FORCEINLINE _Pragma("inline=forced")
174 #endif
175
176 #ifndef __STATIC_FORCEINLINE
177 #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE
178 #endif
179
180 #ifndef __UNALIGNED_UINT16_READ
181 #pragma language=save
182 #pragma language=extended
__iar_uint16_read(void const * ptr)183 __IAR_FT uint16_t __iar_uint16_read(void const *ptr)
184 {
185 return *(__packed uint16_t*)(ptr);
186 }
187 #pragma language=restore
188 #define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
189 #endif
190
191
192 #ifndef __UNALIGNED_UINT16_WRITE
193 #pragma language=save
194 #pragma language=extended
__iar_uint16_write(void const * ptr,uint16_t val)195 __IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
196 {
197 *(__packed uint16_t*)(ptr) = val;;
198 }
199 #pragma language=restore
200 #define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
201 #endif
202
203 #ifndef __UNALIGNED_UINT32_READ
204 #pragma language=save
205 #pragma language=extended
__iar_uint32_read(void const * ptr)206 __IAR_FT uint32_t __iar_uint32_read(void const *ptr)
207 {
208 return *(__packed uint32_t*)(ptr);
209 }
210 #pragma language=restore
211 #define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
212 #endif
213
214 #ifndef __UNALIGNED_UINT32_WRITE
215 #pragma language=save
216 #pragma language=extended
__iar_uint32_write(void const * ptr,uint32_t val)217 __IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
218 {
219 *(__packed uint32_t*)(ptr) = val;;
220 }
221 #pragma language=restore
222 #define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
223 #endif
224
225 #ifndef __UNALIGNED_UINT32 /* deprecated */
226 #pragma language=save
227 #pragma language=extended
228 __packed struct __iar_u32 { uint32_t v; };
229 #pragma language=restore
230 #define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
231 #endif
232
233 #ifndef __USED
234 #if __ICCARM_V8
235 #define __USED __attribute__((used))
236 #else
237 #define __USED _Pragma("__root")
238 #endif
239 #endif
240
241 #undef __WEAK /* undo the definition from DLib_Defaults.h */
242 #ifndef __WEAK
243 #if __ICCARM_V8
244 #define __WEAK __attribute__((weak))
245 #else
246 #define __WEAK _Pragma("__weak")
247 #endif
248 #endif
249
250 #ifndef __PROGRAM_START
251 #define __PROGRAM_START __iar_program_start
252 #endif
253
254 #ifndef __INITIAL_SP
255 #define __INITIAL_SP CSTACK$$Limit
256 #endif
257
258 #ifndef __STACK_LIMIT
259 #define __STACK_LIMIT CSTACK$$Base
260 #endif
261
262 #ifndef __VECTOR_TABLE
263 #define __VECTOR_TABLE __vector_table
264 #endif
265
266 #ifndef __VECTOR_TABLE_ATTRIBUTE
267 #define __VECTOR_TABLE_ATTRIBUTE @".intvec"
268 #endif
269
270 #ifndef __ICCARM_INTRINSICS_VERSION__
271 #define __ICCARM_INTRINSICS_VERSION__ 0
272 #endif
273
274 #if __ICCARM_INTRINSICS_VERSION__ == 2
275
276 #if defined(__CLZ)
277 #undef __CLZ
278 #endif
279 #if defined(__REVSH)
280 #undef __REVSH
281 #endif
282 #if defined(__RBIT)
283 #undef __RBIT
284 #endif
285 #if defined(__SSAT)
286 #undef __SSAT
287 #endif
288 #if defined(__USAT)
289 #undef __USAT
290 #endif
291
292 #include "iccarm_builtin.h"
293
294 #define __disable_fault_irq __iar_builtin_disable_fiq
295 #define __disable_irq __iar_builtin_disable_interrupt
296 #define __enable_fault_irq __iar_builtin_enable_fiq
297 #define __enable_irq __iar_builtin_enable_interrupt
298 #define __arm_rsr __iar_builtin_rsr
299 #define __arm_wsr __iar_builtin_wsr
300
301
302 #define __get_APSR() (__arm_rsr("APSR"))
303 #define __get_BASEPRI() (__arm_rsr("BASEPRI"))
304 #define __get_CONTROL() (__arm_rsr("CONTROL"))
305 #define __get_FAULTMASK() (__arm_rsr("FAULTMASK"))
306
307 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
308 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
309 #define __get_FPSCR() (__arm_rsr("FPSCR"))
310 #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE)))
311 #else
312 #define __get_FPSCR() ( 0 )
313 #define __set_FPSCR(VALUE) ((void)VALUE)
314 #endif
315
316 #define __get_IPSR() (__arm_rsr("IPSR"))
317 #define __get_MSP() (__arm_rsr("MSP"))
318 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
319 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
320 // without main extensions, the non-secure MSPLIM is RAZ/WI
321 #define __get_MSPLIM() (0U)
322 #else
323 #define __get_MSPLIM() (__arm_rsr("MSPLIM"))
324 #endif
325 #define __get_PRIMASK() (__arm_rsr("PRIMASK"))
326 #define __get_PSP() (__arm_rsr("PSP"))
327
328 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
329 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
330 // without main extensions, the non-secure PSPLIM is RAZ/WI
331 #define __get_PSPLIM() (0U)
332 #else
333 #define __get_PSPLIM() (__arm_rsr("PSPLIM"))
334 #endif
335
336 #define __get_xPSR() (__arm_rsr("xPSR"))
337
338 #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE)))
339 #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE)))
340 #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE)))
341 #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE)))
342 #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE)))
343
344 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
345 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
346 // without main extensions, the non-secure MSPLIM is RAZ/WI
347 #define __set_MSPLIM(VALUE) ((void)(VALUE))
348 #else
349 #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE)))
350 #endif
351 #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE)))
352 #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE)))
353 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
354 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
355 // without main extensions, the non-secure PSPLIM is RAZ/WI
356 #define __set_PSPLIM(VALUE) ((void)(VALUE))
357 #else
358 #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE)))
359 #endif
360
361 #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS"))
362 #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE)))
363 #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS"))
364 #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE)))
365 #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS"))
366 #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE)))
367 #define __TZ_get_SP_NS() (__arm_rsr("SP_NS"))
368 #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE)))
369 #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS"))
370 #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE)))
371 #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS"))
372 #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE)))
373 #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS"))
374 #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
375
376 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
377 (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
378 // without main extensions, the non-secure PSPLIM is RAZ/WI
379 #define __TZ_get_PSPLIM_NS() (0U)
380 #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
381 #else
382 #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS"))
383 #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
384 #endif
385
386 #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS"))
387 #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE)))
388
389 #define __NOP __iar_builtin_no_operation
390
391 #define __CLZ __iar_builtin_CLZ
392 #define __CLREX __iar_builtin_CLREX
393
394 #define __DMB __iar_builtin_DMB
395 #define __DSB __iar_builtin_DSB
396 #define __ISB __iar_builtin_ISB
397
398 #define __LDREXB __iar_builtin_LDREXB
399 #define __LDREXH __iar_builtin_LDREXH
400 #define __LDREXW __iar_builtin_LDREX
401
402 #define __RBIT __iar_builtin_RBIT
403 #define __REV __iar_builtin_REV
404 #define __REV16 __iar_builtin_REV16
405
__REVSH(int16_t val)406 __IAR_FT int16_t __REVSH(int16_t val)
407 {
408 return (int16_t) __iar_builtin_REVSH(val);
409 }
410
411 #define __ROR __iar_builtin_ROR
412 #define __RRX __iar_builtin_RRX
413
414 #define __SEV __iar_builtin_SEV
415
416 #if !__IAR_M0_FAMILY
417 #define __SSAT __iar_builtin_SSAT
418 #endif
419
420 #define __STREXB __iar_builtin_STREXB
421 #define __STREXH __iar_builtin_STREXH
422 #define __STREXW __iar_builtin_STREX
423
424 #if !__IAR_M0_FAMILY
425 #define __USAT __iar_builtin_USAT
426 #endif
427
428 #define __WFE __iar_builtin_WFE
429 #define __WFI __iar_builtin_WFI
430
431 #if __ARM_MEDIA__
432 #define __SADD8 __iar_builtin_SADD8
433 #define __QADD8 __iar_builtin_QADD8
434 #define __SHADD8 __iar_builtin_SHADD8
435 #define __UADD8 __iar_builtin_UADD8
436 #define __UQADD8 __iar_builtin_UQADD8
437 #define __UHADD8 __iar_builtin_UHADD8
438 #define __SSUB8 __iar_builtin_SSUB8
439 #define __QSUB8 __iar_builtin_QSUB8
440 #define __SHSUB8 __iar_builtin_SHSUB8
441 #define __USUB8 __iar_builtin_USUB8
442 #define __UQSUB8 __iar_builtin_UQSUB8
443 #define __UHSUB8 __iar_builtin_UHSUB8
444 #define __SADD16 __iar_builtin_SADD16
445 #define __QADD16 __iar_builtin_QADD16
446 #define __SHADD16 __iar_builtin_SHADD16
447 #define __UADD16 __iar_builtin_UADD16
448 #define __UQADD16 __iar_builtin_UQADD16
449 #define __UHADD16 __iar_builtin_UHADD16
450 #define __SSUB16 __iar_builtin_SSUB16
451 #define __QSUB16 __iar_builtin_QSUB16
452 #define __SHSUB16 __iar_builtin_SHSUB16
453 #define __USUB16 __iar_builtin_USUB16
454 #define __UQSUB16 __iar_builtin_UQSUB16
455 #define __UHSUB16 __iar_builtin_UHSUB16
456 #define __SASX __iar_builtin_SASX
457 #define __QASX __iar_builtin_QASX
458 #define __SHASX __iar_builtin_SHASX
459 #define __UASX __iar_builtin_UASX
460 #define __UQASX __iar_builtin_UQASX
461 #define __UHASX __iar_builtin_UHASX
462 #define __SSAX __iar_builtin_SSAX
463 #define __QSAX __iar_builtin_QSAX
464 #define __SHSAX __iar_builtin_SHSAX
465 #define __USAX __iar_builtin_USAX
466 #define __UQSAX __iar_builtin_UQSAX
467 #define __UHSAX __iar_builtin_UHSAX
468 #define __USAD8 __iar_builtin_USAD8
469 #define __USADA8 __iar_builtin_USADA8
470 #define __SSAT16 __iar_builtin_SSAT16
471 #define __USAT16 __iar_builtin_USAT16
472 #define __UXTB16 __iar_builtin_UXTB16
473 #define __UXTAB16 __iar_builtin_UXTAB16
474 #define __SXTB16 __iar_builtin_SXTB16
475 #define __SXTAB16 __iar_builtin_SXTAB16
476 #define __SMUAD __iar_builtin_SMUAD
477 #define __SMUADX __iar_builtin_SMUADX
478 #define __SMMLA __iar_builtin_SMMLA
479 #define __SMLAD __iar_builtin_SMLAD
480 #define __SMLADX __iar_builtin_SMLADX
481 #define __SMLALD __iar_builtin_SMLALD
482 #define __SMLALDX __iar_builtin_SMLALDX
483 #define __SMUSD __iar_builtin_SMUSD
484 #define __SMUSDX __iar_builtin_SMUSDX
485 #define __SMLSD __iar_builtin_SMLSD
486 #define __SMLSDX __iar_builtin_SMLSDX
487 #define __SMLSLD __iar_builtin_SMLSLD
488 #define __SMLSLDX __iar_builtin_SMLSLDX
489 #define __SEL __iar_builtin_SEL
490 #define __QADD __iar_builtin_QADD
491 #define __QSUB __iar_builtin_QSUB
492 #define __PKHBT __iar_builtin_PKHBT
493 #define __PKHTB __iar_builtin_PKHTB
494 #endif
495
496 #else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
497
498 #if __IAR_M0_FAMILY
499 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
500 #define __CLZ __cmsis_iar_clz_not_active
501 #define __SSAT __cmsis_iar_ssat_not_active
502 #define __USAT __cmsis_iar_usat_not_active
503 #define __RBIT __cmsis_iar_rbit_not_active
504 #define __get_APSR __cmsis_iar_get_APSR_not_active
505 #endif
506
507
508 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
509 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
510 #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
511 #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
512 #endif
513
514 #ifdef __INTRINSICS_INCLUDED
515 #error intrinsics.h is already included previously!
516 #endif
517
518 #include <intrinsics.h>
519
520 #if __IAR_M0_FAMILY
521 /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
522 #undef __CLZ
523 #undef __SSAT
524 #undef __USAT
525 #undef __RBIT
526 #undef __get_APSR
527
__CLZ(uint32_t data)528 __STATIC_INLINE uint8_t __CLZ(uint32_t data)
529 {
530 if (data == 0U) { return 32U; }
531
532 uint32_t count = 0U;
533 uint32_t mask = 0x80000000U;
534
535 while ((data & mask) == 0U)
536 {
537 count += 1U;
538 mask = mask >> 1U;
539 }
540 return count;
541 }
542
__RBIT(uint32_t v)543 __STATIC_INLINE uint32_t __RBIT(uint32_t v)
544 {
545 uint8_t sc = 31U;
546 uint32_t r = v;
547 for (v >>= 1U; v; v >>= 1U)
548 {
549 r <<= 1U;
550 r |= v & 1U;
551 sc--;
552 }
553 return (r << sc);
554 }
555
__get_APSR(void)556 __STATIC_INLINE uint32_t __get_APSR(void)
557 {
558 uint32_t res;
559 __asm("MRS %0,APSR" : "=r" (res));
560 return res;
561 }
562
563 #endif
564
565 #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
566 (defined (__FPU_USED ) && (__FPU_USED == 1U)) ))
567 #undef __get_FPSCR
568 #undef __set_FPSCR
569 #define __get_FPSCR() (0)
570 #define __set_FPSCR(VALUE) ((void)VALUE)
571 #endif
572
573 #pragma diag_suppress=Pe940
574 #pragma diag_suppress=Pe177
575
576 #define __enable_irq __enable_interrupt
577 #define __disable_irq __disable_interrupt
578 #define __NOP __no_operation
579
580 #define __get_xPSR __get_PSR
581
582 #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
583
__LDREXW(uint32_t volatile * ptr)584 __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
585 {
586 return __LDREX((unsigned long *)ptr);
587 }
588
__STREXW(uint32_t value,uint32_t volatile * ptr)589 __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
590 {
591 return __STREX(value, (unsigned long *)ptr);
592 }
593 #endif
594
595
596 /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
597 #if (__CORTEX_M >= 0x03)
598
__RRX(uint32_t value)599 __IAR_FT uint32_t __RRX(uint32_t value)
600 {
601 uint32_t result;
602 __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value));
603 return(result);
604 }
605
__set_BASEPRI_MAX(uint32_t value)606 __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
607 {
608 __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value));
609 }
610
611
612 #define __enable_fault_irq __enable_fiq
613 #define __disable_fault_irq __disable_fiq
614
615
616 #endif /* (__CORTEX_M >= 0x03) */
617
__ROR(uint32_t op1,uint32_t op2)618 __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
619 {
620 return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
621 }
622
623 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
624 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
625
__get_MSPLIM(void)626 __IAR_FT uint32_t __get_MSPLIM(void)
627 {
628 uint32_t res;
629 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
630 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
631 // without main extensions, the non-secure MSPLIM is RAZ/WI
632 res = 0U;
633 #else
634 __asm volatile("MRS %0,MSPLIM" : "=r" (res));
635 #endif
636 return res;
637 }
638
__set_MSPLIM(uint32_t value)639 __IAR_FT void __set_MSPLIM(uint32_t value)
640 {
641 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
642 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
643 // without main extensions, the non-secure MSPLIM is RAZ/WI
644 (void)value;
645 #else
646 __asm volatile("MSR MSPLIM,%0" :: "r" (value));
647 #endif
648 }
649
__get_PSPLIM(void)650 __IAR_FT uint32_t __get_PSPLIM(void)
651 {
652 uint32_t res;
653 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
654 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
655 // without main extensions, the non-secure PSPLIM is RAZ/WI
656 res = 0U;
657 #else
658 __asm volatile("MRS %0,PSPLIM" : "=r" (res));
659 #endif
660 return res;
661 }
662
__set_PSPLIM(uint32_t value)663 __IAR_FT void __set_PSPLIM(uint32_t value)
664 {
665 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
666 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
667 // without main extensions, the non-secure PSPLIM is RAZ/WI
668 (void)value;
669 #else
670 __asm volatile("MSR PSPLIM,%0" :: "r" (value));
671 #endif
672 }
673
__TZ_get_CONTROL_NS(void)674 __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
675 {
676 uint32_t res;
677 __asm volatile("MRS %0,CONTROL_NS" : "=r" (res));
678 return res;
679 }
680
__TZ_set_CONTROL_NS(uint32_t value)681 __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value)
682 {
683 __asm volatile("MSR CONTROL_NS,%0" :: "r" (value));
684 }
685
__TZ_get_PSP_NS(void)686 __IAR_FT uint32_t __TZ_get_PSP_NS(void)
687 {
688 uint32_t res;
689 __asm volatile("MRS %0,PSP_NS" : "=r" (res));
690 return res;
691 }
692
__TZ_set_PSP_NS(uint32_t value)693 __IAR_FT void __TZ_set_PSP_NS(uint32_t value)
694 {
695 __asm volatile("MSR PSP_NS,%0" :: "r" (value));
696 }
697
__TZ_get_MSP_NS(void)698 __IAR_FT uint32_t __TZ_get_MSP_NS(void)
699 {
700 uint32_t res;
701 __asm volatile("MRS %0,MSP_NS" : "=r" (res));
702 return res;
703 }
704
__TZ_set_MSP_NS(uint32_t value)705 __IAR_FT void __TZ_set_MSP_NS(uint32_t value)
706 {
707 __asm volatile("MSR MSP_NS,%0" :: "r" (value));
708 }
709
__TZ_get_SP_NS(void)710 __IAR_FT uint32_t __TZ_get_SP_NS(void)
711 {
712 uint32_t res;
713 __asm volatile("MRS %0,SP_NS" : "=r" (res));
714 return res;
715 }
__TZ_set_SP_NS(uint32_t value)716 __IAR_FT void __TZ_set_SP_NS(uint32_t value)
717 {
718 __asm volatile("MSR SP_NS,%0" :: "r" (value));
719 }
720
__TZ_get_PRIMASK_NS(void)721 __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void)
722 {
723 uint32_t res;
724 __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res));
725 return res;
726 }
727
__TZ_set_PRIMASK_NS(uint32_t value)728 __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value)
729 {
730 __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value));
731 }
732
__TZ_get_BASEPRI_NS(void)733 __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void)
734 {
735 uint32_t res;
736 __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res));
737 return res;
738 }
739
__TZ_set_BASEPRI_NS(uint32_t value)740 __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value)
741 {
742 __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value));
743 }
744
__TZ_get_FAULTMASK_NS(void)745 __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void)
746 {
747 uint32_t res;
748 __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res));
749 return res;
750 }
751
__TZ_set_FAULTMASK_NS(uint32_t value)752 __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value)
753 {
754 __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value));
755 }
756
__TZ_get_PSPLIM_NS(void)757 __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void)
758 {
759 uint32_t res;
760 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
761 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
762 // without main extensions, the non-secure PSPLIM is RAZ/WI
763 res = 0U;
764 #else
765 __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res));
766 #endif
767 return res;
768 }
769
__TZ_set_PSPLIM_NS(uint32_t value)770 __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value)
771 {
772 #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
773 (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)))
774 // without main extensions, the non-secure PSPLIM is RAZ/WI
775 (void)value;
776 #else
777 __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value));
778 #endif
779 }
780
__TZ_get_MSPLIM_NS(void)781 __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void)
782 {
783 uint32_t res;
784 __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res));
785 return res;
786 }
787
__TZ_set_MSPLIM_NS(uint32_t value)788 __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value)
789 {
790 __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value));
791 }
792
793 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
794
795 #endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */
796
797 #define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value))
798
799 #if __IAR_M0_FAMILY
__SSAT(int32_t val,uint32_t sat)800 __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
801 {
802 if ((sat >= 1U) && (sat <= 32U))
803 {
804 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
805 const int32_t min = -1 - max ;
806 if (val > max)
807 {
808 return max;
809 }
810 else if (val < min)
811 {
812 return min;
813 }
814 }
815 return val;
816 }
817
__USAT(int32_t val,uint32_t sat)818 __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
819 {
820 if (sat <= 31U)
821 {
822 const uint32_t max = ((1U << sat) - 1U);
823 if (val > (int32_t)max)
824 {
825 return max;
826 }
827 else if (val < 0)
828 {
829 return 0U;
830 }
831 }
832 return (uint32_t)val;
833 }
834 #endif
835
836 #if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
837
__LDRBT(volatile uint8_t * addr)838 __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
839 {
840 uint32_t res;
841 __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
842 return ((uint8_t)res);
843 }
844
__LDRHT(volatile uint16_t * addr)845 __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
846 {
847 uint32_t res;
848 __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
849 return ((uint16_t)res);
850 }
851
__LDRT(volatile uint32_t * addr)852 __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
853 {
854 uint32_t res;
855 __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
856 return res;
857 }
858
__STRBT(uint8_t value,volatile uint8_t * addr)859 __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
860 {
861 __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
862 }
863
__STRHT(uint16_t value,volatile uint16_t * addr)864 __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
865 {
866 __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
867 }
868
__STRT(uint32_t value,volatile uint32_t * addr)869 __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
870 {
871 __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
872 }
873
874 #endif /* (__CORTEX_M >= 0x03) */
875
876 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
877 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
878
879
__LDAB(volatile uint8_t * ptr)880 __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
881 {
882 uint32_t res;
883 __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
884 return ((uint8_t)res);
885 }
886
__LDAH(volatile uint16_t * ptr)887 __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
888 {
889 uint32_t res;
890 __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
891 return ((uint16_t)res);
892 }
893
__LDA(volatile uint32_t * ptr)894 __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
895 {
896 uint32_t res;
897 __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
898 return res;
899 }
900
__STLB(uint8_t value,volatile uint8_t * ptr)901 __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
902 {
903 __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
904 }
905
__STLH(uint16_t value,volatile uint16_t * ptr)906 __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
907 {
908 __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
909 }
910
__STL(uint32_t value,volatile uint32_t * ptr)911 __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
912 {
913 __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
914 }
915
__LDAEXB(volatile uint8_t * ptr)916 __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
917 {
918 uint32_t res;
919 __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
920 return ((uint8_t)res);
921 }
922
__LDAEXH(volatile uint16_t * ptr)923 __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
924 {
925 uint32_t res;
926 __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
927 return ((uint16_t)res);
928 }
929
__LDAEX(volatile uint32_t * ptr)930 __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
931 {
932 uint32_t res;
933 __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
934 return res;
935 }
936
__STLEXB(uint8_t value,volatile uint8_t * ptr)937 __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
938 {
939 uint32_t res;
940 __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
941 return res;
942 }
943
__STLEXH(uint16_t value,volatile uint16_t * ptr)944 __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
945 {
946 uint32_t res;
947 __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
948 return res;
949 }
950
__STLEX(uint32_t value,volatile uint32_t * ptr)951 __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
952 {
953 uint32_t res;
954 __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
955 return res;
956 }
957
958 #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
959
960 #undef __IAR_FT
961 #undef __IAR_M0_FAMILY
962 #undef __ICCARM_V8
963
964 #pragma diag_default=Pe940
965 #pragma diag_default=Pe177
966
967 #define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
968
969 #endif /* __CMSIS_ICCARM_H__ */
970
