1 /* 2 * Copyright (c) 2017 Nordic Semiconductor ASA 3 * Copyright (c) 2023 Arm Limited 4 * 5 * SPDX-License-Identifier: Apache-2.0 6 */ 7 8 /** 9 * @file 10 * @brief CMSIS interface file 11 * 12 * This header populates the default values required to configure the 13 * ARM CMSIS Core headers. 14 */ 15 16 #ifndef ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ 17 #define ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ 18 19 #include <zephyr/arch/arm/cortex_m/nvic.h> 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /* Fill in CMSIS required values for non-CMSIS compliant SoCs. 26 * Use __NVIC_PRIO_BITS as it is required and simple to check, but 27 * ultimately all SoCs will define their own CMSIS types and constants. 28 */ 29 #ifndef __NVIC_PRIO_BITS 30 typedef enum { 31 Reset_IRQn = -15, 32 NonMaskableInt_IRQn = -14, 33 HardFault_IRQn = -13, 34 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE) 35 MemoryManagement_IRQn = -12, 36 BusFault_IRQn = -11, 37 UsageFault_IRQn = -10, 38 #if defined(CONFIG_ARM_SECURE_FIRMWARE) 39 SecureFault_IRQn = -9, 40 #endif /* CONFIG_ARM_SECURE_FIRMWARE */ 41 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */ 42 SVCall_IRQn = -5, 43 DebugMonitor_IRQn = -4, 44 PendSV_IRQn = -2, 45 SysTick_IRQn = -1, 46 Max_IRQn = CONFIG_NUM_IRQS, 47 } IRQn_Type; 48 49 #if defined(CONFIG_CPU_CORTEX_M0) 50 #define __CM0_REV 0 51 #elif defined(CONFIG_CPU_CORTEX_M0PLUS) 52 #define __CM0PLUS_REV 0 53 #elif defined(CONFIG_CPU_CORTEX_M1) 54 #define __CM1_REV 0 55 #elif defined(CONFIG_CPU_CORTEX_M3) 56 #define __CM3_REV 0 57 #elif defined(CONFIG_CPU_CORTEX_M4) 58 #define __CM4_REV 0 59 #elif defined(CONFIG_CPU_CORTEX_M7) 60 #define __CM7_REV 0 61 #elif defined(CONFIG_CPU_CORTEX_M23) 62 #define __CM23_REV 0 63 #elif defined(CONFIG_CPU_CORTEX_M33) 64 #define __CM33_REV 0 65 #elif defined(CONFIG_CPU_CORTEX_M55) 66 #define __CM55_REV 0 67 #elif defined(CONFIG_CPU_CORTEX_M85) 68 #define __CM85_REV 0 69 #else 70 #error "Unknown Cortex-M device" 71 #endif 72 73 #define __NVIC_PRIO_BITS NUM_IRQ_PRIO_BITS 74 #define __Vendor_SysTickConfig 0 /* Default to standard SysTick */ 75 #endif /* __NVIC_PRIO_BITS */ 76 77 #ifndef __MPU_PRESENT 78 #define __MPU_PRESENT CONFIG_CPU_HAS_ARM_MPU 79 #endif 80 81 #ifndef __FPU_PRESENT 82 #define __FPU_PRESENT CONFIG_CPU_HAS_FPU 83 #endif 84 85 #ifndef __FPU_DP 86 #define __FPU_DP CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION 87 #endif 88 89 #ifndef __VTOR_PRESENT 90 #define __VTOR_PRESENT CONFIG_CPU_CORTEX_M_HAS_VTOR 91 #endif 92 93 #ifndef __DSP_PRESENT 94 #define __DSP_PRESENT CONFIG_ARMV8_M_DSP 95 #endif 96 97 #ifndef __ICACHE_PRESENT 98 #define __ICACHE_PRESENT CONFIG_CPU_HAS_ICACHE 99 #endif 100 101 #ifndef __DCACHE_PRESENT 102 #define __DCACHE_PRESENT CONFIG_CPU_HAS_DCACHE 103 #endif 104 105 #ifndef __MVE_PRESENT 106 #define __MVE_PRESENT CONFIG_ARMV8_1_M_MVEI 107 #endif 108 109 #ifndef __SAUREGION_PRESENT 110 #define __SAUREGION_PRESENT CONFIG_CPU_HAS_ARM_SAU 111 #endif 112 113 #ifndef __PMU_PRESENT 114 #define __PMU_PRESENT CONFIG_ARMV8_1_M_PMU 115 #define __PMU_NUM_EVENTCNT CONFIG_ARMV8_1_M_PMU_EVENTCNT 116 #endif 117 118 #ifdef __cplusplus 119 } 120 #endif 121 122 #if defined(CONFIG_CPU_CORTEX_M0) 123 #include <core_cm0.h> 124 #elif defined(CONFIG_CPU_CORTEX_M0PLUS) 125 #include <core_cm0plus.h> 126 #elif defined(CONFIG_CPU_CORTEX_M1) 127 #include <core_cm1.h> 128 #elif defined(CONFIG_CPU_CORTEX_M3) 129 #include <core_cm3.h> 130 #elif defined(CONFIG_CPU_CORTEX_M4) 131 #include <core_cm4.h> 132 #elif defined(CONFIG_CPU_CORTEX_M7) 133 #include <core_cm7.h> 134 #elif defined(CONFIG_CPU_CORTEX_M23) 135 #include <core_cm23.h> 136 #elif defined(CONFIG_CPU_CORTEX_M33) 137 #include <core_cm33.h> 138 #elif defined(CONFIG_CPU_CORTEX_M55) 139 #include <core_cm55.h> 140 #elif defined(CONFIG_CPU_CORTEX_M85) 141 #include <core_cm85.h> 142 #else 143 #error "Unknown Cortex-M device" 144 #endif 145 146 #endif /* ZEPHYR_MODULES_CMSIS_CMSIS_M_DEFAULTS_H_ */ 147
