1 /*
2  *
3  * Copyright (c) 2018 Ilya Tagunov
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
16 #include "clock_stm32_ll_common.h"
17 
18 #if defined(STM32_PLL_ENABLED)
19 
20 /* Macros to fill up multiplication and division factors values */
21 #define z_pll_mul(v) LL_RCC_PLL_MUL_ ## v
22 #define pll_mul(v) z_pll_mul(v)
23 
24 #define z_pll_div(v) LL_RCC_PLL_DIV_ ## v
25 #define pll_div(v) z_pll_div(v)
26 
27 /**
28  * @brief Return PLL source
29  */
30 __unused
get_pll_source(void)31 static uint32_t get_pll_source(void)
32 {
33 	/* Configure PLL source */
34 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
35 		return LL_RCC_PLLSOURCE_HSI;
36 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
37 		return LL_RCC_PLLSOURCE_HSE;
38 	}
39 
40 	__ASSERT(0, "Invalid source");
41 	return 0;
42 }
43 
44 /**
45  * @brief get the pll source frequency
46  */
47 __unused
get_pllsrc_frequency(void)48 uint32_t get_pllsrc_frequency(void)
49 {
50 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
51 		return STM32_HSI_FREQ;
52 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
53 		return STM32_HSE_FREQ;
54 	}
55 
56 	__ASSERT(0, "Invalid source");
57 	return 0;
58 }
59 
60 /**
61  * @brief Set up pll configuration
62  */
63 __unused
config_pll_sysclock(void)64 void config_pll_sysclock(void)
65 {
66 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
67 				    pll_mul(STM32_PLL_MULTIPLIER),
68 				    pll_div(STM32_PLL_DIVISOR));
69 }
70 
71 /**
72  * @brief Return pllout frequency
73  */
74 __unused
get_pllout_frequency(void)75 uint32_t get_pllout_frequency(void)
76 {
77 	return __LL_RCC_CALC_PLLCLK_FREQ(get_pllsrc_frequency(),
78 					 pll_mul(STM32_PLL_MULTIPLIER),
79 					 pll_div(STM32_PLL_DIVISOR));
80 }
81 
82 #endif /* defined(STM32_PLL_ENABLED) */
83 
84 /**
85  * @brief Activate default clocks
86  */
config_enable_default_clocks(void)87 void config_enable_default_clocks(void)
88 {
89 #if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32) || \
90 	(defined(CONFIG_SOC_SERIES_STM32L0X) &&			  \
91 	 defined(CONFIG_ENTROPY_STM32_RNG))
92 	/* Enable System Configuration Controller clock. */
93 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
94 #endif
95 }
96