1 /*
2  * Copyright (c) 2019 Richard Osterloh <richard.osterloh@gmail.com>
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 
8 #include <soc.h>
9 #include <stm32_ll_bus.h>
10 #include <stm32_ll_pwr.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
16 #include <zephyr/sys/time_units.h>
17 #include "clock_stm32_ll_common.h"
18 
19 #if defined(STM32_PLL_ENABLED)
20 
21 /**
22  * @brief Return PLL source
23  */
24 __unused
get_pll_source(void)25 static uint32_t get_pll_source(void)
26 {
27 	/* Configure PLL source */
28 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
29 		return LL_RCC_PLLSOURCE_HSI;
30 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
31 		return LL_RCC_PLLSOURCE_HSE;
32 	}
33 
34 	__ASSERT(0, "Invalid source");
35 	return 0;
36 }
37 
38 /**
39  * @brief get the pll source frequency
40  */
41 __unused
get_pllsrc_frequency(void)42 uint32_t get_pllsrc_frequency(void)
43 {
44 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
45 		return STM32_HSI_FREQ;
46 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
47 		return STM32_HSE_FREQ;
48 	}
49 
50 	__ASSERT(0, "Invalid source");
51 	return 0;
52 }
53 
54 /**
55  * @brief Set up pll configuration
56  */
57 __unused
config_pll_sysclock(void)58 void config_pll_sysclock(void)
59 {
60 	/* set power boost mode for sys clock greater than 150MHz */
61 	if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
62 		LL_PWR_EnableRange1BoostMode();
63 	}
64 
65 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
66 				    pllm(STM32_PLL_M_DIVISOR),
67 				    STM32_PLL_N_MULTIPLIER,
68 				    pllr(STM32_PLL_R_DIVISOR));
69 
70 	LL_RCC_PLL_EnableDomain_SYS();
71 }
72 
73 #endif /* defined(STM32_PLL_ENABLED) */
74 
75 /**
76  * @brief Activate default clocks
77  */
config_enable_default_clocks(void)78 void config_enable_default_clocks(void)
79 {
80 	/* Enable the power interface clock */
81 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
82 }
83