1 /*
2  *
3  * Copyright (c) 2019 Ilya Tagunov
4  * Copyright (c) 2019 STMicroelectronics
5  *
6  * SPDX-License-Identifier: Apache-2.0
7  */
8 
9 
10 #include <soc.h>
11 #include <stm32_ll_bus.h>
12 #include <stm32_ll_crs.h>
13 #include <stm32_ll_rcc.h>
14 #include <stm32_ll_utils.h>
15 #include <zephyr/drivers/clock_control.h>
16 #include <zephyr/sys/util.h>
17 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
18 #include "clock_stm32_ll_common.h"
19 
20 #if defined(STM32_PLL_ENABLED)
21 
22 /**
23  * @brief Return PLL source
24  */
25 __unused
get_pll_source(void)26 static uint32_t get_pll_source(void)
27 {
28 	/* Configure PLL source */
29 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
30 		return LL_RCC_PLLSOURCE_HSI;
31 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
32 		return LL_RCC_PLLSOURCE_HSE;
33 	}
34 
35 	__ASSERT(0, "Invalid source");
36 	return 0;
37 }
38 
39 /**
40  * @brief get the pll source frequency
41  */
42 __unused
get_pllsrc_frequency(void)43 uint32_t get_pllsrc_frequency(void)
44 {
45 	if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
46 		return STM32_HSI_FREQ;
47 	} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
48 		return STM32_HSE_FREQ;
49 	}
50 
51 	__ASSERT(0, "Invalid source");
52 	return 0;
53 }
54 
55 /**
56  * @brief Set up pll configuration
57  */
58 __unused
config_pll_sysclock(void)59 void config_pll_sysclock(void)
60 {
61 	LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
62 				    pllm(STM32_PLL_M_DIVISOR),
63 				    STM32_PLL_N_MULTIPLIER,
64 				    pllr(STM32_PLL_R_DIVISOR));
65 
66 	LL_RCC_PLL_EnableDomain_SYS();
67 }
68 
69 #endif /* defined(STM32_PLL_ENABLED) */
70 
71 /**
72  * @brief Activate default clocks
73  */
config_enable_default_clocks(void)74 void config_enable_default_clocks(void)
75 {
76 	/* Enable the power interface clock */
77 	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
78 
79 #if defined(CRS)
80 	if (IS_ENABLED(STM32_HSI48_CRS_USB_SOF)) {
81 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
82 		/*
83 		 * After reset the CRS configuration register
84 		 * (CRS_CFGR) value corresponds to an USB SOF
85 		 * synchronization.  FIXME: write it anyway.
86 		 */
87 		LL_CRS_EnableAutoTrimming();
88 		LL_CRS_EnableFreqErrorCounter();
89 	}
90 #endif /* defined(CRS) */
91 
92 }
93