1 /*
2 *
3 * Copyright (c) 2017 Linaro Limited.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_pwr.h>
12 #include <stm32_ll_rcc.h>
13 #include <stm32_ll_utils.h>
14 #include <zephyr/drivers/clock_control.h>
15 #include <zephyr/sys/util.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include "clock_stm32_ll_common.h"
18
19 #if defined(STM32_PLL_ENABLED)
20
21 /**
22 * @brief Return PLL source
23 */
24 __unused
get_pll_source(void)25 static uint32_t get_pll_source(void)
26 {
27 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
28 return LL_RCC_PLLSOURCE_HSI;
29 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
30 return LL_RCC_PLLSOURCE_HSE;
31 }
32
33 __ASSERT(0, "Invalid source");
34 return 0;
35 }
36
37 /**
38 * @brief get the pll source frequency
39 */
40 __unused
get_pllsrc_frequency(void)41 uint32_t get_pllsrc_frequency(void)
42 {
43 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
44 return STM32_HSI_FREQ;
45 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
46 return STM32_HSE_FREQ;
47 }
48
49 __ASSERT(0, "Invalid source");
50 return 0;
51 }
52
53 /**
54 * @brief Set up pll configuration
55 */
56 __unused
config_pll_sysclock(void)57 void config_pll_sysclock(void)
58 {
59 #if defined(STM32_SRC_PLL_R) && STM32_PLL_R_ENABLED && defined(RCC_PLLCFGR_PLLR)
60 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR, pllr(STM32_PLL_R_DIVISOR));
61 #endif
62 LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
63 pllm(STM32_PLL_M_DIVISOR),
64 STM32_PLL_N_MULTIPLIER,
65 pllp(STM32_PLL_P_DIVISOR));
66
67 #if defined(CONFIG_SOC_SERIES_STM32F7X)
68 /* Assuming we stay on Power Scale default value: Power Scale 1 */
69 if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
70 /* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL
71 * locking phase since the system will be stalled during the switch
72 * (ODSW) but the PLL clock system will be running during the locking
73 * phase. See reference manual (RM0431) §4.1.4 Voltage regulator
74 * Sub section: Entering Over-drive mode.
75 */
76 LL_RCC_PLL_Enable();
77
78 /* Set Overdrive if needed before configuring the Flash Latency */
79 LL_PWR_EnableOverDriveMode();
80 while (LL_PWR_IsActiveFlag_OD() != 1) {
81 /* Wait for OverDrive mode ready */
82 }
83 LL_PWR_EnableOverDriveSwitching();
84 while (LL_PWR_IsActiveFlag_ODSW() != 1) {
85 /* Wait for OverDrive switch ready */
86 }
87
88 /* The PLL could still not be locked when returning to the caller
89 * function. But the caller doesn't know we've turned on the PLL
90 * for the overdrive function. The caller will try to turn on the PLL
91 * And start waiting for the PLL locking phase to complete.
92 */
93 }
94 #endif /* CONFIG_SOC_SERIES_STM32F7X */
95 }
96
97 #endif /* defined(STM32_PLL_ENABLED) */
98
99 #ifdef STM32_PLLI2S_ENABLED
100
101 /**
102 * @brief Set up PLL I2S configuration
103 */
104 __unused
config_plli2s(void)105 void config_plli2s(void)
106 {
107 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_plli2s_clock)
108 LL_RCC_PLLI2S_ConfigDomain_I2S(get_pll_source(),
109 pllm(STM32_PLLI2S_M_DIVISOR),
110 STM32_PLLI2S_N_MULTIPLIER,
111 plli2sr(STM32_PLLI2S_R_DIVISOR));
112 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f412_plli2s_clock)
113 LL_RCC_PLL_ConfigDomain_I2S(get_pll_source(),
114 plli2sm(STM32_PLLI2S_M_DIVISOR),
115 STM32_PLLI2S_N_MULTIPLIER,
116 plli2sr(STM32_PLLI2S_R_DIVISOR));
117 #endif
118 }
119
120 #endif /* STM32_PLLI2S_ENABLED */
121
122 /**
123 * @brief Activate default clocks
124 */
config_enable_default_clocks(void)125 void config_enable_default_clocks(void)
126 {
127 /* Power Interface clock enabled by default */
128 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
129 }
130
