1 /*
2 *
3 * Copyright (c) 2017 Linaro Limited.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8
9 #include <soc.h>
10 #include <stm32_ll_bus.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
16 #include "clock_stm32_ll_common.h"
17
18 #if defined(RCC_CFGR_ADCPRE)
19 #define z_adc_prescaler(v) LL_RCC_ADC_CLKSRC_PCLK2_DIV_ ## v
20 #define adc_prescaler(v) z_adc_prescaler(v)
21 #elif defined(RCC_CFGR2_ADC1PRES)
22 #define z_adc12_prescaler(v) \
23 COND_CODE_1(IS_EQ(v, 0), \
24 LL_RCC_ADC1_CLKSRC_HCLK, \
25 LL_RCC_ADC1_CLKSRC_PLL_DIV_ ## v)
26 #define adc12_prescaler(v) z_adc12_prescaler(v)
27 #else
28 #define z_adc12_prescaler(v) \
29 COND_CODE_1(IS_EQ(v, 0), \
30 LL_RCC_ADC12_CLKSRC_HCLK, \
31 LL_RCC_ADC12_CLKSRC_PLL_DIV_ ## v)
32 #define adc12_prescaler(v) z_adc12_prescaler(v)
33 #define z_adc34_prescaler(v) \
34 COND_CODE_1(IS_EQ(v, 0), \
35 LL_RCC_ADC34_CLKSRC_HCLK, \
36 LL_RCC_ADC34_CLKSRC_PLL_DIV_ ## v)
37 #define adc34_prescaler(v) z_adc34_prescaler(v)
38 #endif
39
40 #if defined(STM32_PLL_ENABLED)
41
42 /**
43 * @brief Set up pll configuration
44 */
45 __unused
config_pll_sysclock(void)46 void config_pll_sysclock(void)
47 {
48 uint32_t pll_source, pll_mul, pll_div;
49
50 /*
51 * PLL MUL
52 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
53 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
54 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
55 * ...
56 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
57 */
58 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
59
60 /*
61 * PLL PREDIV
62 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
63 * 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
64 * 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
65 * ...
66 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
67 */
68 pll_div = STM32_PLL_PREDIV - 1;
69
70 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
71 /*
72 * PREDIV1 support is a specific RCC configuration present on
73 * following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
74 * STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
75 * cf Reference manual for more details
76 */
77
78 /* Configure PLL source */
79 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
80 pll_source = LL_RCC_PLLSOURCE_HSE;
81 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
82 pll_source = LL_RCC_PLLSOURCE_HSI;
83 } else {
84 __ASSERT(0, "Invalid source");
85 }
86
87 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul, pll_div);
88 #else
89 /* Configure PLL source */
90 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
91 pll_source = LL_RCC_PLLSOURCE_HSE | pll_div;
92 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
93 pll_source = LL_RCC_PLLSOURCE_HSI_DIV_2;
94 } else {
95 __ASSERT(0, "Invalid source");
96 }
97
98 LL_RCC_PLL_ConfigDomain_SYS(pll_source, pll_mul);
99 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
100 }
101
102 /**
103 * @brief Return pllout frequency
104 */
105 __unused
get_pllout_frequency(void)106 uint32_t get_pllout_frequency(void)
107 {
108 uint32_t pll_input_freq, pll_mul, pll_div;
109
110 /*
111 * PLL MUL
112 * 2 -> LL_RCC_PLL_MUL_2 -> 0x00000000
113 * 3 -> LL_RCC_PLL_MUL_3 -> 0x00040000
114 * 4 -> LL_RCC_PLL_MUL_4 -> 0x00080000
115 * ...
116 * 16 -> LL_RCC_PLL_MUL_16 -> 0x00380000
117 */
118 pll_mul = ((STM32_PLL_MULTIPLIER - 2) << RCC_CFGR_PLLMUL_Pos);
119
120 /*
121 * PLL PREDIV
122 * 1 -> LL_RCC_PREDIV_DIV_1 -> 0x00000000
123 * 2 -> LL_RCC_PREDIV_DIV_2 -> 0x00000001
124 * 3 -> LL_RCC_PREDIV_DIV_3 -> 0x00000002
125 * ...
126 * 16 -> LL_RCC_PREDIV_DIV_16 -> 0x0000000F
127 */
128 pll_div = STM32_PLL_PREDIV - 1;
129
130 #if defined(RCC_PLLSRC_PREDIV1_SUPPORT)
131 /*
132 * PREDIV1 support is a specific RCC configuration present on
133 * following SoCs: STM32F04xx, STM32F07xx, STM32F09xx,
134 * STM32F030xC, STM32F302xE, STM32F303xE and STM32F39xx
135 * cf Reference manual for more details
136 */
137
138 /* Configure PLL source */
139 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
140 pll_input_freq = STM32_HSE_FREQ;
141 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
142 pll_input_freq = STM32_HSI_FREQ;
143 } else {
144 return 0;
145 }
146
147 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul, pll_div);
148 #else
149 /* Configure PLL source */
150 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
151 pll_input_freq = STM32_HSE_FREQ;
152 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
153 pll_input_freq = STM32_HSI_FREQ / 2;
154 } else {
155 return 0;
156 }
157
158 return __LL_RCC_CALC_PLLCLK_FREQ(pll_input_freq, pll_mul);
159 #endif /* RCC_PLLSRC_PREDIV1_SUPPORT */
160 }
161
162 #endif /* defined(STM32_PLL_ENABLED) */
163
164 /**
165 * @brief Activate default clocks
166 */
config_enable_default_clocks(void)167 void config_enable_default_clocks(void)
168 {
169 /* Enable PWR clock, required to access BDCR and PWR_CR */
170 LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
171
172 #ifndef CONFIG_SOC_SERIES_STM32F3X
173 #if defined(CONFIG_EXTI_STM32) || defined(CONFIG_USB_DC_STM32)
174 /* Enable System Configuration Controller clock. */
175 LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG);
176 #endif
177 #else
178 #if defined(CONFIG_USB_DC_STM32) && defined(SYSCFG_CFGR1_USB_IT_RMP)
179 /* Enable System Configuration Controller clock. */
180 /* SYSCFG is required to remap IRQ to avoid conflicts with CAN */
181 /* cf §14.1.3, RM0316 */
182 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
183 #endif
184 #endif /* !CONFIG_SOC_SERIES_STM32F3X */
185 }
186
