1 /*
2 * SPDX-License-Identifier: Apache-2.0
3 *
4 * Copyright (C) 2022, Linaro Ltd
5 *
6 */
7
8 #include <zephyr/drivers/clock_control.h>
9 #include <zephyr/sys/util.h>
10 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
11
12 #include <zephyr/logging/log.h>
13 #include <soc.h>
14
15 #define DT_DRV_COMPAT st_stm32_clock_mux
16
17 LOG_MODULE_REGISTER(clock_mux, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
18
19
20 struct stm32_clk_mux_config {
21 const struct stm32_pclken pclken;
22 };
23
stm32_clk_mux_init(const struct device * dev)24 static int stm32_clk_mux_init(const struct device *dev)
25 {
26 const struct stm32_clk_mux_config *cfg = dev->config;
27
28 if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
29 (clock_control_subsys_t) &cfg->pclken, NULL) != 0) {
30 LOG_ERR("Could not enable clock mux");
31 return -EIO;
32 }
33
34 return 0;
35 }
36
37 #define STM32_MUX_CLK_INIT(id) \
38 \
39 static const struct stm32_clk_mux_config stm32_clk_mux_cfg_##id = { \
40 .pclken = STM32_CLOCK_INFO(0, DT_DRV_INST(id)) \
41 }; \
42 \
43 DEVICE_DT_INST_DEFINE(id, &stm32_clk_mux_init, NULL, \
44 NULL, &stm32_clk_mux_cfg_##id, \
45 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,\
46 NULL);
47
48 DT_INST_FOREACH_STATUS_OKAY(STM32_MUX_CLK_INIT)
49
