1 /*
2 * Copyright (c) 2023 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <soc.h>
8 #include <stm32_ll_bus.h>
9 #include <stm32_ll_pwr.h>
10 #include <stm32_ll_rcc.h>
11 #include <stm32_ll_system.h>
12 #include <stm32_ll_utils.h>
13 #include <zephyr/drivers/clock_control.h>
14 #include <zephyr/sys/util.h>
15 #include <zephyr/sys/__assert.h>
16 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
17 #include "stm32_hsem.h"
18
19 /* Macros to fill up prescaler values */
20 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
21 #define ahb_prescaler(v) fn_ahb_prescaler(v)
22
23 #define fn_ahb5_prescaler(v) LL_RCC_AHB5_DIV_ ## v
24 #define ahb5_prescaler(v) fn_ahb5_prescaler(v)
25
26 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
27 #define apb1_prescaler(v) fn_apb1_prescaler(v)
28
29 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
30 #define apb2_prescaler(v) fn_apb2_prescaler(v)
31
32 #define fn_apb7_prescaler(v) LL_RCC_APB7_DIV_ ## v
33 #define apb7_prescaler(v) fn_apb7_prescaler(v)
34
35 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK_FREQ
36 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler
37
get_bus_clock(uint32_t clock,uint32_t prescaler)38 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
39 {
40 return clock / prescaler;
41 }
42
43 /** @brief Verifies clock is part of active clock configuration */
44 __unused
enabled_clock(uint32_t src_clk)45 static int enabled_clock(uint32_t src_clk)
46 {
47 if ((src_clk == STM32_SRC_SYSCLK) ||
48 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
49 ((src_clk == STM32_SRC_HSI16) && IS_ENABLED(STM32_HSI_ENABLED)) ||
50 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
51 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
52 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
53 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
54 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED))) {
55 return 0;
56 }
57
58 return -ENOTSUP;
59 }
60
stm32_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)61 static inline int stm32_clock_control_on(const struct device *dev,
62 clock_control_subsys_t sub_system)
63 {
64 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
65
66 ARG_UNUSED(dev);
67
68 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
69 /* Attemp to toggle a wrong periph clock bit */
70 return -ENOTSUP;
71 }
72
73 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
74 pclken->enr);
75 return 0;
76 }
77
stm32_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)78 static inline int stm32_clock_control_off(const struct device *dev,
79 clock_control_subsys_t sub_system)
80 {
81 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
82
83 ARG_UNUSED(dev);
84
85 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
86 /* Attemp to toggle a wrong periph clock bit */
87 return -ENOTSUP;
88 }
89
90 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
91 pclken->enr);
92
93 return 0;
94 }
95
stm32_clock_control_configure(const struct device * dev,clock_control_subsys_t sub_system,void * data)96 static inline int stm32_clock_control_configure(const struct device *dev,
97 clock_control_subsys_t sub_system,
98 void *data)
99 {
100 #if defined(STM32_SRC_CLOCK_MIN)
101 /* At least one alt src clock available */
102 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
103 int err;
104
105 ARG_UNUSED(dev);
106 ARG_UNUSED(data);
107
108 err = enabled_clock(pclken->bus);
109 if (err < 0) {
110 /* Attempt to configure a src clock not available or not valid */
111 return err;
112 }
113
114 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
115 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
116 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
117 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
118
119 return 0;
120 #else
121 /* No src clock available: Not supported */
122 return -ENOTSUP;
123 #endif
124 }
125
126 __unused
get_pllsrc_frequency(void)127 static uint32_t get_pllsrc_frequency(void)
128 {
129
130 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
131 return STM32_HSI_FREQ;
132 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
133 return STM32_HSE_FREQ;
134 }
135
136 __ASSERT(0, "No PLL Source configured");
137 return 0;
138 }
139
140 __unused
get_pllsrc(void)141 static uint32_t get_pllsrc(void)
142 {
143
144 if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
145 return LL_RCC_PLL1SOURCE_HSI;
146 } else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
147 return LL_RCC_PLL1SOURCE_HSE;
148 }
149
150 __ASSERT(0, "No PLL Source configured");
151 return 0;
152 }
153
stm32_clock_control_get_subsys_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)154 static int stm32_clock_control_get_subsys_rate(const struct device *dev,
155 clock_control_subsys_t sub_system,
156 uint32_t *rate)
157 {
158 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
159 /*
160 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
161 * SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
162 * since it will be updated after clock configuration and hence
163 * more likely to contain actual clock speed
164 */
165 uint32_t ahb_clock = SystemCoreClock;
166 uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
167 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
168 uint32_t apb7_clock = get_bus_clock(ahb_clock, STM32_APB7_PRESCALER);
169 uint32_t ahb5_clock;
170
171 ARG_UNUSED(dev);
172
173 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
174 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */
175 ahb5_clock = get_bus_clock(ahb_clock * STM32_AHB_PRESCALER,
176 STM32_AHB5_PRESCALER);
177 } else {
178 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */
179 if (IS_ENABLED(STM32_AHB5_DIV)) {
180 ahb5_clock = ahb_clock * STM32_AHB_PRESCALER / 2;
181 } else {
182 ahb5_clock = ahb_clock * STM32_AHB_PRESCALER;
183 }
184
185 }
186
187 __ASSERT(ahb5_clock <= MHZ(32), "AHB5 clock frequency exceeds 32 MHz");
188
189 switch (pclken->bus) {
190 case STM32_CLOCK_BUS_AHB1:
191 case STM32_CLOCK_BUS_AHB2:
192 case STM32_CLOCK_BUS_AHB4:
193 *rate = ahb_clock;
194 break;
195 case STM32_CLOCK_BUS_AHB5:
196 *rate = ahb5_clock;
197 break;
198 case STM32_CLOCK_BUS_APB1:
199 case STM32_CLOCK_BUS_APB1_2:
200 *rate = apb1_clock;
201 break;
202 case STM32_CLOCK_BUS_APB2:
203 *rate = apb2_clock;
204 break;
205 case STM32_CLOCK_BUS_APB7:
206 *rate = apb7_clock;
207 break;
208 case STM32_SRC_SYSCLK:
209 *rate = SystemCoreClock * STM32_CORE_PRESCALER;
210 break;
211 #if defined(STM32_PLL_ENABLED)
212 case STM32_SRC_PLL1_P:
213 *rate = __LL_RCC_CALC_PLL1PCLK_FREQ(get_pllsrc_frequency(),
214 STM32_PLL_M_DIVISOR,
215 STM32_PLL_N_MULTIPLIER,
216 STM32_PLL_P_DIVISOR);
217 break;
218 case STM32_SRC_PLL1_Q:
219 *rate = __LL_RCC_CALC_PLL1QCLK_FREQ(get_pllsrc_frequency(),
220 STM32_PLL_M_DIVISOR,
221 STM32_PLL_N_MULTIPLIER,
222 STM32_PLL_Q_DIVISOR);
223 break;
224 case STM32_SRC_PLL1_R:
225 *rate = __LL_RCC_CALC_PLL1RCLK_FREQ(get_pllsrc_frequency(),
226 STM32_PLL_M_DIVISOR,
227 STM32_PLL_N_MULTIPLIER,
228 STM32_PLL_R_DIVISOR);
229 break;
230 #endif /* STM32_PLL_ENABLED */
231 #if defined(STM32_LSE_ENABLED)
232 case STM32_SRC_LSE:
233 *rate = STM32_LSE_FREQ;
234 break;
235 #endif
236 #if defined(STM32_LSI_ENABLED)
237 case STM32_SRC_LSI:
238 *rate = STM32_LSI_FREQ;
239 break;
240 #endif
241 #if defined(STM32_HSI_ENABLED)
242 case STM32_SRC_HSI16:
243 *rate = STM32_HSI_FREQ;
244 break;
245 #endif
246 #if defined(STM32_HSE_ENABLED)
247 case STM32_SRC_HSE:
248 if (IS_ENABLED(STM32_HSE_DIV2)) {
249 *rate = STM32_HSE_FREQ / 2;
250 } else {
251 *rate = STM32_HSE_FREQ;
252 }
253
254 break;
255 #endif
256 default:
257 return -ENOTSUP;
258 }
259
260 return 0;
261 }
262
stm32_clock_control_get_status(const struct device * dev,clock_control_subsys_t sub_system)263 static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
264 clock_control_subsys_t sub_system)
265 {
266 struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
267
268 ARG_UNUSED(dev);
269
270 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
271 /* Gated clocks */
272 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
273 == pclken->enr) {
274 return CLOCK_CONTROL_STATUS_ON;
275 } else {
276 return CLOCK_CONTROL_STATUS_OFF;
277 }
278 } else {
279 /* Domain clock sources */
280 if (enabled_clock(pclken->bus) == 0) {
281 return CLOCK_CONTROL_STATUS_ON;
282 } else {
283 return CLOCK_CONTROL_STATUS_OFF;
284 }
285 }
286 }
287
288 static struct clock_control_driver_api stm32_clock_control_api = {
289 .on = stm32_clock_control_on,
290 .off = stm32_clock_control_off,
291 .get_rate = stm32_clock_control_get_subsys_rate,
292 .get_status = stm32_clock_control_get_status,
293 .configure = stm32_clock_control_configure,
294 };
295
296 __unused
get_vco_input_range(uint32_t m_div,uint32_t * range)297 static int get_vco_input_range(uint32_t m_div, uint32_t *range)
298 {
299 uint32_t vco_freq;
300
301 vco_freq = get_pllsrc_frequency() / m_div;
302
303 if (MHZ(4) <= vco_freq && vco_freq <= MHZ(8)) {
304 *range = LL_RCC_PLLINPUTRANGE_4_8;
305 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
306 *range = LL_RCC_PLLINPUTRANGE_8_16;
307 } else {
308 return -ERANGE;
309 }
310
311 return 0;
312 }
313
set_regu_voltage(uint32_t hclk_freq)314 static void set_regu_voltage(uint32_t hclk_freq)
315 {
316 if (hclk_freq <= MHZ(16)) {
317 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE2);
318 } else {
319 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
320 }
321 while (LL_PWR_IsActiveFlag_VOS() == 0) {
322 }
323 }
324
325 /*
326 * Unconditionally switch the system clock source to HSI.
327 */
328 __unused
stm32_clock_switch_to_hsi(void)329 static void stm32_clock_switch_to_hsi(void)
330 {
331 /* Enable HSI if not enabled */
332 if (LL_RCC_HSI_IsReady() != 1) {
333 /* Enable HSI */
334 LL_RCC_HSI_Enable();
335 while (LL_RCC_HSI_IsReady() != 1) {
336 /* Wait for HSI ready */
337 }
338 }
339
340 /* Set HSI as SYSCLCK source */
341 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
342 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
343 }
344 }
345
346 __unused
set_up_plls(void)347 static int set_up_plls(void)
348 {
349 #if defined(STM32_PLL_ENABLED)
350 int r;
351 uint32_t vco_input_range;
352
353 /*
354 * Case of chain-loaded applications:
355 * Switch to HSI and disable the PLL before configuration.
356 * (Switching to HSI makes sure we have a SYSCLK source in
357 * case we're currently running from the PLL we're about to
358 * turn off and reconfigure.)
359 *
360 */
361 if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R) {
362 LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
363 stm32_clock_switch_to_hsi();
364 }
365
366 LL_RCC_PLL1_Disable();
367
368 /* Configure PLL source */
369 /* Can be HSE, HSI */
370 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
371 /* Main PLL configuration and activation */
372 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSE);
373 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
374 /* Main PLL configuration and activation */
375 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_HSI);
376 } else {
377 return -ENOTSUP;
378 }
379
380 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
381 if (r < 0) {
382 return r;
383 }
384
385 LL_RCC_PLL1_SetDivider(STM32_PLL_M_DIVISOR);
386
387 LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
388
389 LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
390
391 LL_RCC_PLL1FRACN_Disable();
392
393 if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
394 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
395 LL_RCC_PLL1_EnableDomain_PLL1P();
396 }
397
398 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
399 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
400 LL_RCC_PLL1_EnableDomain_PLL1Q();
401 }
402
403 if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
404 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
405
406 LL_RCC_PLL1_EnableDomain_PLL1R();
407 }
408
409 /* Enable PLL */
410 LL_RCC_PLL1_Enable();
411 while (LL_RCC_PLL1_IsReady() != 1U) {
412 /* Wait for PLL ready */
413 }
414 #else
415 /* Init PLL source to None */
416 LL_RCC_PLL1_SetMainSource(LL_RCC_PLL1SOURCE_NONE);
417 #endif /* STM32_PLL_ENABLED */
418
419 return 0;
420 }
421
set_up_fixed_clock_sources(void)422 static void set_up_fixed_clock_sources(void)
423 {
424
425 if (IS_ENABLED(STM32_HSE_ENABLED)) {
426 if (IS_ENABLED(STM32_HSE_DIV2)) {
427 LL_RCC_HSE_EnablePrescaler();
428 }
429
430 /* Enable HSE */
431 LL_RCC_HSE_Enable();
432 while (LL_RCC_HSE_IsReady() != 1) {
433 /* Wait for HSE ready */
434 }
435 }
436
437 if (IS_ENABLED(STM32_HSI_ENABLED)) {
438 /* Enable HSI if not enabled */
439 if (LL_RCC_HSI_IsReady() != 1) {
440 /* Enable HSI */
441 LL_RCC_HSI_Enable();
442 while (LL_RCC_HSI_IsReady() != 1) {
443 /* Wait for HSI ready */
444 }
445 }
446 }
447
448 if (IS_ENABLED(STM32_LSI_ENABLED)) {
449 /* LSI belongs to the back-up domain, enable access.*/
450
451 /* Set the DBP bit in the Power control register 1 (PWR_CR1) */
452 LL_PWR_EnableBkUpAccess();
453 while (!LL_PWR_IsEnabledBkUpAccess()) {
454 /* Wait for Backup domain access */
455 }
456
457 LL_RCC_LSI1_Enable();
458 while (LL_RCC_LSI1_IsReady() != 1) {
459 }
460
461 LL_PWR_DisableBkUpAccess();
462 }
463
464 if (IS_ENABLED(STM32_LSE_ENABLED)) {
465 /* LSE belongs to the back-up domain, enable access.*/
466
467 /* Set the DBP bit in the Power control register 1 (PWR_CR1) */
468 LL_PWR_EnableBkUpAccess();
469 while (!LL_PWR_IsEnabledBkUpAccess()) {
470 /* Wait for Backup domain access */
471 }
472
473 /* Configure driving capability */
474 LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR1_LSEDRV_Pos);
475
476 /* Enable LSE Oscillator (32.768 kHz) */
477 LL_RCC_LSE_Enable();
478 while (!LL_RCC_LSE_IsReady()) {
479 /* Wait for LSE ready */
480 }
481
482 /* Enable LSESYS additionnally */
483 LL_RCC_LSE_EnablePropagation();
484 /* Wait till LSESYS is ready */
485 while (!LL_RCC_LSE_IsPropagationReady()) {
486 }
487 }
488 }
489
490 /**
491 * @brief Initialize clocks for the stm32
492 *
493 * This routine is called to enable and configure the clocks and PLL
494 * of the soc on the board. It depends on the board definition.
495 * This function is called on the startup and also to restore the config
496 * when exiting for low power mode.
497 *
498 * @param dev clock device struct
499 *
500 * @return 0
501 */
stm32_clock_control_init(const struct device * dev)502 int stm32_clock_control_init(const struct device *dev)
503 {
504 uint32_t old_flash_freq;
505 int r = 0;
506
507 ARG_UNUSED(dev);
508
509 old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(),
510 GET_CURRENT_FLASH_PRESCALER());
511
512
513
514 /* Set up individual enabled clocks */
515 set_up_fixed_clock_sources();
516
517 /* Set voltage regulator to comply with targeted system frequency */
518 set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
519
520 /* If required, apply max step freq for Sysclock w/ PLL input */
521 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
522 LL_RCC_PLL1_SetPLL1RCLKDivisionStep(LL_RCC_PLL1RCLK_2_STEP_DIV);
523
524 /* Send 2 pulses on CLKPRE like it is done in STM32Cube HAL */
525 LL_RCC_PLL1_DisablePLL1RCLKDivision();
526 LL_RCC_PLL1_EnablePLL1RCLKDivision();
527 LL_RCC_PLL1_DisablePLL1RCLKDivision();
528 LL_RCC_PLL1_EnablePLL1RCLKDivision();
529 }
530
531 /* Set up PLLs */
532 r = set_up_plls();
533 if (r < 0) {
534 return r;
535 }
536
537 /* If freq increases, set flash latency before any clock setting */
538 if (old_flash_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
539 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
540 }
541
542 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));
543
544 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
545 /* PLL is the SYSCLK source, use 'ahb5-prescaler' */
546 LL_RCC_SetAHB5Prescaler(ahb5_prescaler(STM32_AHB5_PRESCALER));
547 } else {
548 /* PLL is not the SYSCLK source, use 'ahb5-div'(if set) */
549 if (IS_ENABLED(STM32_AHB5_DIV)) {
550 LL_RCC_SetAHB5Divider(LL_RCC_AHB5_DIVIDER_2);
551 } else {
552 LL_RCC_SetAHB5Divider(LL_RCC_AHB5_DIVIDER_1);
553 }
554 }
555
556 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
557 /* Set PLL as System Clock Source */
558 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1R);
559 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1R) {
560 }
561 LL_RCC_PLL1_DisablePLL1RCLKDivision();
562 while (LL_RCC_PLL1_IsPLL1RCLKDivisionReady() == 0) {
563 }
564 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
565 /* Set HSE as SYSCLCK source */
566 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
567 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
568 }
569 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
570 stm32_clock_switch_to_hsi();
571 }
572
573 /* If freq not increased, set flash latency after all clock setting */
574 if (old_flash_freq >= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {
575 LL_SetFlashLatency(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
576 }
577
578 /* Set voltage regulator to comply with targeted system frequency */
579 set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
580
581 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
582
583 /* Set bus prescalers prescaler */
584 LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
585 LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
586 LL_RCC_SetAPB7Prescaler(apb7_prescaler(STM32_APB7_PRESCALER));
587
588 return 0;
589 }
590
591 /**
592 * @brief RCC device, note that priority is intentionally set to 1 so
593 * that the device init runs just after SOC init
594 */
595 DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
596 &stm32_clock_control_init,
597 NULL,
598 NULL, NULL,
599 PRE_KERNEL_1,
600 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
601 &stm32_clock_control_api);
602
