1 /*
2 *
3 * Copyright (c) 2019 Linaro Limited.
4 * Copyright (c) 2020 Jeremy LOCHE
5 * Copyright (c) 2021 Electrolance Solutions
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #include <soc.h>
11 #include <stm32_ll_bus.h>
12 #include <stm32_ll_pwr.h>
13 #include <stm32_ll_rcc.h>
14 #include <stm32_ll_utils.h>
15 #include <zephyr/arch/cpu.h>
16 #include <zephyr/drivers/clock_control.h>
17 #include <zephyr/sys/util.h>
18 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
19 #include "clock_stm32_ll_mco.h"
20 #include "stm32_hsem.h"
21
22
23 /* Macros to fill up prescaler values */
24 #define z_hsi_divider(v) LL_RCC_HSI_DIV ## v
25 #define hsi_divider(v) z_hsi_divider(v)
26
27 #define z_sysclk_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
28 #define sysclk_prescaler(v) z_sysclk_prescaler(v)
29
30 #define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
31 #define ahb_prescaler(v) z_ahb_prescaler(v)
32
33 #define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
34 #define apb1_prescaler(v) z_apb1_prescaler(v)
35
36 #define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
37 #define apb2_prescaler(v) z_apb2_prescaler(v)
38
39 #define z_apb3_prescaler(v) LL_RCC_APB3_DIV_ ## v
40 #define apb3_prescaler(v) z_apb3_prescaler(v)
41
42 #define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
43 #define apb4_prescaler(v) z_apb4_prescaler(v)
44
45 /* Macro to check for clock feasibility */
46 /* It is Cortex M7's responsibility to setup clock tree */
47 /* This check should only be performed for the M7 core code */
48 #ifdef CONFIG_CPU_CORTEX_M7
49
50 /* Choose PLL SRC */
51 #if defined(STM32_PLL_SRC_HSI)
52 #define PLLSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
53 #elif defined(STM32_PLL_SRC_CSI)
54 #define PLLSRC_FREQ STM32_CSI_FREQ
55 #elif defined(STM32_PLL_SRC_HSE)
56 #define PLLSRC_FREQ STM32_HSE_FREQ
57 #else
58 #define PLLSRC_FREQ 0
59 #endif
60
61 /* Given source clock and dividers, computed the output frequency of PLLP */
62 #define PLLP_FREQ(pllsrc_freq, divm, divn, divp) (((pllsrc_freq)*\
63 (divn))/((divm)*(divp)))
64
65 /* PLL P output frequency value */
66 #define PLLP_VALUE PLLP_FREQ(\
67 PLLSRC_FREQ,\
68 STM32_PLL_M_DIVISOR,\
69 STM32_PLL_N_MULTIPLIER,\
70 STM32_PLL_P_DIVISOR)
71
72 /* SYSCLKSRC before the D1CPRE prescaler */
73 #if defined(STM32_SYSCLK_SRC_PLL)
74 #define SYSCLKSRC_FREQ PLLP_VALUE
75 #elif defined(STM32_SYSCLK_SRC_HSI)
76 #define SYSCLKSRC_FREQ ((STM32_HSI_FREQ)/(STM32_HSI_DIVISOR))
77 #elif defined(STM32_SYSCLK_SRC_CSI)
78 #define SYSCLKSRC_FREQ STM32_CSI_FREQ
79 #elif defined(STM32_SYSCLK_SRC_HSE)
80 #define SYSCLKSRC_FREQ STM32_HSE_FREQ
81 #endif
82
83 /* ARM Sys CPU Clock before HPRE prescaler */
84 #define SYSCLK_FREQ ((SYSCLKSRC_FREQ)/(STM32_D1CPRE))
85 #define AHB_FREQ ((SYSCLK_FREQ)/(STM32_HPRE))
86 #define APB1_FREQ ((AHB_FREQ)/(STM32_D2PPRE1))
87 #define APB2_FREQ ((AHB_FREQ)/(STM32_D2PPRE2))
88 #define APB3_FREQ ((AHB_FREQ)/(STM32_D1PPRE))
89 #define APB4_FREQ ((AHB_FREQ)/(STM32_D3PPRE))
90
91 /* Datasheet maximum frequency definitions */
92 #if defined(CONFIG_SOC_STM32H743XX) ||\
93 defined(CONFIG_SOC_STM32H745XX) ||\
94 defined(CONFIG_SOC_STM32H747XX) ||\
95 defined(CONFIG_SOC_STM32H750XX) ||\
96 defined(CONFIG_SOC_STM32H753XX)
97 /* All h7 SoC with maximum 480MHz SYSCLK */
98 #define SYSCLK_FREQ_MAX 480000000UL
99 #define AHB_FREQ_MAX 240000000UL
100 #define APBx_FREQ_MAX 120000000UL
101 #elif defined(CONFIG_SOC_STM32H723XX) ||\
102 defined(CONFIG_SOC_STM32H725XX) ||\
103 defined(CONFIG_SOC_STM32H730XX) || defined(CONFIG_SOC_STM32H730XXQ) ||\
104 defined(CONFIG_SOC_STM32H735XX)
105 /* All h7 SoC with maximum 550MHz SYSCLK */
106 #define SYSCLK_FREQ_MAX 550000000UL
107 #define AHB_FREQ_MAX 275000000UL
108 #define APBx_FREQ_MAX 137500000UL
109 #elif defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) ||\
110 defined(CONFIG_SOC_STM32H7B0XX) || defined(CONFIG_SOC_STM32H7B0XXQ) ||\
111 defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
112 #define SYSCLK_FREQ_MAX 280000000UL
113 #define AHB_FREQ_MAX 280000000UL
114 #define APBx_FREQ_MAX 140000000UL
115 #else
116 /* Default: All h7 SoC with maximum 280MHz SYSCLK */
117 #define SYSCLK_FREQ_MAX 280000000UL
118 #define AHB_FREQ_MAX 140000000UL
119 #define APBx_FREQ_MAX 70000000UL
120 #endif
121
122 #if SYSCLK_FREQ > SYSCLK_FREQ_MAX
123 #error "SYSCLK frequency is too high!"
124 #endif
125 #if AHB_FREQ > AHB_FREQ_MAX
126 #error "AHB frequency is too high!"
127 #endif
128 #if APB1_FREQ > APBx_FREQ_MAX
129 #error "APB1 frequency is too high!"
130 #endif
131 #if APB2_FREQ > APBx_FREQ_MAX
132 #error "APB2 frequency is too high!"
133 #endif
134 #if APB3_FREQ > APBx_FREQ_MAX
135 #error "APB3 frequency is too high!"
136 #endif
137 #if APB4_FREQ > APBx_FREQ_MAX
138 #error "APB4 frequency is too high!"
139 #endif
140
141 #if SYSCLK_FREQ != CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
142 #error "SYS clock frequency for M7 core doesn't match CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC"
143 #endif
144
145 /* end of clock feasability check */
146 #endif /* CONFIG_CPU_CORTEX_M7 */
147
148
149 #if defined(CONFIG_CPU_CORTEX_M7)
150 #if STM32_D1CPRE > 1
151 /*
152 * D1CPRE prescaler allows to set a HCLK frequency lower than SYSCLK frequency.
153 * Though, zephyr doesn't make a difference today between these two clocks.
154 * So, changing this prescaler is not allowed until it is made possible to
155 * use them independently in zephyr clock subsystem.
156 */
157 #error "D1CPRE presacler can't be higher than 1"
158 #endif
159 #endif /* CONFIG_CPU_CORTEX_M7 */
160
161 #if defined(CONFIG_CPU_CORTEX_M7)
162 /* Offset to access bus clock registers from M7 (or only) core */
163 #define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc))
164 #elif defined(CONFIG_CPU_CORTEX_M4)
165 /* Offset to access bus clock registers from M4 core */
166 #define STM32H7_BUS_CLK_REG DT_REG_ADDR(DT_NODELABEL(rcc)) + 0x60
167 #endif
168
get_bus_clock(uint32_t clock,uint32_t prescaler)169 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
170 {
171 return clock / prescaler;
172 }
173
174 __unused
get_pllout_frequency(uint32_t pllsrc_freq,int pllm_div,int plln_mul,int pllout_div)175 static uint32_t get_pllout_frequency(uint32_t pllsrc_freq,
176 int pllm_div,
177 int plln_mul,
178 int pllout_div)
179 {
180 __ASSERT_NO_MSG(pllm_div && pllout_div);
181
182 return (pllsrc_freq / pllm_div) * plln_mul / pllout_div;
183 }
184
185 __unused
get_pllsrc_frequency(void)186 static uint32_t get_pllsrc_frequency(void)
187 {
188 switch (LL_RCC_PLL_GetSource()) {
189 case LL_RCC_PLLSOURCE_HSI:
190 return STM32_HSI_FREQ;
191 case LL_RCC_PLLSOURCE_CSI:
192 return STM32_CSI_FREQ;
193 case LL_RCC_PLLSOURCE_HSE:
194 return STM32_HSE_FREQ;
195 case LL_RCC_PLLSOURCE_NONE:
196 default:
197 return 0;
198 }
199 }
200
201 __unused
get_hclk_frequency(void)202 static uint32_t get_hclk_frequency(void)
203 {
204 uint32_t sysclk = 0;
205
206 /* Get the current system clock source */
207 switch (LL_RCC_GetSysClkSource()) {
208 case LL_RCC_SYS_CLKSOURCE_STATUS_HSI:
209 sysclk = STM32_HSI_FREQ/STM32_HSI_DIVISOR;
210 break;
211 case LL_RCC_SYS_CLKSOURCE_STATUS_CSI:
212 sysclk = STM32_CSI_FREQ;
213 break;
214 case LL_RCC_SYS_CLKSOURCE_STATUS_HSE:
215 sysclk = STM32_HSE_FREQ;
216 break;
217 #if defined(STM32_PLL_ENABLED)
218 case LL_RCC_SYS_CLKSOURCE_STATUS_PLL1:
219 sysclk = get_pllout_frequency(get_pllsrc_frequency(),
220 STM32_PLL_M_DIVISOR,
221 STM32_PLL_N_MULTIPLIER,
222 STM32_PLL_P_DIVISOR);
223 break;
224 #endif /* STM32_PLL_ENABLED */
225 }
226
227 return get_bus_clock(sysclk, STM32_HPRE);
228 }
229
230 #if !defined(CONFIG_CPU_CORTEX_M4)
231
prepare_regulator_voltage_scale(void)232 static int32_t prepare_regulator_voltage_scale(void)
233 {
234 /* Apply system power supply configuration */
235 #if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
236 LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
237 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
238 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
239 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
240 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
241 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
242 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
243 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
244 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
245 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
246 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
247 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
248 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
249 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
250 LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
251 #else
252 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
253 #endif
254
255 /* Make sure to put the CPU in highest Voltage scale during clock configuration */
256 /* Highest voltage is SCALE0 */
257 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
258 while (LL_PWR_IsActiveFlag_VOS() == 0) {
259 }
260 return 0;
261 }
262
optimize_regulator_voltage_scale(uint32_t sysclk_freq)263 static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
264 {
265
266 /* After sysclock is configured, tweak the voltage scale down */
267 /* to reduce power consumption */
268
269 /* Needs some smart work to configure properly */
270 /* LL_PWR_REGULATOR_SCALE3 is lowest power consumption */
271 /* Must be done in accordance to the Maximum allowed frequency vs VOS*/
272 /* See RM0433 page 352 for more details */
273 #if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
274 LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
275 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
276 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
277 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
278 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
279 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
280 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
281 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
282 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
283 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
284 LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
285 #elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
286 LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
287 #elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
288 LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
289 #else
290 LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
291 #endif
292 LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
293 while (LL_PWR_IsActiveFlag_VOS() == 0) {
294 }
295 return 0;
296 }
297
298 __unused
get_vco_input_range(uint32_t m_div,uint32_t * range)299 static int get_vco_input_range(uint32_t m_div, uint32_t *range)
300 {
301 uint32_t vco_freq;
302
303 vco_freq = PLLSRC_FREQ / m_div;
304
305 if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) {
306 *range = LL_RCC_PLLINPUTRANGE_1_2;
307 } else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) {
308 *range = LL_RCC_PLLINPUTRANGE_2_4;
309 } else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) {
310 *range = LL_RCC_PLLINPUTRANGE_4_8;
311 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) {
312 *range = LL_RCC_PLLINPUTRANGE_8_16;
313 } else {
314 return -ERANGE;
315 }
316
317 return 0;
318 }
319
320 __unused
get_vco_output_range(uint32_t vco_input_range)321 static uint32_t get_vco_output_range(uint32_t vco_input_range)
322 {
323 if (vco_input_range == LL_RCC_PLLINPUTRANGE_1_2) {
324 return LL_RCC_PLLVCORANGE_MEDIUM;
325 }
326
327 return LL_RCC_PLLVCORANGE_WIDE;
328 }
329
330 #endif /* ! CONFIG_CPU_CORTEX_M4 */
331
332 /** @brief Verifies clock is part of actve clock configuration */
enabled_clock(uint32_t src_clk)333 static int enabled_clock(uint32_t src_clk)
334 {
335
336 if ((src_clk == STM32_SRC_SYSCLK) ||
337 ((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
338 ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
339 ((src_clk == STM32_SRC_HSI_KER) && IS_ENABLED(STM32_HSI_ENABLED)) ||
340 ((src_clk == STM32_SRC_CSI_KER) && IS_ENABLED(STM32_CSI_ENABLED)) ||
341 ((src_clk == STM32_SRC_HSI48) && IS_ENABLED(STM32_HSI48_ENABLED)) ||
342 ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
343 ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
344 ((src_clk == STM32_SRC_PLL1_P) && IS_ENABLED(STM32_PLL_P_ENABLED)) ||
345 ((src_clk == STM32_SRC_PLL1_Q) && IS_ENABLED(STM32_PLL_Q_ENABLED)) ||
346 ((src_clk == STM32_SRC_PLL1_R) && IS_ENABLED(STM32_PLL_R_ENABLED)) ||
347 ((src_clk == STM32_SRC_PLL2_P) && IS_ENABLED(STM32_PLL2_P_ENABLED)) ||
348 ((src_clk == STM32_SRC_PLL2_Q) && IS_ENABLED(STM32_PLL2_Q_ENABLED)) ||
349 ((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
350 ((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
351 ((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
352 ((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
353 return 0;
354 }
355
356 return -ENOTSUP;
357 }
358
stm32_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)359 static inline int stm32_clock_control_on(const struct device *dev,
360 clock_control_subsys_t sub_system)
361 {
362 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
363
364 ARG_UNUSED(dev);
365
366 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
367 /* Attemp to toggle a wrong periph clock bit */
368 return -ENOTSUP;
369 }
370
371 z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
372
373 sys_set_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
374
375 z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
376
377 return 0;
378 }
379
stm32_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)380 static inline int stm32_clock_control_off(const struct device *dev,
381 clock_control_subsys_t sub_system)
382 {
383 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
384
385 ARG_UNUSED(dev);
386
387 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
388 /* Attemp to toggle a wrong periph clock bit */
389 return -ENOTSUP;
390 }
391
392 z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
393
394 sys_clear_bits(STM32H7_BUS_CLK_REG + pclken->bus, pclken->enr);
395
396 z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
397
398 return 0;
399 }
400
stm32_clock_control_configure(const struct device * dev,clock_control_subsys_t sub_system,void * data)401 static inline int stm32_clock_control_configure(const struct device *dev,
402 clock_control_subsys_t sub_system,
403 void *data)
404 {
405 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
406 int err;
407
408 ARG_UNUSED(dev);
409 ARG_UNUSED(data);
410
411 err = enabled_clock(pclken->bus);
412 if (err < 0) {
413 /* Attemp to configure a src clock not available or not valid */
414 return err;
415 }
416
417 z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
418
419 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
420 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
421 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
422 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
423
424 z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
425
426 return 0;
427 }
428
stm32_clock_control_get_subsys_rate(const struct device * clock,clock_control_subsys_t sub_system,uint32_t * rate)429 static int stm32_clock_control_get_subsys_rate(const struct device *clock,
430 clock_control_subsys_t sub_system,
431 uint32_t *rate)
432 {
433 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
434 /*
435 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
436 * SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
437 * since it will be updated after clock configuration and hence
438 * more likely to contain actual clock speed
439 */
440 #if defined(CONFIG_CPU_CORTEX_M4)
441 uint32_t ahb_clock = SystemCoreClock;
442 #else
443 uint32_t ahb_clock = get_bus_clock(SystemCoreClock, STM32_HPRE);
444 #endif
445 uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_D2PPRE1);
446 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_D2PPRE2);
447 uint32_t apb3_clock = get_bus_clock(ahb_clock, STM32_D1PPRE);
448 uint32_t apb4_clock = get_bus_clock(ahb_clock, STM32_D3PPRE);
449
450 ARG_UNUSED(clock);
451
452 switch (pclken->bus) {
453 case STM32_CLOCK_BUS_AHB1:
454 case STM32_CLOCK_BUS_AHB2:
455 case STM32_CLOCK_BUS_AHB3:
456 case STM32_CLOCK_BUS_AHB4:
457 *rate = ahb_clock;
458 break;
459 case STM32_CLOCK_BUS_APB1:
460 case STM32_CLOCK_BUS_APB1_2:
461 *rate = apb1_clock;
462 break;
463 case STM32_CLOCK_BUS_APB2:
464 *rate = apb2_clock;
465 break;
466 case STM32_CLOCK_BUS_APB3:
467 *rate = apb3_clock;
468 break;
469 case STM32_CLOCK_BUS_APB4:
470 *rate = apb4_clock;
471 break;
472 case STM32_SRC_SYSCLK:
473 *rate = get_hclk_frequency();
474 break;
475 #if defined(STM32_CKPER_ENABLED)
476 case STM32_SRC_CKPER:
477 *rate = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
478 break;
479 #endif /* STM32_CKPER_ENABLED */
480 #if defined(STM32_HSE_ENABLED)
481 case STM32_SRC_HSE:
482 *rate = STM32_HSE_FREQ;
483 break;
484 #endif /* STM32_HSE_ENABLED */
485 #if defined(STM32_LSE_ENABLED)
486 case STM32_SRC_LSE:
487 *rate = STM32_LSE_FREQ;
488 break;
489 #endif /* STM32_LSE_ENABLED */
490 #if defined(STM32_LSI_ENABLED)
491 case STM32_SRC_LSI:
492 *rate = STM32_LSI_FREQ;
493 break;
494 #endif /* STM32_LSI_ENABLED */
495 #if defined(STM32_HSI48_ENABLED)
496 case STM32_SRC_HSI48:
497 *rate = STM32_HSI48_FREQ;
498 break;
499 #endif /* STM32_HSI48_ENABLED */
500 #if defined(STM32_PLL_ENABLED)
501 case STM32_SRC_PLL1_P:
502 *rate = get_pllout_frequency(get_pllsrc_frequency(),
503 STM32_PLL_M_DIVISOR,
504 STM32_PLL_N_MULTIPLIER,
505 STM32_PLL_P_DIVISOR);
506 break;
507 case STM32_SRC_PLL1_Q:
508 *rate = get_pllout_frequency(get_pllsrc_frequency(),
509 STM32_PLL_M_DIVISOR,
510 STM32_PLL_N_MULTIPLIER,
511 STM32_PLL_Q_DIVISOR);
512 break;
513 case STM32_SRC_PLL1_R:
514 *rate = get_pllout_frequency(get_pllsrc_frequency(),
515 STM32_PLL_M_DIVISOR,
516 STM32_PLL_N_MULTIPLIER,
517 STM32_PLL_R_DIVISOR);
518 break;
519 #endif /* STM32_PLL_ENABLED */
520 #if defined(STM32_PLL2_ENABLED)
521 case STM32_SRC_PLL2_P:
522 *rate = get_pllout_frequency(get_pllsrc_frequency(),
523 STM32_PLL2_M_DIVISOR,
524 STM32_PLL2_N_MULTIPLIER,
525 STM32_PLL2_P_DIVISOR);
526 break;
527 case STM32_SRC_PLL2_Q:
528 *rate = get_pllout_frequency(get_pllsrc_frequency(),
529 STM32_PLL2_M_DIVISOR,
530 STM32_PLL2_N_MULTIPLIER,
531 STM32_PLL2_Q_DIVISOR);
532 break;
533 case STM32_SRC_PLL2_R:
534 *rate = get_pllout_frequency(get_pllsrc_frequency(),
535 STM32_PLL2_M_DIVISOR,
536 STM32_PLL2_N_MULTIPLIER,
537 STM32_PLL2_R_DIVISOR);
538 break;
539 #endif /* STM32_PLL2_ENABLED */
540 #if defined(STM32_PLL3_ENABLED)
541 case STM32_SRC_PLL3_P:
542 *rate = get_pllout_frequency(get_pllsrc_frequency(),
543 STM32_PLL3_M_DIVISOR,
544 STM32_PLL3_N_MULTIPLIER,
545 STM32_PLL3_P_DIVISOR);
546 break;
547 case STM32_SRC_PLL3_Q:
548 *rate = get_pllout_frequency(get_pllsrc_frequency(),
549 STM32_PLL3_M_DIVISOR,
550 STM32_PLL3_N_MULTIPLIER,
551 STM32_PLL3_Q_DIVISOR);
552 break;
553 case STM32_SRC_PLL3_R:
554 *rate = get_pllout_frequency(get_pllsrc_frequency(),
555 STM32_PLL3_M_DIVISOR,
556 STM32_PLL3_N_MULTIPLIER,
557 STM32_PLL3_R_DIVISOR);
558 break;
559 #endif /* STM32_PLL3_ENABLED */
560 default:
561 return -ENOTSUP;
562 }
563
564 return 0;
565 }
566
567 static struct clock_control_driver_api stm32_clock_control_api = {
568 .on = stm32_clock_control_on,
569 .off = stm32_clock_control_off,
570 .get_rate = stm32_clock_control_get_subsys_rate,
571 .configure = stm32_clock_control_configure,
572 };
573
574 __unused
set_up_fixed_clock_sources(void)575 static void set_up_fixed_clock_sources(void)
576 {
577
578 if (IS_ENABLED(STM32_HSE_ENABLED)) {
579 /* Enable HSE oscillator */
580 if (IS_ENABLED(STM32_HSE_BYPASS)) {
581 LL_RCC_HSE_EnableBypass();
582 } else {
583 LL_RCC_HSE_DisableBypass();
584 }
585
586 LL_RCC_HSE_Enable();
587 while (LL_RCC_HSE_IsReady() != 1) {
588 }
589 /* Check if we need to enable HSE clock security system or not */
590 #if STM32_HSE_CSS
591 z_arm_nmi_set_handler(HAL_RCC_NMI_IRQHandler);
592 LL_RCC_HSE_EnableCSS();
593 #endif /* STM32_HSE_CSS */
594 }
595
596 if (IS_ENABLED(STM32_HSI_ENABLED)) {
597 /* Enable HSI oscillator */
598 LL_RCC_HSI_Enable();
599 while (LL_RCC_HSI_IsReady() != 1) {
600 }
601 /* HSI divider configuration */
602 LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
603 }
604
605 if (IS_ENABLED(STM32_CSI_ENABLED)) {
606 /* Enable CSI oscillator */
607 LL_RCC_CSI_Enable();
608 while (LL_RCC_CSI_IsReady() != 1) {
609 }
610 }
611
612 if (IS_ENABLED(STM32_LSI_ENABLED)) {
613 /* Enable LSI oscillator */
614 LL_RCC_LSI_Enable();
615 while (LL_RCC_LSI_IsReady() != 1) {
616 }
617 }
618
619 if (IS_ENABLED(STM32_LSE_ENABLED)) {
620 /* Enable backup domain */
621 LL_PWR_EnableBkUpAccess();
622
623 /* Configure driving capability */
624 LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
625
626 if (IS_ENABLED(STM32_LSE_BYPASS)) {
627 /* Configure LSE bypass */
628 LL_RCC_LSE_EnableBypass();
629 }
630
631 /* Enable LSE oscillator */
632 LL_RCC_LSE_Enable();
633 while (LL_RCC_LSE_IsReady() != 1) {
634 }
635 }
636
637 if (IS_ENABLED(STM32_HSI48_ENABLED)) {
638 LL_RCC_HSI48_Enable();
639 while (LL_RCC_HSI48_IsReady() != 1) {
640 }
641 }
642 }
643
644 /*
645 * Unconditionally switch the system clock source to HSI.
646 */
647 __unused
stm32_clock_switch_to_hsi(void)648 static void stm32_clock_switch_to_hsi(void)
649 {
650 /* Enable HSI if not enabled */
651 if (LL_RCC_HSI_IsReady() != 1) {
652 /* Enable HSI */
653 LL_RCC_HSI_Enable();
654 while (LL_RCC_HSI_IsReady() != 1) {
655 /* Wait for HSI ready */
656 }
657 }
658
659 /* Set HSI as SYSCLCK source */
660 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
661 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
662 }
663 }
664
665 __unused
set_up_plls(void)666 static int set_up_plls(void)
667 {
668 #if defined(STM32_PLL_ENABLED) || defined(STM32_PLL2_ENABLED) || defined(STM32_PLL3_ENABLED)
669 int r;
670 uint32_t vco_input_range;
671 uint32_t vco_output_range;
672
673 /*
674 * Case of chain-loaded applications:
675 * Switch to HSI and disable the PLL before configuration.
676 * (Switching to HSI makes sure we have a SYSCLK source in
677 * case we're currently running from the PLL we're about to
678 * turn off and reconfigure.)
679 *
680 */
681 if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
682 stm32_clock_switch_to_hsi();
683 LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
684 }
685 LL_RCC_PLL1_Disable();
686
687 /* Configure PLL source */
688
689 /* Can be HSE , HSI 64Mhz/HSIDIV, CSI 4MHz*/
690 if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
691 /* Main PLL configuration and activation */
692 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSE);
693 } else if (IS_ENABLED(STM32_PLL_SRC_CSI)) {
694 /* Main PLL configuration and activation */
695 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_CSI);
696 } else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
697 /* Main PLL configuration and activation */
698 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_HSI);
699 } else {
700 return -ENOTSUP;
701 }
702
703 #if defined(STM32_PLL_ENABLED)
704 r = get_vco_input_range(STM32_PLL_M_DIVISOR, &vco_input_range);
705 if (r < 0) {
706 return r;
707 }
708
709 vco_output_range = get_vco_output_range(vco_input_range);
710
711 LL_RCC_PLL1_SetM(STM32_PLL_M_DIVISOR);
712
713 LL_RCC_PLL1_SetVCOInputRange(vco_input_range);
714 LL_RCC_PLL1_SetVCOOutputRange(vco_output_range);
715
716 LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
717
718 /* FRACN disable DIVP,DIVQ,DIVR enable*/
719 LL_RCC_PLL1FRACN_Disable();
720
721 if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
722 LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
723 LL_RCC_PLL1P_Enable();
724 }
725
726 if (IS_ENABLED(STM32_PLL_Q_ENABLED)) {
727 LL_RCC_PLL1_SetQ(STM32_PLL_Q_DIVISOR);
728 LL_RCC_PLL1Q_Enable();
729 }
730
731 if (IS_ENABLED(STM32_PLL_R_ENABLED)) {
732 LL_RCC_PLL1_SetR(STM32_PLL_R_DIVISOR);
733 LL_RCC_PLL1R_Enable();
734 }
735
736 LL_RCC_PLL1_Enable();
737 while (LL_RCC_PLL1_IsReady() != 1U) {
738 }
739
740 #endif /* STM32_PLL_ENABLED */
741
742 #if defined(STM32_PLL2_ENABLED)
743 r = get_vco_input_range(STM32_PLL2_M_DIVISOR, &vco_input_range);
744 if (r < 0) {
745 return r;
746 }
747
748 vco_output_range = get_vco_output_range(vco_input_range);
749
750 LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
751
752 LL_RCC_PLL2_SetVCOInputRange(vco_input_range);
753 LL_RCC_PLL2_SetVCOOutputRange(vco_output_range);
754
755 LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
756
757 LL_RCC_PLL2FRACN_Disable();
758
759 if (IS_ENABLED(STM32_PLL2_P_ENABLED)) {
760 LL_RCC_PLL2_SetP(STM32_PLL2_P_DIVISOR);
761 LL_RCC_PLL2P_Enable();
762 }
763
764 if (IS_ENABLED(STM32_PLL2_Q_ENABLED)) {
765 LL_RCC_PLL2_SetQ(STM32_PLL2_Q_DIVISOR);
766 LL_RCC_PLL2Q_Enable();
767 }
768
769 if (IS_ENABLED(STM32_PLL2_R_ENABLED)) {
770 LL_RCC_PLL2_SetR(STM32_PLL2_R_DIVISOR);
771 LL_RCC_PLL2R_Enable();
772 }
773
774 LL_RCC_PLL2_Enable();
775 while (LL_RCC_PLL2_IsReady() != 1U) {
776 }
777
778 #endif /* STM32_PLL2_ENABLED */
779
780 #if defined(STM32_PLL3_ENABLED)
781 r = get_vco_input_range(STM32_PLL3_M_DIVISOR, &vco_input_range);
782 if (r < 0) {
783 return r;
784 }
785
786 vco_output_range = get_vco_output_range(vco_input_range);
787
788 LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
789
790 LL_RCC_PLL3_SetVCOInputRange(vco_input_range);
791 LL_RCC_PLL3_SetVCOOutputRange(vco_output_range);
792
793 LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
794
795 LL_RCC_PLL3FRACN_Disable();
796
797 if (IS_ENABLED(STM32_PLL3_P_ENABLED)) {
798 LL_RCC_PLL3_SetP(STM32_PLL3_P_DIVISOR);
799 LL_RCC_PLL3P_Enable();
800 }
801
802 if (IS_ENABLED(STM32_PLL3_Q_ENABLED)) {
803 LL_RCC_PLL3_SetQ(STM32_PLL3_Q_DIVISOR);
804 LL_RCC_PLL3Q_Enable();
805 }
806
807 if (IS_ENABLED(STM32_PLL3_R_ENABLED)) {
808 LL_RCC_PLL3_SetR(STM32_PLL3_R_DIVISOR);
809 LL_RCC_PLL3R_Enable();
810 }
811
812 LL_RCC_PLL3_Enable();
813 while (LL_RCC_PLL3_IsReady() != 1U) {
814 }
815
816 #endif /* STM32_PLL3_ENABLED */
817
818 #else
819 /* Init PLL source to None */
820 LL_RCC_PLL_SetSource(LL_RCC_PLLSOURCE_NONE);
821
822 #endif /* STM32_PLL_ENABLED || STM32_PLL2_ENABLED || STM32_PLL3_ENABLED */
823
824 return 0;
825 }
826
stm32_clock_control_init(const struct device * dev)827 int stm32_clock_control_init(const struct device *dev)
828 {
829 int r = 0;
830
831 #if defined(CONFIG_CPU_CORTEX_M7)
832 uint32_t old_hclk_freq = 0;
833 uint32_t new_hclk_freq = 0;
834
835 /* HW semaphore Clock enable */
836 #if defined(CONFIG_SOC_STM32H7A3XX) || defined(CONFIG_SOC_STM32H7A3XXQ) || \
837 defined(CONFIG_SOC_STM32H7B0XX) || defined(CONFIG_SOC_STM32H7B0XXQ) || \
838 defined(CONFIG_SOC_STM32H7B3XX) || defined(CONFIG_SOC_STM32H7B3XXQ)
839 LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_HSEM);
840 #else
841 LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_HSEM);
842 #endif
843
844 z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
845
846 /* Configure MCO1/MCO2 based on Kconfig */
847 stm32_clock_control_mco_init();
848
849 /* Set up indiviual enabled clocks */
850 set_up_fixed_clock_sources();
851
852 /* Set up PLLs */
853 r = set_up_plls();
854 if (r < 0) {
855 return r;
856 }
857
858 /* Configure Voltage scale to comply with the desired system frequency */
859 prepare_regulator_voltage_scale();
860
861 /* Current hclk value */
862 old_hclk_freq = get_hclk_frequency();
863 /* AHB is HCLK clock to configure */
864 new_hclk_freq = get_bus_clock(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
865 STM32_HPRE);
866
867 /* Set flash latency */
868 /* AHB/AXI/HCLK clock is SYSCLK / HPRE */
869 /* If freq increases, set flash latency before any clock setting */
870 if (new_hclk_freq > old_hclk_freq) {
871 LL_SetFlashLatency(new_hclk_freq);
872 }
873
874 /* Preset the prescalers prior to chosing SYSCLK */
875 /* Prevents APB clock to go over limits */
876 /* Set buses (Sys,AHB, APB1, APB2 & APB4) prescalers */
877 LL_RCC_SetSysPrescaler(sysclk_prescaler(STM32_D1CPRE));
878 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_HPRE));
879 LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_D2PPRE1));
880 LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_D2PPRE2));
881 LL_RCC_SetAPB3Prescaler(apb3_prescaler(STM32_D1PPRE));
882 LL_RCC_SetAPB4Prescaler(apb4_prescaler(STM32_D3PPRE));
883
884 /* Set up sys clock */
885 if (IS_ENABLED(STM32_SYSCLK_SRC_PLL)) {
886 /* Set PLL1 as System Clock Source */
887 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1);
888 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) {
889 }
890 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
891 /* Set sysclk source to HSE */
892 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
893 while (LL_RCC_GetSysClkSource() !=
894 LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
895 }
896 } else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
897 /* Set sysclk source to HSI */
898 stm32_clock_switch_to_hsi();
899 } else if (IS_ENABLED(STM32_SYSCLK_SRC_CSI)) {
900 /* Set sysclk source to CSI */
901 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_CSI);
902 while (LL_RCC_GetSysClkSource() !=
903 LL_RCC_SYS_CLKSOURCE_STATUS_CSI) {
904 }
905 } else {
906 return -ENOTSUP;
907 }
908
909 /* Set FLASH latency */
910 /* AHB/AXI/HCLK clock is SYSCLK / HPRE */
911 /* If freq not increased, set flash latency after all clock setting */
912 if (new_hclk_freq <= old_hclk_freq) {
913 LL_SetFlashLatency(new_hclk_freq);
914 }
915
916 optimize_regulator_voltage_scale(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
917
918 z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
919 #endif /* CONFIG_CPU_CORTEX_M7 */
920
921 ARG_UNUSED(dev);
922
923 /* Update CMSIS variable */
924 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
925
926 return r;
927 }
928
929 #if defined(STM32_HSE_CSS)
stm32_hse_css_callback(void)930 void __weak stm32_hse_css_callback(void) {}
931
932 /* Called by the HAL in response to an HSE CSS interrupt */
HAL_RCC_CSSCallback(void)933 void HAL_RCC_CSSCallback(void)
934 {
935 stm32_hse_css_callback();
936 }
937 #endif
938
939 /**
940 * @brief RCC device, note that priority is intentionally set to 1 so
941 * that the device init runs just after SOC init
942 */
943 DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
944 &stm32_clock_control_init,
945 NULL,
946 NULL, NULL,
947 PRE_KERNEL_1,
948 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
949 &stm32_clock_control_api);
950
