1 /*
2 * Copyright (c) 2017-2022 Linaro Limited.
3 * Copyright (c) 2017 RnDity Sp. z o.o.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #include <soc.h>
9 #include <stm32_ll_bus.h>
10 #include <stm32_ll_pwr.h>
11 #include <stm32_ll_rcc.h>
12 #include <stm32_ll_system.h>
13 #include <stm32_ll_utils.h>
14 #include <zephyr/arch/cpu.h>
15 #include <zephyr/drivers/clock_control.h>
16 #include <zephyr/sys/util.h>
17 #include <zephyr/sys/__assert.h>
18 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
19 #include "clock_stm32_ll_common.h"
20 #include "clock_stm32_ll_mco.h"
21 #include "stm32_hsem.h"
22
23 /* Macros to fill up prescaler values */
24 #define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
25 #define hsi_divider(v) z_hsi_divider(v)
26
27 #define fn_ahb_prescaler(v) LL_RCC_SYSCLK_DIV_ ## v
28 #define ahb_prescaler(v) fn_ahb_prescaler(v)
29
30 #define fn_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
31 #define apb1_prescaler(v) fn_apb1_prescaler(v)
32
33 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), apb2_prescaler)
34 #define fn_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
35 #define apb2_prescaler(v) fn_apb2_prescaler(v)
36 #endif
37
38 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
39 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK4_FREQ
40 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHB4Prescaler
41 #elif DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
42 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK3_FREQ
43 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHB3Prescaler
44 #else
45 #define RCC_CALC_FLASH_FREQ __LL_RCC_CALC_HCLK_FREQ
46 #define GET_CURRENT_FLASH_PRESCALER LL_RCC_GetAHBPrescaler
47 #endif
48
49 #if defined(RCC_PLLCFGR_PLLPEN)
50 #define RCC_PLLP_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN)
51 #else
52 #define RCC_PLLP_ENABLE()
53 #endif /* RCC_PLLCFGR_PLLPEN */
54 #if defined(RCC_PLLCFGR_PLLQEN)
55 #define RCC_PLLQ_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN)
56 #else
57 #define RCC_PLLQ_ENABLE()
58 #endif /* RCC_PLLCFGR_PLLQEN */
59
60 /**
61 * @brief Return frequency for pll with 2 dividers and a multiplier
62 */
63 __unused
get_pll_div_frequency(uint32_t pllsrc_freq,int pllm_div,int plln_mul,int pllout_div)64 static uint32_t get_pll_div_frequency(uint32_t pllsrc_freq,
65 int pllm_div,
66 int plln_mul,
67 int pllout_div)
68 {
69 __ASSERT_NO_MSG(pllm_div && pllout_div);
70
71 return pllsrc_freq / pllm_div * plln_mul / pllout_div;
72 }
73
get_bus_clock(uint32_t clock,uint32_t prescaler)74 static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
75 {
76 return clock / prescaler;
77 }
78
79 __unused
get_msi_frequency(void)80 static uint32_t get_msi_frequency(void)
81 {
82 #if defined(STM32_MSI_ENABLED)
83 #if !defined(LL_RCC_MSIRANGESEL_RUN)
84 return __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
85 #else
86 return __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN,
87 LL_RCC_MSI_GetRange());
88 #endif
89 #endif
90 return 0;
91 }
92
93 /** @brief Verifies clock is part of active clock configuration */
94 __unused
enabled_clock(uint32_t src_clk)95 static int enabled_clock(uint32_t src_clk)
96 {
97 int r = 0;
98
99 switch (src_clk) {
100 #if defined(STM32_SRC_SYSCLK)
101 case STM32_SRC_SYSCLK:
102 break;
103 #endif /* STM32_SRC_SYSCLK */
104 #if defined(STM32_SRC_PCLK)
105 case STM32_SRC_PCLK:
106 break;
107 #endif /* STM32_SRC_PCLK */
108 #if defined(STM32_SRC_HSE)
109 case STM32_SRC_HSE:
110 if (!IS_ENABLED(STM32_HSE_ENABLED)) {
111 r = -ENOTSUP;
112 }
113 break;
114 #endif /* STM32_SRC_HSE */
115 #if defined(STM32_SRC_HSI)
116 case STM32_SRC_HSI:
117 if (!IS_ENABLED(STM32_HSI_ENABLED)) {
118 r = -ENOTSUP;
119 }
120 break;
121 #endif /* STM32_SRC_HSI */
122 #if defined(STM32_SRC_LSE)
123 case STM32_SRC_LSE:
124 if (!IS_ENABLED(STM32_LSE_ENABLED)) {
125 r = -ENOTSUP;
126 }
127 break;
128 #endif /* STM32_SRC_LSE */
129 #if defined(STM32_SRC_LSI)
130 case STM32_SRC_LSI:
131 if (!IS_ENABLED(STM32_LSI_ENABLED)) {
132 r = -ENOTSUP;
133 }
134 break;
135 #endif /* STM32_SRC_LSI */
136 #if defined(STM32_SRC_HSI14)
137 case STM32_SRC_HSI14:
138 if (!IS_ENABLED(STM32_HSI14_ENABLED)) {
139 r = -ENOTSUP;
140 }
141 break;
142 #endif /* STM32_SRC_HSI14 */
143 #if defined(STM32_SRC_HSI48)
144 case STM32_SRC_HSI48:
145 if (!IS_ENABLED(STM32_HSI48_ENABLED)) {
146 r = -ENOTSUP;
147 }
148 break;
149 #endif /* STM32_SRC_HSI48 */
150 #if defined(STM32_SRC_MSI)
151 case STM32_SRC_MSI:
152 if (!IS_ENABLED(STM32_MSI_ENABLED)) {
153 r = -ENOTSUP;
154 }
155 break;
156 #endif /* STM32_SRC_MSI */
157 #if defined(STM32_SRC_PLLCLK)
158 case STM32_SRC_PLLCLK:
159 if (!IS_ENABLED(STM32_PLL_ENABLED)) {
160 r = -ENOTSUP;
161 }
162 break;
163 #endif /* STM32_SRC_PLLCLK */
164 #if defined(STM32_SRC_PLL_P)
165 case STM32_SRC_PLL_P:
166 if (!IS_ENABLED(STM32_PLL_P_ENABLED)) {
167 r = -ENOTSUP;
168 }
169 break;
170 #endif /* STM32_SRC_PLL_P */
171 #if defined(STM32_SRC_PLL_Q)
172 case STM32_SRC_PLL_Q:
173 if (!IS_ENABLED(STM32_PLL_Q_ENABLED)) {
174 r = -ENOTSUP;
175 }
176 break;
177 #endif /* STM32_SRC_PLL_Q */
178 #if defined(STM32_SRC_PLL_R)
179 case STM32_SRC_PLL_R:
180 if (!IS_ENABLED(STM32_PLL_R_ENABLED)) {
181 r = -ENOTSUP;
182 }
183 break;
184 #endif /* STM32_SRC_PLL_R */
185 #if defined(STM32_SRC_PLLI2S_R)
186 case STM32_SRC_PLLI2S_R:
187 if (!IS_ENABLED(STM32_PLLI2S_R_ENABLED)) {
188 r = -ENOTSUP;
189 }
190 break;
191 #endif /* STM32_SRC_PLLI2S_R */
192 default:
193 return -ENOTSUP;
194 }
195
196 return r;
197 }
198
stm32_clock_control_on(const struct device * dev,clock_control_subsys_t sub_system)199 static inline int stm32_clock_control_on(const struct device *dev,
200 clock_control_subsys_t sub_system)
201 {
202 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
203
204 ARG_UNUSED(dev);
205
206 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
207 /* Attemp to change a wrong periph clock bit */
208 return -ENOTSUP;
209 }
210
211 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
212 pclken->enr);
213
214 return 0;
215 }
216
stm32_clock_control_off(const struct device * dev,clock_control_subsys_t sub_system)217 static inline int stm32_clock_control_off(const struct device *dev,
218 clock_control_subsys_t sub_system)
219 {
220 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
221
222 ARG_UNUSED(dev);
223
224 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
225 /* Attemp to toggle a wrong periph clock bit */
226 return -ENOTSUP;
227 }
228
229 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
230 pclken->enr);
231
232 return 0;
233 }
234
stm32_clock_control_configure(const struct device * dev,clock_control_subsys_t sub_system,void * data)235 static inline int stm32_clock_control_configure(const struct device *dev,
236 clock_control_subsys_t sub_system,
237 void *data)
238 {
239 #if defined(STM32_SRC_SYSCLK)
240 /* At least one alt src clock available */
241 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
242 int err;
243
244 ARG_UNUSED(dev);
245 ARG_UNUSED(data);
246
247 err = enabled_clock(pclken->bus);
248 if (err < 0) {
249 /* Attempt to configure a src clock not available or not valid */
250 return err;
251 }
252
253 if (pclken->enr == NO_SEL) {
254 /* Domain clock is fixed. Nothing to set. Exit */
255 return 0;
256 }
257
258 sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
259 STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
260 sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
261 STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
262
263 return 0;
264 #else
265 /* No src clock available: Not supported */
266 return -ENOTSUP;
267 #endif
268 }
269
stm32_clock_control_get_subsys_rate(const struct device * clock,clock_control_subsys_t sub_system,uint32_t * rate)270 static int stm32_clock_control_get_subsys_rate(const struct device *clock,
271 clock_control_subsys_t sub_system,
272 uint32_t *rate)
273 {
274 struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
275 /*
276 * Get AHB Clock (= SystemCoreClock = SYSCLK/prescaler)
277 * SystemCoreClock is preferred to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
278 * since it will be updated after clock configuration and hence
279 * more likely to contain actual clock speed
280 */
281 uint32_t ahb_clock = SystemCoreClock;
282 uint32_t apb1_clock = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
283 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), apb2_prescaler)
284 uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
285 #elif defined(STM32_CLOCK_BUS_APB2)
286 /* APB2 bus exists, but w/o dedicated prescaler */
287 uint32_t apb2_clock = apb1_clock;
288 #endif
289 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
290 uint32_t ahb3_clock = get_bus_clock(ahb_clock * STM32_CPU1_PRESCALER,
291 STM32_AHB3_PRESCALER);
292 #elif defined(STM32_CLOCK_BUS_AHB3)
293 /* AHB3 bus exists, but w/o dedicated prescaler */
294 uint32_t ahb3_clock = ahb_clock;
295 #endif
296
297 #if defined(STM32_SRC_PCLK)
298 if (pclken->bus == STM32_SRC_PCLK) {
299 /* STM32_SRC_PCLK can't be used to request a subsys freq */
300 /* Use STM32_CLOCK_BUS_FOO instead. */
301 return -ENOTSUP;
302 }
303 #endif
304
305 ARG_UNUSED(clock);
306
307 switch (pclken->bus) {
308 case STM32_CLOCK_BUS_AHB1:
309 #if defined(STM32_CLOCK_BUS_AHB2)
310 case STM32_CLOCK_BUS_AHB2:
311 #endif
312 #if defined(STM32_CLOCK_BUS_IOP)
313 case STM32_CLOCK_BUS_IOP:
314 #endif
315 *rate = ahb_clock;
316 break;
317 #if defined(STM32_CLOCK_BUS_AHB3)
318 case STM32_CLOCK_BUS_AHB3:
319 *rate = ahb3_clock;
320 break;
321 #endif
322 case STM32_CLOCK_BUS_APB1:
323 #if defined(STM32_CLOCK_BUS_APB1_2)
324 case STM32_CLOCK_BUS_APB1_2:
325 #endif
326 *rate = apb1_clock;
327 break;
328 #if defined(STM32_CLOCK_BUS_APB2)
329 case STM32_CLOCK_BUS_APB2:
330 *rate = apb2_clock;
331 break;
332 #endif
333 #if defined(STM32_CLOCK_BUS_APB3)
334 case STM32_CLOCK_BUS_APB3:
335 /* STM32WL: AHB3 and APB3 share the same clock and prescaler. */
336 *rate = ahb3_clock;
337 break;
338 #endif
339 #if defined(STM32_SRC_SYSCLK)
340 case STM32_SRC_SYSCLK:
341 *rate = SystemCoreClock * STM32_CORE_PRESCALER;
342 break;
343 #endif
344 #if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL)
345 case STM32_SRC_PLLCLK:
346 if (get_pllout_frequency() == 0) {
347 return -EIO;
348 }
349 *rate = get_pllout_frequency();
350 break;
351 #endif
352 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
353 case STM32_SRC_PLL_P:
354 *rate = get_pll_div_frequency(get_pllsrc_frequency(),
355 STM32_PLL_M_DIVISOR,
356 STM32_PLL_N_MULTIPLIER,
357 STM32_PLL_P_DIVISOR);
358 break;
359 #endif
360 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
361 case STM32_SRC_PLL_Q:
362 *rate = get_pll_div_frequency(get_pllsrc_frequency(),
363 STM32_PLL_M_DIVISOR,
364 STM32_PLL_N_MULTIPLIER,
365 STM32_PLL_Q_DIVISOR);
366 break;
367 #endif
368 #if defined(STM32_SRC_PLL_R) & STM32_PLL_R_ENABLED
369 case STM32_SRC_PLL_R:
370 *rate = get_pll_div_frequency(get_pllsrc_frequency(),
371 STM32_PLL_M_DIVISOR,
372 STM32_PLL_N_MULTIPLIER,
373 STM32_PLL_R_DIVISOR);
374 break;
375 #endif
376 #if defined(STM32_SRC_PLLI2S_R) & STM32_PLLI2S_ENABLED
377 case STM32_SRC_PLLI2S_R:
378 *rate = get_pll_div_frequency(get_pllsrc_frequency(),
379 STM32_PLLI2S_M_DIVISOR,
380 STM32_PLLI2S_N_MULTIPLIER,
381 STM32_PLLI2S_R_DIVISOR);
382 break;
383 #endif /* STM32_SRC_PLLI2S_R */
384 /* PLLSAI1x not supported yet */
385 /* PLLSAI2x not supported yet */
386 #if defined(STM32_SRC_LSE)
387 case STM32_SRC_LSE:
388 *rate = STM32_LSE_FREQ;
389 break;
390 #endif
391 #if defined(STM32_SRC_LSI)
392 case STM32_SRC_LSI:
393 *rate = STM32_LSI_FREQ;
394 break;
395 #endif
396 #if defined(STM32_SRC_HSI)
397 case STM32_SRC_HSI:
398 *rate = STM32_HSI_FREQ;
399 break;
400 #endif
401 #if defined(STM32_SRC_MSI)
402 case STM32_SRC_MSI:
403 *rate = get_msi_frequency();
404 break;
405 #endif
406 #if defined(STM32_SRC_HSE)
407 case STM32_SRC_HSE:
408 *rate = STM32_HSE_FREQ;
409 break;
410 #endif
411 #if defined(STM32_HSI48_ENABLED)
412 case STM32_SRC_HSI48:
413 *rate = STM32_HSI48_FREQ;
414 break;
415 #endif /* STM32_HSI48_ENABLED */
416 default:
417 return -ENOTSUP;
418 }
419
420 return 0;
421 }
422
stm32_clock_control_get_status(const struct device * dev,clock_control_subsys_t sub_system)423 static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
424 clock_control_subsys_t sub_system)
425 {
426 struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
427
428 ARG_UNUSED(dev);
429
430 if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
431 /* Gated clocks */
432 if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
433 == pclken->enr) {
434 return CLOCK_CONTROL_STATUS_ON;
435 } else {
436 return CLOCK_CONTROL_STATUS_OFF;
437 }
438 } else {
439 /* Domain clock sources */
440 if (enabled_clock(pclken->bus) == 0) {
441 return CLOCK_CONTROL_STATUS_ON;
442 } else {
443 return CLOCK_CONTROL_STATUS_OFF;
444 }
445 }
446 }
447
448 static struct clock_control_driver_api stm32_clock_control_api = {
449 .on = stm32_clock_control_on,
450 .off = stm32_clock_control_off,
451 .get_rate = stm32_clock_control_get_subsys_rate,
452 .get_status = stm32_clock_control_get_status,
453 .configure = stm32_clock_control_configure,
454 };
455
456 /*
457 * Unconditionally switch the system clock source to HSI.
458 */
459 __unused
stm32_clock_switch_to_hsi(void)460 static void stm32_clock_switch_to_hsi(void)
461 {
462 /* Enable HSI if not enabled */
463 if (LL_RCC_HSI_IsReady() != 1) {
464 /* Enable HSI */
465 LL_RCC_HSI_Enable();
466 while (LL_RCC_HSI_IsReady() != 1) {
467 /* Wait for HSI ready */
468 }
469 }
470
471 /* Set HSI as SYSCLCK source */
472 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
473 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
474 }
475 }
476
477 __unused
set_up_plls(void)478 static void set_up_plls(void)
479 {
480 #if defined(STM32_PLL_ENABLED)
481
482 /*
483 * Case of chain-loaded applications:
484 * Switch to HSI and disable the PLL before configuration.
485 * (Switching to HSI makes sure we have a SYSCLK source in
486 * case we're currently running from the PLL we're about to
487 * turn off and reconfigure.)
488 *
489 */
490 if (LL_RCC_GetSysClkSource() == LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
491 stm32_clock_switch_to_hsi();
492 LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
493 }
494 LL_RCC_PLL_Disable();
495
496 #endif
497
498 #if defined(STM32_PLL2_ENABLED)
499 /*
500 * Disable PLL2 after switching to HSI for SysClk
501 * and disabling PLL, but before enabling PLL again,
502 * since PLL source can be PLL2.
503 */
504 LL_RCC_PLL2_Disable();
505
506 config_pll2();
507
508 /* Enable PLL2 */
509 LL_RCC_PLL2_Enable();
510 while (LL_RCC_PLL2_IsReady() != 1U) {
511 /* Wait for PLL2 ready */
512 }
513 #endif /* STM32_PLL2_ENABLED */
514
515 #if defined(STM32_PLL_ENABLED)
516
517 #if defined(STM32_SRC_PLL_P) & STM32_PLL_P_ENABLED
518 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLP, pllp(STM32_PLL_P_DIVISOR));
519 RCC_PLLP_ENABLE();
520 #endif
521 #if defined(STM32_SRC_PLL_Q) & STM32_PLL_Q_ENABLED
522 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ, pllq(STM32_PLL_Q_DIVISOR));
523 RCC_PLLQ_ENABLE();
524 #endif
525
526 config_pll_sysclock();
527
528 /* Enable PLL */
529 LL_RCC_PLL_Enable();
530 while (LL_RCC_PLL_IsReady() != 1U) {
531 /* Wait for PLL ready */
532 }
533
534 #endif /* STM32_PLL_ENABLED */
535
536 #if defined(STM32_PLLI2S_ENABLED)
537 config_plli2s();
538
539 /* Enable PLL */
540 LL_RCC_PLLI2S_Enable();
541 while (LL_RCC_PLLI2S_IsReady() != 1U) {
542 /* Wait for PLL ready */
543 }
544 #endif /* STM32_PLLI2S_ENABLED */
545 }
546
set_up_fixed_clock_sources(void)547 static void set_up_fixed_clock_sources(void)
548 {
549
550 if (IS_ENABLED(STM32_HSE_ENABLED)) {
551 #if defined(STM32_HSE_BYPASS)
552 /* Check if need to enable HSE bypass feature or not */
553 if (IS_ENABLED(STM32_HSE_BYPASS)) {
554 LL_RCC_HSE_EnableBypass();
555 } else {
556 LL_RCC_HSE_DisableBypass();
557 }
558 #endif
559 #if STM32_HSE_TCXO
560 LL_RCC_HSE_EnableTcxo();
561 #endif
562 #if STM32_HSE_DIV2
563 LL_RCC_HSE_EnableDiv2();
564 #endif
565 /* Enable HSE */
566 LL_RCC_HSE_Enable();
567 while (LL_RCC_HSE_IsReady() != 1) {
568 /* Wait for HSE ready */
569 }
570 /* Check if we need to enable HSE clock security system or not */
571 #if STM32_HSE_CSS
572 z_arm_nmi_set_handler(HAL_RCC_NMI_IRQHandler);
573 LL_RCC_HSE_EnableCSS();
574 #endif /* STM32_HSE_CSS */
575 }
576
577 if (IS_ENABLED(STM32_HSI_ENABLED)) {
578 /* Enable HSI if not enabled */
579 if (LL_RCC_HSI_IsReady() != 1) {
580 /* Enable HSI */
581 LL_RCC_HSI_Enable();
582 while (LL_RCC_HSI_IsReady() != 1) {
583 /* Wait for HSI ready */
584 }
585 }
586 #if STM32_HSI_DIV_ENABLED
587 LL_RCC_SetHSIDiv(hsi_divider(STM32_HSI_DIVISOR));
588 #endif
589 }
590
591 #if defined(STM32_MSI_ENABLED)
592 if (IS_ENABLED(STM32_MSI_ENABLED)) {
593 /* Set MSI Range */
594 #if defined(RCC_CR_MSIRGSEL)
595 LL_RCC_MSI_EnableRangeSelection();
596 #endif /* RCC_CR_MSIRGSEL */
597
598 #if defined(CONFIG_SOC_SERIES_STM32L0X) || defined(CONFIG_SOC_SERIES_STM32L1X)
599 LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_ICSCR_MSIRANGE_Pos);
600 #else
601 LL_RCC_MSI_SetRange(STM32_MSI_RANGE << RCC_CR_MSIRANGE_Pos);
602 #endif /* CONFIG_SOC_SERIES_STM32L0X || CONFIG_SOC_SERIES_STM32L1X */
603
604 #if STM32_MSI_PLL_MODE
605 /* Enable MSI hardware auto calibration */
606 LL_RCC_MSI_EnablePLLMode();
607 #endif
608
609 LL_RCC_MSI_SetCalibTrimming(0);
610
611 /* Enable MSI if not enabled */
612 if (LL_RCC_MSI_IsReady() != 1) {
613 /* Enable MSI */
614 LL_RCC_MSI_Enable();
615 while (LL_RCC_MSI_IsReady() != 1) {
616 /* Wait for MSI ready */
617 }
618 }
619 }
620 #endif /* STM32_MSI_ENABLED */
621
622 if (IS_ENABLED(STM32_LSI_ENABLED)) {
623 #if defined(CONFIG_SOC_SERIES_STM32WBX)
624 LL_RCC_LSI1_Enable();
625 while (LL_RCC_LSI1_IsReady() != 1) {
626 }
627 #else
628 LL_RCC_LSI_Enable();
629 while (LL_RCC_LSI_IsReady() != 1) {
630 }
631 #endif
632 }
633
634 if (IS_ENABLED(STM32_LSE_ENABLED)) {
635 /* LSE belongs to the back-up domain, enable access.*/
636
637 z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
638
639 #if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPR_DBP)
640 /* Set the DBP bit in the Power control register 1 (PWR_CR1) */
641 LL_PWR_EnableBkUpAccess();
642 while (!LL_PWR_IsEnabledBkUpAccess()) {
643 /* Wait for Backup domain access */
644 }
645 #endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */
646
647 #if STM32_LSE_DRIVING
648 /* Configure driving capability */
649 LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_BDCR_LSEDRV_Pos);
650 #endif
651
652 if (IS_ENABLED(STM32_LSE_BYPASS)) {
653 /* Configure LSE bypass */
654 LL_RCC_LSE_EnableBypass();
655 }
656
657 /* Enable LSE Oscillator (32.768 kHz) */
658 LL_RCC_LSE_Enable();
659 while (!LL_RCC_LSE_IsReady()) {
660 /* Wait for LSE ready */
661 }
662
663 #ifdef RCC_BDCR_LSESYSEN
664 LL_RCC_LSE_EnablePropagation();
665 /* Wait till LSESYS is ready */
666 while (!LL_RCC_LSE_IsPropagationReady()) {
667 }
668 #endif /* RCC_BDCR_LSESYSEN */
669
670 #if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPR_DBP)
671 LL_PWR_DisableBkUpAccess();
672 #endif /* PWR_CR_DBP || PWR_CR1_DBP || PWR_DBPR_DBP */
673
674 z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
675 }
676
677 #if defined(STM32_HSI14_ENABLED)
678 /* For all series with HSI 14 clock support */
679 if (IS_ENABLED(STM32_HSI14_ENABLED)) {
680 LL_RCC_HSI14_Enable();
681 while (LL_RCC_HSI14_IsReady() != 1) {
682 }
683 }
684 #endif /* STM32_HSI48_ENABLED */
685
686 #if defined(STM32_HSI48_ENABLED)
687 /* For all series with HSI 48 clock support */
688 if (IS_ENABLED(STM32_HSI48_ENABLED)) {
689 #if defined(CONFIG_SOC_SERIES_STM32L0X)
690 /*
691 * HSI48 requires VREFINT (see RM0376 section 7.2.4).
692 * The SYSCFG is needed to control VREFINT, so clock it.
693 */
694 LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_SYSCFG);
695 LL_SYSCFG_VREFINT_EnableHSI48();
696 #endif /* CONFIG_SOC_SERIES_STM32L0X */
697
698 /*
699 * STM32WB: Lock the CLK48 HSEM and do not release to prevent
700 * M0 core to disable this clock (used for RNG on M0).
701 * No-op on other series.
702 */
703 z_stm32_hsem_lock(CFG_HW_CLK48_CONFIG_SEMID, HSEM_LOCK_DEFAULT_RETRY);
704
705 LL_RCC_HSI48_Enable();
706 while (LL_RCC_HSI48_IsReady() != 1) {
707 }
708 }
709 #endif /* STM32_HSI48_ENABLED */
710 }
711
712 /**
713 * @brief Initialize clocks for the stm32
714 *
715 * This routine is called to enable and configure the clocks and PLL
716 * of the soc on the board. It depends on the board definition.
717 * This function is called on the startup and also to restore the config
718 * when exiting for low power mode.
719 *
720 * @param dev clock device struct
721 *
722 * @return 0
723 */
stm32_clock_control_init(const struct device * dev)724 int stm32_clock_control_init(const struct device *dev)
725 {
726 ARG_UNUSED(dev);
727
728 /* Some clocks would be activated by default */
729 config_enable_default_clocks();
730
731 #if defined(FLASH_ACR_LATENCY)
732 uint32_t old_flash_freq;
733 uint32_t new_flash_freq;
734
735 old_flash_freq = RCC_CALC_FLASH_FREQ(HAL_RCC_GetSysClockFreq(),
736 GET_CURRENT_FLASH_PRESCALER());
737
738 new_flash_freq = RCC_CALC_FLASH_FREQ(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
739 STM32_FLASH_PRESCALER);
740
741 /* If HCLK increases, set flash latency before any clock setting */
742 if (old_flash_freq < new_flash_freq) {
743 LL_SetFlashLatency(new_flash_freq);
744 }
745 #endif /* FLASH_ACR_LATENCY */
746
747 /* Set up indiviual enabled clocks */
748 set_up_fixed_clock_sources();
749
750 /* Set up PLLs */
751 set_up_plls();
752
753 if (DT_PROP(DT_NODELABEL(rcc), undershoot_prevention) &&
754 (STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1) &&
755 (MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
756 LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_2);
757 } else {
758 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));
759 }
760
761 #if STM32_SYSCLK_SRC_PLL
762 /* Set PLL as System Clock Source */
763 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
764 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) {
765 }
766 #elif STM32_SYSCLK_SRC_HSE
767 /* Set HSE as SYSCLCK source */
768 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
769 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
770 }
771 #elif STM32_SYSCLK_SRC_MSI
772 /* Set MSI as SYSCLCK source */
773 LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_MSI);
774 while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_MSI) {
775 }
776 #elif STM32_SYSCLK_SRC_HSI
777 stm32_clock_switch_to_hsi();
778 #endif /* STM32_SYSCLK_SRC_... */
779
780 if (DT_PROP(DT_NODELABEL(rcc), undershoot_prevention) &&
781 (STM32_CORE_PRESCALER == LL_RCC_SYSCLK_DIV_1) &&
782 (MHZ(80) < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC)) {
783 LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CORE_PRESCALER));
784 }
785
786 #if defined(FLASH_ACR_LATENCY)
787 /* If HCLK not increased, set flash latency after all clock setting */
788 if (old_flash_freq >= new_flash_freq) {
789 LL_SetFlashLatency(new_flash_freq);
790 }
791 #endif /* FLASH_ACR_LATENCY */
792
793 SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
794
795 /* Set bus prescalers prescaler */
796 LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
797 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), apb2_prescaler)
798 LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
799 #endif
800 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), cpu2_prescaler)
801 LL_C2_RCC_SetAHBPrescaler(ahb_prescaler(STM32_CPU2_PRESCALER));
802 #endif
803 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
804 LL_RCC_SetAHB3Prescaler(ahb_prescaler(STM32_AHB3_PRESCALER));
805 #endif
806 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), ahb4_prescaler)
807 LL_RCC_SetAHB4Prescaler(ahb_prescaler(STM32_AHB4_PRESCALER));
808 #endif
809 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc_prescaler)
810 LL_RCC_SetADCClockSource(adc_prescaler(STM32_ADC_PRESCALER));
811 #endif
812 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc12_prescaler)
813 LL_RCC_SetADCClockSource(adc_prescaler(STM32_ADC12_PRESCALER));
814 #endif
815 #if DT_NODE_HAS_PROP(DT_NODELABEL(rcc), adc34_prescaler)
816 LL_RCC_SetADCClockSource(adc_prescaler(STM32_ADC34_PRESCALER));
817 #endif
818
819 /* configure MCO1/MCO2 based on Kconfig */
820 stm32_clock_control_mco_init();
821
822 return 0;
823 }
824
825 #if defined(STM32_HSE_CSS)
stm32_hse_css_callback(void)826 void __weak stm32_hse_css_callback(void) {}
827
828 /* Called by the HAL in response to an HSE CSS interrupt */
HAL_RCC_CSSCallback(void)829 void HAL_RCC_CSSCallback(void)
830 {
831 stm32_hse_css_callback();
832 }
833 #endif
834
835 /**
836 * @brief RCC device, note that priority is intentionally set to 1 so
837 * that the device init runs just after SOC init
838 */
839 DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
840 &stm32_clock_control_init,
841 NULL,
842 NULL, NULL,
843 PRE_KERNEL_1,
844 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
845 &stm32_clock_control_api);
846
