1 /*
2 * Copyright (c) 2018 Foundries.io
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT openisa_rv32m1_pcc
8 #include <errno.h>
9 #include <soc.h>
10 #include <zephyr/drivers/clock_control.h>
11 #include <fsl_clock.h>
12
13 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
14 #include <zephyr/logging/log.h>
15 LOG_MODULE_REGISTER(clock_control);
16
17 struct rv32m1_pcc_config {
18 uint32_t base_address;
19 };
20
21 #define DEV_BASE(dev) \
22 (((struct rv32m1_pcc_config *)(dev->config))->base_address)
23
clock_ip(const struct device * dev,clock_control_subsys_t sub_system)24 static inline clock_ip_name_t clock_ip(const struct device *dev,
25 clock_control_subsys_t sub_system)
26 {
27 uint32_t offset = POINTER_TO_UINT(sub_system);
28
29 return MAKE_PCC_REGADDR(DEV_BASE(dev), offset);
30 }
31
rv32m1_pcc_on(const struct device * dev,clock_control_subsys_t sub_system)32 static int rv32m1_pcc_on(const struct device *dev,
33 clock_control_subsys_t sub_system)
34 {
35 CLOCK_EnableClock(clock_ip(dev, sub_system));
36 return 0;
37 }
38
rv32m1_pcc_off(const struct device * dev,clock_control_subsys_t sub_system)39 static int rv32m1_pcc_off(const struct device *dev,
40 clock_control_subsys_t sub_system)
41 {
42 CLOCK_DisableClock(clock_ip(dev, sub_system));
43 return 0;
44 }
45
rv32m1_pcc_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)46 static int rv32m1_pcc_get_rate(const struct device *dev,
47 clock_control_subsys_t sub_system,
48 uint32_t *rate)
49 {
50 *rate = CLOCK_GetIpFreq(clock_ip(dev, sub_system));
51 return 0;
52 }
53
54 static const struct clock_control_driver_api rv32m1_pcc_api = {
55 .on = rv32m1_pcc_on,
56 .off = rv32m1_pcc_off,
57 .get_rate = rv32m1_pcc_get_rate,
58 };
59
60 #define RV32M1_PCC_INIT(inst) \
61 static struct rv32m1_pcc_config rv32m1_pcc##inst##_config = { \
62 .base_address = DT_INST_REG_ADDR(inst) \
63 }; \
64 \
65 DEVICE_DT_INST_DEFINE(inst, \
66 NULL, \
67 NULL, \
68 NULL, &rv32m1_pcc##inst##_config, \
69 PRE_KERNEL_1, \
70 CONFIG_CLOCK_CONTROL_INIT_PRIORITY, \
71 &rv32m1_pcc_api);
72
73 DT_INST_FOREACH_STATUS_OKAY(RV32M1_PCC_INIT)
74
