1 /*
2 * Copyright (c) 2019 Vestas Wind Systems A/S
3 *
4 * Based on clock_control_mcux_sim.c, which is:
5 * Copyright (c) 2017, NXP
6 *
7 * SPDX-License-Identifier: Apache-2.0
8 */
9
10 #define DT_DRV_COMPAT nxp_kinetis_mcg
11
12 #include <zephyr/drivers/clock_control.h>
13 #include <zephyr/dt-bindings/clock/kinetis_mcg.h>
14 #include <soc.h>
15 #include <fsl_clock.h>
16
17 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
18 #include <zephyr/logging/log.h>
19 LOG_MODULE_REGISTER(clock_control_mcg);
20
mcux_mcg_on(const struct device * dev,clock_control_subsys_t sub_system)21 static int mcux_mcg_on(const struct device *dev,
22 clock_control_subsys_t sub_system)
23 {
24 return 0;
25 }
26
mcux_mcg_off(const struct device * dev,clock_control_subsys_t sub_system)27 static int mcux_mcg_off(const struct device *dev,
28 clock_control_subsys_t sub_system)
29 {
30 return 0;
31 }
32
mcux_mcg_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)33 static int mcux_mcg_get_rate(const struct device *dev,
34 clock_control_subsys_t sub_system,
35 uint32_t *rate)
36 {
37 clock_name_t clock_name;
38
39 switch ((uint32_t) sub_system) {
40 #if defined(FSL_FEATURE_MCG_FFCLK_DIV) && (FSL_FEATURE_MCG_FFCLK_DIV)
41 case KINETIS_MCG_FIXED_FREQ_CLK:
42 clock_name = kCLOCK_McgFixedFreqClk;
43 break;
44 #endif
45 case KINETIS_MCG_OUT_CLK:
46 *rate = CLOCK_GetOutClkFreq();
47 return 0;
48 default:
49 LOG_ERR("Unsupported clock name");
50 return -EINVAL;
51 break;
52 }
53
54 *rate = CLOCK_GetFreq(clock_name);
55 return 0;
56 }
57
58 static const struct clock_control_driver_api mcux_mcg_driver_api = {
59 .on = mcux_mcg_on,
60 .off = mcux_mcg_off,
61 .get_rate = mcux_mcg_get_rate,
62 };
63
64 DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1,
65 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
66 &mcux_mcg_driver_api);
67
