1 /*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_ccm
8 #include <errno.h>
9 #include <zephyr/arch/cpu.h>
10 #include <zephyr/sys/util.h>
11 #include <zephyr/drivers/clock_control.h>
12 #include <zephyr/dt-bindings/clock/imx_ccm.h>
13 #include <fsl_clock.h>
14
15 #if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP)
16 #include <main/ipc.h>
17 #endif
18
19 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
20 #include <zephyr/logging/log.h>
21 LOG_MODULE_REGISTER(clock_control);
22
23 #ifdef CONFIG_SPI_MCUX_LPSPI
24 static const clock_name_t lpspi_clocks[] = {
25 kCLOCK_Usb1PllPfd1Clk,
26 kCLOCK_Usb1PllPfd0Clk,
27 kCLOCK_SysPllClk,
28 kCLOCK_SysPllPfd2Clk,
29 };
30 #endif
31 #ifdef CONFIG_UART_MCUX_IUART
32 static const clock_root_control_t uart_clk_root[] = {
33 kCLOCK_RootUart1,
34 kCLOCK_RootUart2,
35 kCLOCK_RootUart3,
36 kCLOCK_RootUart4,
37 };
38
39 static const clock_ip_name_t uart_clocks[] = {
40 kCLOCK_Uart1,
41 kCLOCK_Uart2,
42 kCLOCK_Uart3,
43 kCLOCK_Uart4,
44 };
45 #endif
46
47 #ifdef CONFIG_UART_MCUX_LPUART
48
49 #ifdef CONFIG_SOC_MIMX8QM_ADSP
50 static const clock_ip_name_t lpuart_clocks[] = {
51 kCLOCK_DMA_Lpuart0,
52 kCLOCK_DMA_Lpuart1,
53 kCLOCK_DMA_Lpuart2,
54 kCLOCK_DMA_Lpuart3,
55 kCLOCK_DMA_Lpuart4,
56 };
57
58 static const uint32_t lpuart_rate = MHZ(80);
59 #endif /* CONFIG_SOC_MIMX8QM_ADSP */
60
61 #ifdef CONFIG_SOC_MIMX8QXP_ADSP
62 static const clock_ip_name_t lpuart_clocks[] = {
63 kCLOCK_DMA_Lpuart0,
64 kCLOCK_DMA_Lpuart1,
65 kCLOCK_DMA_Lpuart2,
66 kCLOCK_DMA_Lpuart3,
67 };
68
69 static const uint32_t lpuart_rate = MHZ(80);
70 #endif /* CONFIG_SOC_MIMX8QXP_ADSP */
71
72 #endif /* CONFIG_UART_MCUX_LPUART */
73
74
mcux_ccm_on(const struct device * dev,clock_control_subsys_t sub_system)75 static int mcux_ccm_on(const struct device *dev,
76 clock_control_subsys_t sub_system)
77 {
78 uint32_t clock_name = (uintptr_t)sub_system;
79 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
80
81 switch (clock_name) {
82 #ifdef CONFIG_UART_MCUX_IUART
83 case IMX_CCM_UART1_CLK:
84 case IMX_CCM_UART2_CLK:
85 case IMX_CCM_UART3_CLK:
86 case IMX_CCM_UART4_CLK:
87 CLOCK_EnableClock(uart_clocks[instance]);
88 return 0;
89 #endif
90
91 #if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QM_ADSP)
92 case IMX_CCM_LPUART1_CLK:
93 case IMX_CCM_LPUART2_CLK:
94 case IMX_CCM_LPUART3_CLK:
95 case IMX_CCM_LPUART4_CLK:
96 case IMX_CCM_LPUART5_CLK:
97 CLOCK_EnableClock(lpuart_clocks[instance]);
98 return 0;
99 #endif
100
101 #if defined(CONFIG_UART_MCUX_LPUART) && defined(CONFIG_SOC_MIMX8QXP_ADSP)
102 case IMX_CCM_LPUART1_CLK:
103 case IMX_CCM_LPUART2_CLK:
104 case IMX_CCM_LPUART3_CLK:
105 case IMX_CCM_LPUART4_CLK:
106 CLOCK_EnableClock(lpuart_clocks[instance]);
107 return 0;
108 #endif
109
110 #if defined(CONFIG_ETH_NXP_ENET)
111 case IMX_CCM_ENET_CLK:
112 CLOCK_EnableClock(kCLOCK_Enet);
113 return 0;
114 #endif
115 default:
116 (void)instance;
117 return 0;
118 }
119 }
120
mcux_ccm_off(const struct device * dev,clock_control_subsys_t sub_system)121 static int mcux_ccm_off(const struct device *dev,
122 clock_control_subsys_t sub_system)
123 {
124 uint32_t clock_name = (uintptr_t)sub_system;
125 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
126
127 switch (clock_name) {
128 #ifdef CONFIG_UART_MCUX_IUART
129 case IMX_CCM_UART1_CLK:
130 case IMX_CCM_UART2_CLK:
131 case IMX_CCM_UART3_CLK:
132 case IMX_CCM_UART4_CLK:
133 CLOCK_DisableClock(uart_clocks[instance]);
134 return 0;
135 #endif
136 default:
137 (void)instance;
138 return 0;
139 }
140 }
141
mcux_ccm_get_subsys_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)142 static int mcux_ccm_get_subsys_rate(const struct device *dev,
143 clock_control_subsys_t sub_system,
144 uint32_t *rate)
145 {
146 uint32_t clock_name = (uintptr_t)sub_system;
147
148 switch (clock_name) {
149
150 #ifdef CONFIG_I2C_MCUX_LPI2C
151 case IMX_CCM_LPI2C_CLK:
152 if (CLOCK_GetMux(kCLOCK_Lpi2cMux) == 0) {
153 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
154 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
155 } else {
156 *rate = CLOCK_GetOscFreq()
157 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
158 }
159
160 break;
161 #endif
162
163 #ifdef CONFIG_SPI_MCUX_LPSPI
164 case IMX_CCM_LPSPI_CLK:
165 {
166 uint32_t lpspi_mux = CLOCK_GetMux(kCLOCK_LpspiMux);
167 clock_name_t lpspi_clock = lpspi_clocks[lpspi_mux];
168
169 *rate = CLOCK_GetFreq(lpspi_clock)
170 / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1);
171 break;
172 }
173 #endif
174
175 #ifdef CONFIG_UART_MCUX_LPUART
176
177 #if defined(CONFIG_SOC_MIMX8QM_ADSP)
178 case IMX_CCM_LPUART1_CLK:
179 case IMX_CCM_LPUART2_CLK:
180 case IMX_CCM_LPUART3_CLK:
181 case IMX_CCM_LPUART4_CLK:
182 case IMX_CCM_LPUART5_CLK:
183 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
184
185 CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
186 *rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
187 break;
188
189 #elif defined(CONFIG_SOC_MIMX8QXP_ADSP)
190 case IMX_CCM_LPUART1_CLK:
191 case IMX_CCM_LPUART2_CLK:
192 case IMX_CCM_LPUART3_CLK:
193 case IMX_CCM_LPUART4_CLK:
194 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
195
196 CLOCK_SetIpFreq(lpuart_clocks[instance], lpuart_rate);
197 *rate = CLOCK_GetIpFreq(lpuart_clocks[instance]);
198 break;
199
200 #else
201 case IMX_CCM_LPUART_CLK:
202 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
203 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
204 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
205 } else {
206 *rate = CLOCK_GetOscFreq()
207 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
208 }
209
210 break;
211 #endif
212 #endif
213
214 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
215 case IMX_CCM_USDHC1_CLK:
216 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
217 (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
218 break;
219 #endif
220
221 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC
222 case IMX_CCM_USDHC2_CLK:
223 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
224 (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U);
225 break;
226 #endif
227
228 #ifdef CONFIG_DMA_MCUX_EDMA
229 case IMX_CCM_EDMA_CLK:
230 *rate = CLOCK_GetIpgFreq();
231 break;
232 #endif
233
234 #ifdef CONFIG_PWM_MCUX
235 case IMX_CCM_PWM_CLK:
236 *rate = CLOCK_GetIpgFreq();
237 break;
238 #endif
239
240 #ifdef CONFIG_ETH_NXP_ENET
241 case IMX_CCM_ENET_CLK:
242 *rate = CLOCK_GetIpgFreq();
243 break;
244 #endif
245 #ifdef CONFIG_PTP_CLOCK_NXP_ENET
246 case IMX_CCM_ENET_PLL:
247 *rate = CLOCK_GetPllFreq(kCLOCK_PllEnet);
248 break;
249 #endif
250
251 #ifdef CONFIG_UART_MCUX_IUART
252 case IMX_CCM_UART1_CLK:
253 case IMX_CCM_UART2_CLK:
254 case IMX_CCM_UART3_CLK:
255 case IMX_CCM_UART4_CLK:
256 {
257 uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
258 clock_root_control_t clk_root = uart_clk_root[instance];
259 uint32_t uart_mux = CLOCK_GetRootMux(clk_root);
260
261 if (uart_mux == 0) {
262 *rate = MHZ(24);
263 } else if (uart_mux == 1) {
264 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
265 (CLOCK_GetRootPreDivider(clk_root)) /
266 (CLOCK_GetRootPostDivider(clk_root)) /
267 10;
268 }
269
270 } break;
271 #endif
272
273 #ifdef CONFIG_CAN_MCUX_FLEXCAN
274 case IMX_CCM_CAN_CLK:
275 {
276 uint32_t can_mux = CLOCK_GetMux(kCLOCK_CanMux);
277
278 if (can_mux == 0) {
279 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
280 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
281 } else if (can_mux == 1) {
282 *rate = CLOCK_GetOscFreq()
283 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
284 } else {
285 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
286 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
287 }
288 } break;
289 #endif
290
291 #ifdef CONFIG_COUNTER_MCUX_GPT
292 case IMX_CCM_GPT_CLK:
293 *rate = CLOCK_GetFreq(kCLOCK_PerClk);
294 break;
295 #endif
296
297 #ifdef CONFIG_COUNTER_MCUX_QTMR
298 case IMX_CCM_QTMR_CLK:
299 *rate = CLOCK_GetIpgFreq();
300 break;
301 #endif
302
303 #ifdef CONFIG_I2S_MCUX_SAI
304 case IMX_CCM_SAI1_CLK:
305 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
306 / (CLOCK_GetDiv(kCLOCK_Sai1PreDiv) + 1)
307 / (CLOCK_GetDiv(kCLOCK_Sai1Div) + 1);
308 break;
309 case IMX_CCM_SAI2_CLK:
310 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
311 / (CLOCK_GetDiv(kCLOCK_Sai2PreDiv) + 1)
312 / (CLOCK_GetDiv(kCLOCK_Sai2Div) + 1);
313 break;
314 case IMX_CCM_SAI3_CLK:
315 *rate = CLOCK_GetFreq(kCLOCK_AudioPllClk)
316 / (CLOCK_GetDiv(kCLOCK_Sai3PreDiv) + 1)
317 / (CLOCK_GetDiv(kCLOCK_Sai3Div) + 1);
318 break;
319 #endif
320 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi), okay)
321 case IMX_CCM_FLEXSPI_CLK:
322 *rate = CLOCK_GetClockRootFreq(kCLOCK_FlexspiClkRoot);
323 break;
324 #endif
325 #if DT_NODE_HAS_STATUS(DT_NODELABEL(flexspi2), okay)
326 case IMX_CCM_FLEXSPI2_CLK:
327 *rate = CLOCK_GetClockRootFreq(kCLOCK_Flexspi2ClkRoot);
328 break;
329 #endif
330 }
331
332 return 0;
333 }
334
335 /*
336 * Since this function is used to reclock the FlexSPI when running in
337 * XIP, it must be located in RAM when MEMC Flexspi driver is enabled.
338 */
339 #ifdef CONFIG_MEMC_MCUX_FLEXSPI
340 #define CCM_SET_FUNC_ATTR __ramfunc
341 #else
342 #define CCM_SET_FUNC_ATTR
343 #endif
344
mcux_ccm_set_subsys_rate(const struct device * dev,clock_control_subsys_t subsys,clock_control_subsys_rate_t rate)345 static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
346 clock_control_subsys_t subsys,
347 clock_control_subsys_rate_t rate)
348 {
349 uint32_t clock_name = (uintptr_t)subsys;
350 uint32_t clock_rate = (uintptr_t)rate;
351
352 switch (clock_name) {
353 case IMX_CCM_FLEXSPI_CLK:
354 __fallthrough;
355 case IMX_CCM_FLEXSPI2_CLK:
356 #if defined(CONFIG_SOC_SERIES_IMX_RT10XX) && defined(CONFIG_MEMC_MCUX_FLEXSPI)
357 /* The SOC is using the FlexSPI for XIP. Therefore,
358 * the FlexSPI itself must be managed within the function,
359 * which is SOC specific.
360 */
361 return flexspi_clock_set_freq(clock_name, clock_rate);
362 #endif
363 default:
364 /* Silence unused variable warning */
365 ARG_UNUSED(clock_rate);
366 return -ENOTSUP;
367 }
368 }
369
370
371
372 static const struct clock_control_driver_api mcux_ccm_driver_api = {
373 .on = mcux_ccm_on,
374 .off = mcux_ccm_off,
375 .get_rate = mcux_ccm_get_subsys_rate,
376 .set_rate = mcux_ccm_set_subsys_rate,
377 };
378
mcux_ccm_init(const struct device * dev)379 static int mcux_ccm_init(const struct device *dev)
380 {
381 #if defined(CONFIG_SOC_MIMX8QM_ADSP) || defined(CONFIG_SOC_MIMX8QXP_ADSP)
382 sc_ipc_t ipc_handle;
383 int ret;
384
385 ret = sc_ipc_open(&ipc_handle, DT_REG_ADDR(DT_NODELABEL(scu_mu)));
386 if (ret != SC_ERR_NONE) {
387 return -ENODEV;
388 }
389
390 CLOCK_Init(ipc_handle);
391 #endif
392 return 0;
393 }
394
395 DEVICE_DT_INST_DEFINE(0, mcux_ccm_init, NULL, NULL, NULL,
396 PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
397 &mcux_ccm_driver_api);
398
