1 /*
2 * Copyright (c) 2017, NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_ccm
8 #include <errno.h>
9 #include <soc.h>
10 #include <drivers/clock_control.h>
11 #include <dt-bindings/clock/imx_ccm.h>
12 #include <fsl_clock.h>
13
14 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
15 #include <logging/log.h>
16 LOG_MODULE_REGISTER(clock_control);
17
18 #ifdef CONFIG_SPI_MCUX_LPSPI
19 static const clock_name_t lpspi_clocks[] = {
20 kCLOCK_Usb1PllPfd1Clk,
21 kCLOCK_Usb1PllPfd0Clk,
22 kCLOCK_SysPllClk,
23 kCLOCK_SysPllPfd2Clk,
24 };
25 #endif
26
mcux_ccm_on(const struct device * dev,clock_control_subsys_t sub_system)27 static int mcux_ccm_on(const struct device *dev,
28 clock_control_subsys_t sub_system)
29 {
30 return 0;
31 }
32
mcux_ccm_off(const struct device * dev,clock_control_subsys_t sub_system)33 static int mcux_ccm_off(const struct device *dev,
34 clock_control_subsys_t sub_system)
35 {
36 return 0;
37 }
38
mcux_ccm_get_subsys_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)39 static int mcux_ccm_get_subsys_rate(const struct device *dev,
40 clock_control_subsys_t sub_system,
41 uint32_t *rate)
42 {
43 uint32_t clock_name = (uint32_t) sub_system;
44
45 switch (clock_name) {
46
47 #ifdef CONFIG_I2C_MCUX_LPI2C
48 case IMX_CCM_LPI2C_CLK:
49 if (CLOCK_GetMux(kCLOCK_Lpi2cMux) == 0) {
50 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
51 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
52 } else {
53 *rate = CLOCK_GetOscFreq()
54 / (CLOCK_GetDiv(kCLOCK_Lpi2cDiv) + 1);
55 }
56
57 break;
58 #endif
59
60 #ifdef CONFIG_SPI_MCUX_LPSPI
61 case IMX_CCM_LPSPI_CLK:
62 {
63 uint32_t lpspi_mux = CLOCK_GetMux(kCLOCK_LpspiMux);
64 clock_name_t lpspi_clock = lpspi_clocks[lpspi_mux];
65
66 *rate = CLOCK_GetFreq(lpspi_clock)
67 / (CLOCK_GetDiv(kCLOCK_LpspiDiv) + 1);
68 break;
69 }
70 #endif
71
72 #ifdef CONFIG_UART_MCUX_LPUART
73 case IMX_CCM_LPUART_CLK:
74 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) {
75 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
76 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
77 } else {
78 *rate = CLOCK_GetOscFreq()
79 / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1);
80 }
81
82 break;
83 #endif
84
85 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_DISK_DRIVER_SDMMC
86 case IMX_CCM_USDHC1_CLK:
87 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
88 (CLOCK_GetDiv(kCLOCK_Usdhc1Div) + 1U);
89 break;
90 #endif
91
92 #if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_DISK_DRIVER_SDMMC
93 case IMX_CCM_USDHC2_CLK:
94 *rate = CLOCK_GetSysPfdFreq(kCLOCK_Pfd0) /
95 (CLOCK_GetDiv(kCLOCK_Usdhc2Div) + 1U);
96 break;
97 #endif
98
99 #ifdef CONFIG_DMA_MCUX_EDMA
100 case IMX_CCM_EDMA_CLK:
101 *rate = CLOCK_GetIpgFreq();
102 break;
103 #endif
104
105 #ifdef CONFIG_UART_MCUX_IUART
106 case IMX_CCM_UART_CLK:
107 *rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
108 (CLOCK_GetRootPreDivider(kCLOCK_RootUart4)) /
109 (CLOCK_GetRootPostDivider(kCLOCK_RootUart4)) /
110 10;
111 break;
112 #endif
113
114 #ifdef CONFIG_CAN_MCUX_FLEXCAN
115 case IMX_CCM_CAN_CLK:
116 {
117 uint32_t can_mux = CLOCK_GetMux(kCLOCK_CanMux);
118
119 if (can_mux == 0) {
120 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 8
121 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
122 } else if (can_mux == 1) {
123 *rate = CLOCK_GetOscFreq()
124 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
125 } else {
126 *rate = CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6
127 / (CLOCK_GetDiv(kCLOCK_CanDiv) + 1);
128 }
129 } break;
130 #endif
131
132 #ifdef CONFIG_COUNTER_MCUX_GPT
133 case IMX_CCM_GPT_CLK:
134 *rate = CLOCK_GetFreq(kCLOCK_PerClk);
135 break;
136 #endif
137
138 }
139
140 return 0;
141 }
142
mcux_ccm_init(const struct device * dev)143 static int mcux_ccm_init(const struct device *dev)
144 {
145 return 0;
146 }
147
148 static const struct clock_control_driver_api mcux_ccm_driver_api = {
149 .on = mcux_ccm_on,
150 .off = mcux_ccm_off,
151 .get_rate = mcux_ccm_get_subsys_rate,
152 };
153
154 DEVICE_DT_INST_DEFINE(0,
155 &mcux_ccm_init,
156 NULL,
157 NULL, NULL,
158 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
159 &mcux_ccm_driver_api);
160
