1 /*
2 * Copyright (c) 2020 Mohamed ElShahawi.
3 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT espressif_esp32_rtc
9
10 #define CPU_RESET_REASON RTC_SW_CPU_RESET
11
12 #if defined(CONFIG_SOC_SERIES_ESP32)
13 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx6
14 #undef CPU_RESET_REASON
15 #define CPU_RESET_REASON SW_CPU_RESET
16 #include <zephyr/dt-bindings/clock/esp32_clock.h>
17 #include "esp32/rom/rtc.h"
18 #include "soc/dport_reg.h"
19 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
20 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
21 #include <zephyr/dt-bindings/clock/esp32s2_clock.h>
22 #include "esp32s2/rom/rtc.h"
23 #include "soc/dport_reg.h"
24 #elif defined(CONFIG_SOC_SERIES_ESP32S3)
25 #define DT_CPU_COMPAT cdns_tensilica_xtensa_lx7
26 #include <zephyr/dt-bindings/clock/esp32s3_clock.h>
27 #include "esp32s3/rom/rtc.h"
28 #include "soc/dport_reg.h"
29 #include "esp32s3/clk.h"
30 #elif CONFIG_SOC_SERIES_ESP32C3
31 #define DT_CPU_COMPAT espressif_riscv
32 #include <zephyr/dt-bindings/clock/esp32c3_clock.h>
33 #include "esp32c3/rom/rtc.h"
34 #include <soc/soc_caps.h>
35 #include <soc/soc.h>
36 #include <soc/rtc.h>
37 #endif /* CONFIG_SOC_SERIES_ESP32xx */
38
39 #include "esp_rom_sys.h"
40 #include <soc/rtc.h>
41 #include <soc/i2s_reg.h>
42 #include <soc/apb_ctrl_reg.h>
43 #include <soc/timer_group_reg.h>
44 #include <hal/clk_gate_ll.h>
45 #include <soc.h>
46 #include <zephyr/drivers/clock_control.h>
47 #include <driver/periph_ctrl.h>
48 #include <hal/cpu_hal.h>
49
50 struct esp32_clock_config {
51 int clk_src_sel;
52 uint32_t cpu_freq;
53 uint32_t xtal_freq_sel;
54 int xtal_div;
55 };
56
57 static uint8_t const xtal_freq[] = {
58 #if defined(CONFIG_SOC_SERIES_ESP32) || \
59 defined(CONFIG_SOC_SERIES_ESP32S3)
60 [ESP32_CLK_XTAL_24M] = 24,
61 [ESP32_CLK_XTAL_26M] = 26,
62 [ESP32_CLK_XTAL_40M] = 40,
63 [ESP32_CLK_XTAL_AUTO] = 0
64 #elif defined(CONFIG_SOC_SERIES_ESP32S2)
65 [ESP32_CLK_XTAL_40M] = 40,
66 #elif defined(CONFIG_SOC_SERIES_ESP32C3)
67 [ESP32_CLK_XTAL_32M] = 32,
68 [ESP32_CLK_XTAL_40M] = 40,
69 #endif
70 };
71
clock_control_esp32_on(const struct device * dev,clock_control_subsys_t sys)72 static int clock_control_esp32_on(const struct device *dev,
73 clock_control_subsys_t sys)
74 {
75 ARG_UNUSED(dev);
76 periph_module_enable((periph_module_t)sys);
77 return 0;
78 }
79
clock_control_esp32_off(const struct device * dev,clock_control_subsys_t sys)80 static int clock_control_esp32_off(const struct device *dev,
81 clock_control_subsys_t sys)
82 {
83 ARG_UNUSED(dev);
84 periph_module_disable((periph_module_t)sys);
85 return 0;
86 }
87
clock_control_esp32_async_on(const struct device * dev,clock_control_subsys_t sys,clock_control_cb_t cb,void * user_data)88 static int clock_control_esp32_async_on(const struct device *dev,
89 clock_control_subsys_t sys,
90 clock_control_cb_t cb,
91 void *user_data)
92 {
93 ARG_UNUSED(dev);
94 ARG_UNUSED(sys);
95 ARG_UNUSED(cb);
96 ARG_UNUSED(user_data);
97 return -ENOTSUP;
98 }
99
clock_control_esp32_get_status(const struct device * dev,clock_control_subsys_t sys)100 static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
101 clock_control_subsys_t sys)
102 {
103 ARG_UNUSED(dev);
104 uint32_t clk_en_reg = periph_ll_get_clk_en_reg((periph_module_t)sys);
105 uint32_t clk_en_mask = periph_ll_get_clk_en_mask((periph_module_t)sys);
106
107 if (DPORT_GET_PERI_REG_MASK(clk_en_reg, clk_en_mask)) {
108 return CLOCK_CONTROL_STATUS_ON;
109 }
110 return CLOCK_CONTROL_STATUS_OFF;
111 }
112
clock_control_esp32_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)113 static int clock_control_esp32_get_rate(const struct device *dev,
114 clock_control_subsys_t sub_system,
115 uint32_t *rate)
116 {
117 ARG_UNUSED(sub_system);
118
119 rtc_cpu_freq_config_t config;
120
121 rtc_clk_cpu_freq_get_config(&config);
122
123 *rate = config.freq_mhz;
124
125 return 0;
126 }
127
128 #if defined(CONFIG_SOC_SERIES_ESP32)
esp32_clock_perip_init(void)129 static void esp32_clock_perip_init(void)
130 {
131 uint32_t common_perip_clk;
132 uint32_t hwcrypto_perip_clk;
133 uint32_t wifi_bt_sdio_clk;
134
135 #if !CONFIG_SMP
136 soc_reset_reason_t rst_reas[1];
137 #else
138 soc_reset_reason_t rst_reas[2];
139 #endif
140
141 rst_reas[0] = esp_rom_get_reset_reason(0);
142 #if CONFIG_SMP
143 rst_reas[1] = esp_rom_get_reset_reason(1);
144 #endif
145
146 /* For reason that only reset CPU, do not disable the clocks
147 * that have been enabled before reset.
148 */
149 if ((rst_reas[0] == RESET_REASON_CPU0_MWDT0 || rst_reas[0] == RESET_REASON_CPU0_SW ||
150 rst_reas[0] == RESET_REASON_CPU0_RTC_WDT)
151 #if CONFIG_SMP
152 || (rst_reas[1] == RESET_REASON_CPU1_MWDT1 || rst_reas[1] == RESET_REASON_CPU1_SW ||
153 rst_reas[1] == RESET_REASON_CPU1_RTC_WDT)
154 #endif
155 ) {
156 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
157 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERI_CLK_EN_REG);
158 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
159 } else {
160 common_perip_clk = DPORT_WDG_CLK_EN |
161 DPORT_PCNT_CLK_EN |
162 DPORT_LEDC_CLK_EN |
163 DPORT_TIMERGROUP1_CLK_EN |
164 DPORT_PWM0_CLK_EN |
165 DPORT_TWAI_CLK_EN |
166 DPORT_PWM1_CLK_EN |
167 DPORT_PWM2_CLK_EN |
168 DPORT_PWM3_CLK_EN;
169
170 hwcrypto_perip_clk = DPORT_PERI_EN_AES |
171 DPORT_PERI_EN_SHA |
172 DPORT_PERI_EN_RSA |
173 DPORT_PERI_EN_SECUREBOOT;
174
175 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
176 DPORT_WIFI_CLK_BT_EN_M |
177 DPORT_WIFI_CLK_UNUSED_BIT5 |
178 DPORT_WIFI_CLK_UNUSED_BIT12 |
179 DPORT_WIFI_CLK_SDIOSLAVE_EN |
180 DPORT_WIFI_CLK_SDIO_HOST_EN |
181 DPORT_WIFI_CLK_EMAC_EN;
182 }
183
184 /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
185 common_perip_clk |= DPORT_I2S0_CLK_EN |
186 DPORT_UART_CLK_EN |
187 DPORT_SPI2_CLK_EN |
188 DPORT_I2C_EXT0_CLK_EN |
189 DPORT_UHCI0_CLK_EN |
190 DPORT_RMT_CLK_EN |
191 DPORT_UHCI1_CLK_EN |
192 DPORT_SPI3_CLK_EN |
193 DPORT_I2C_EXT1_CLK_EN |
194 DPORT_I2S1_CLK_EN |
195 DPORT_SPI_DMA_CLK_EN;
196
197 common_perip_clk &= ~DPORT_SPI01_CLK_EN;
198 common_perip_clk &= ~DPORT_SPI2_CLK_EN;
199 common_perip_clk &= ~DPORT_SPI3_CLK_EN;
200
201 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
202 * the current is not reduced when disable I2S clock.
203 */
204 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(0), I2S_CLKA_ENA);
205 DPORT_SET_PERI_REG_MASK(I2S_CLKM_CONF_REG(1), I2S_CLKA_ENA);
206
207 /* Disable some peripheral clocks. */
208 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
209 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
210
211 /* Disable hardware crypto clocks. */
212 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERI_CLK_EN_REG, hwcrypto_perip_clk);
213 DPORT_SET_PERI_REG_MASK(DPORT_PERI_RST_EN_REG, hwcrypto_perip_clk);
214
215 /* Disable WiFi/BT/SDIO clocks. */
216 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
217
218 /* Enable RNG clock. */
219 periph_module_enable(PERIPH_RNG_MODULE);
220 }
221 #endif /* CONFIG_SOC_SERIES_ESP32 */
222
223 #if defined(CONFIG_SOC_SERIES_ESP32S2)
esp32_clock_perip_init(void)224 static void esp32_clock_perip_init(void)
225 {
226 uint32_t common_perip_clk;
227 uint32_t hwcrypto_perip_clk;
228 uint32_t wifi_bt_sdio_clk;
229 uint32_t common_perip_clk1;
230
231 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
232
233 /* For reason that only reset CPU, do not disable the clocks
234 * that have been enabled before reset.
235 */
236 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
237 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
238 common_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN_REG);
239 hwcrypto_perip_clk = ~DPORT_READ_PERI_REG(DPORT_PERIP_CLK_EN1_REG);
240 wifi_bt_sdio_clk = ~DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
241 } else {
242 common_perip_clk = DPORT_WDG_CLK_EN |
243 DPORT_I2S0_CLK_EN |
244 DPORT_UART1_CLK_EN |
245 DPORT_SPI2_CLK_EN |
246 DPORT_I2C_EXT0_CLK_EN |
247 DPORT_UHCI0_CLK_EN |
248 DPORT_RMT_CLK_EN |
249 DPORT_PCNT_CLK_EN |
250 DPORT_LEDC_CLK_EN |
251 DPORT_TIMERGROUP1_CLK_EN |
252 DPORT_SPI3_CLK_EN |
253 DPORT_PWM0_CLK_EN |
254 DPORT_TWAI_CLK_EN |
255 DPORT_PWM1_CLK_EN |
256 DPORT_I2S1_CLK_EN |
257 DPORT_SPI2_DMA_CLK_EN |
258 DPORT_SPI3_DMA_CLK_EN |
259 DPORT_PWM2_CLK_EN |
260 DPORT_PWM3_CLK_EN;
261
262 common_perip_clk1 = 0;
263
264 hwcrypto_perip_clk = DPORT_CRYPTO_AES_CLK_EN |
265 DPORT_CRYPTO_SHA_CLK_EN |
266 DPORT_CRYPTO_RSA_CLK_EN;
267
268 wifi_bt_sdio_clk = DPORT_WIFI_CLK_WIFI_EN |
269 DPORT_WIFI_CLK_BT_EN_M |
270 DPORT_WIFI_CLK_UNUSED_BIT5 |
271 DPORT_WIFI_CLK_UNUSED_BIT12 |
272 DPORT_WIFI_CLK_SDIOSLAVE_EN |
273 DPORT_WIFI_CLK_SDIO_HOST_EN |
274 DPORT_WIFI_CLK_EMAC_EN;
275 }
276
277 /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
278 common_perip_clk |= DPORT_I2S0_CLK_EN |
279 DPORT_UART1_CLK_EN |
280 DPORT_USB_CLK_EN |
281 DPORT_SPI2_CLK_EN |
282 DPORT_I2C_EXT0_CLK_EN |
283 DPORT_UHCI0_CLK_EN |
284 DPORT_RMT_CLK_EN |
285 DPORT_UHCI1_CLK_EN |
286 DPORT_SPI3_CLK_EN |
287 DPORT_I2C_EXT1_CLK_EN |
288 DPORT_I2S1_CLK_EN |
289 DPORT_SPI2_DMA_CLK_EN |
290 DPORT_SPI3_DMA_CLK_EN;
291
292 common_perip_clk1 = 0;
293
294 /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
295 * the current is not reduced when disable I2S clock.
296 */
297 REG_SET_FIELD(I2S_CLKM_CONF_REG(0), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
298 REG_SET_FIELD(I2S_CLKM_CONF_REG(1), I2S_CLK_SEL, I2S_CLK_AUDIO_PLL);
299
300 /* Disable some peripheral clocks. */
301 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, common_perip_clk);
302 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, common_perip_clk);
303
304 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, common_perip_clk1);
305 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, common_perip_clk1);
306
307 /* Disable hardware crypto clocks. */
308 DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
309 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
310
311 /* Disable WiFi/BT/SDIO clocks. */
312 DPORT_CLEAR_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
313
314 /* Enable WiFi MAC and POWER clocks */
315 DPORT_SET_PERI_REG_MASK(DPORT_WIFI_CLK_EN_REG, DPORT_WIFI_CLK_WIFI_EN);
316
317 /* Set WiFi light sleep clock source to RTC slow clock */
318 DPORT_REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 0);
319 DPORT_CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
320 DPORT_SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_RTC_SLOW);
321
322 /* Enable RNG clock. */
323 periph_module_enable(PERIPH_RNG_MODULE);
324 }
325 #endif /* CONFIG_SOC_SERIES_ESP32S2 */
326
327 #if defined(CONFIG_SOC_SERIES_ESP32S3)
esp32_clock_perip_init(void)328 static void esp32_clock_perip_init(void)
329 {
330 #if defined(CONFIG_SOC_ESP32S3_APPCPU)
331 /* skip APPCPU configuration */
332 return;
333 #endif
334
335 uint32_t common_perip_clk, hwcrypto_perip_clk, wifi_bt_sdio_clk = 0;
336 uint32_t common_perip_clk1 = 0;
337
338 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
339
340 /* For reason that only reset CPU, do not disable the clocks
341 * that have been enabled before reset.
342 */
343 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
344 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
345 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
346 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
347 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
348 } else {
349 common_perip_clk = SYSTEM_WDG_CLK_EN |
350 SYSTEM_I2S0_CLK_EN |
351 SYSTEM_UART1_CLK_EN |
352 SYSTEM_UART2_CLK_EN |
353 SYSTEM_USB_CLK_EN |
354 SYSTEM_SPI2_CLK_EN |
355 SYSTEM_I2C_EXT0_CLK_EN |
356 SYSTEM_UHCI0_CLK_EN |
357 SYSTEM_RMT_CLK_EN |
358 SYSTEM_PCNT_CLK_EN |
359 SYSTEM_LEDC_CLK_EN |
360 SYSTEM_TIMERGROUP1_CLK_EN |
361 SYSTEM_SPI3_CLK_EN |
362 SYSTEM_SPI4_CLK_EN |
363 SYSTEM_PWM0_CLK_EN |
364 SYSTEM_TWAI_CLK_EN |
365 SYSTEM_PWM1_CLK_EN |
366 SYSTEM_I2S1_CLK_EN |
367 SYSTEM_SPI2_DMA_CLK_EN |
368 SYSTEM_SPI3_DMA_CLK_EN |
369 SYSTEM_PWM2_CLK_EN |
370 SYSTEM_PWM3_CLK_EN;
371
372 common_perip_clk1 = 0;
373
374 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
375 SYSTEM_CRYPTO_SHA_CLK_EN |
376 SYSTEM_CRYPTO_RSA_CLK_EN;
377
378 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
379 SYSTEM_WIFI_CLK_BT_EN_M |
380 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
381 SYSTEM_WIFI_CLK_UNUSED_BIT12 |
382 SYSTEM_WIFI_CLK_SDIO_HOST_EN;
383 }
384
385 /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
386 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
387 SYSTEM_UART1_CLK_EN |
388 SYSTEM_UART2_CLK_EN |
389 SYSTEM_USB_CLK_EN |
390 SYSTEM_SPI2_CLK_EN |
391 SYSTEM_I2C_EXT0_CLK_EN |
392 SYSTEM_UHCI0_CLK_EN |
393 SYSTEM_RMT_CLK_EN |
394 SYSTEM_UHCI1_CLK_EN |
395 SYSTEM_SPI3_CLK_EN |
396 SYSTEM_SPI4_CLK_EN |
397 SYSTEM_I2C_EXT1_CLK_EN |
398 SYSTEM_I2S1_CLK_EN |
399 SYSTEM_SPI2_DMA_CLK_EN |
400 SYSTEM_SPI3_DMA_CLK_EN;
401
402 common_perip_clk1 = 0;
403
404 /* Disable some peripheral clocks. */
405 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
406 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
407
408 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
409 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
410
411 /* Disable hardware crypto clocks. */
412 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
413 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
414
415 /* Disable WiFi/BT/SDIO clocks. */
416 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
417 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
418
419 /* Set WiFi light sleep clock source to RTC slow clock */
420 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
421 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
422 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
423
424 /* Enable RNG clock. */
425 periph_module_enable(PERIPH_RNG_MODULE);
426
427 esp_rom_uart_tx_wait_idle(0);
428 esp_rom_uart_set_clock_baudrate(0, UART_CLK_FREQ_ROM, 115200);
429 }
430 #endif /* CONFIG_SOC_SERIES_ESP32S3 */
431
432 #if defined(CONFIG_SOC_SERIES_ESP32C3)
esp32_clock_perip_init(void)433 static void esp32_clock_perip_init(void)
434 {
435 uint32_t common_perip_clk;
436 uint32_t hwcrypto_perip_clk;
437 uint32_t wifi_bt_sdio_clk;
438 uint32_t common_perip_clk1;
439
440 soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
441
442 /* For reason that only reset CPU, do not disable the clocks
443 * that have been enabled before reset.
444 */
445 if (rst_reason == RESET_REASON_CPU0_MWDT0 || rst_reason == RESET_REASON_CPU0_SW ||
446 rst_reason == RESET_REASON_CPU0_RTC_WDT || rst_reason == RESET_REASON_CPU0_MWDT1) {
447 common_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN0_REG);
448 hwcrypto_perip_clk = ~READ_PERI_REG(SYSTEM_PERIP_CLK_EN1_REG);
449 wifi_bt_sdio_clk = ~READ_PERI_REG(SYSTEM_WIFI_CLK_EN_REG);
450 } else {
451 common_perip_clk = SYSTEM_WDG_CLK_EN |
452 SYSTEM_I2S0_CLK_EN |
453 SYSTEM_UART1_CLK_EN |
454 SYSTEM_SPI2_CLK_EN |
455 SYSTEM_I2C_EXT0_CLK_EN |
456 SYSTEM_UHCI0_CLK_EN |
457 SYSTEM_RMT_CLK_EN |
458 SYSTEM_LEDC_CLK_EN |
459 SYSTEM_TIMERGROUP1_CLK_EN |
460 SYSTEM_SPI3_CLK_EN |
461 SYSTEM_SPI4_CLK_EN |
462 SYSTEM_TWAI_CLK_EN |
463 SYSTEM_I2S1_CLK_EN |
464 SYSTEM_SPI2_DMA_CLK_EN |
465 SYSTEM_SPI3_DMA_CLK_EN;
466
467 common_perip_clk1 = 0;
468
469 hwcrypto_perip_clk = SYSTEM_CRYPTO_AES_CLK_EN |
470 SYSTEM_CRYPTO_SHA_CLK_EN |
471 SYSTEM_CRYPTO_RSA_CLK_EN;
472
473 wifi_bt_sdio_clk = SYSTEM_WIFI_CLK_WIFI_EN |
474 SYSTEM_WIFI_CLK_BT_EN_M |
475 SYSTEM_WIFI_CLK_UNUSED_BIT5 |
476 SYSTEM_WIFI_CLK_UNUSED_BIT12;
477 }
478
479 /* Reset peripherals like I2C, SPI, UART, I2S and bring them to known state */
480 common_perip_clk |= SYSTEM_I2S0_CLK_EN |
481 SYSTEM_UART1_CLK_EN |
482 SYSTEM_SPI2_CLK_EN |
483 SYSTEM_I2C_EXT0_CLK_EN |
484 SYSTEM_UHCI0_CLK_EN |
485 SYSTEM_RMT_CLK_EN |
486 SYSTEM_UHCI1_CLK_EN |
487 SYSTEM_SPI3_CLK_EN |
488 SYSTEM_SPI4_CLK_EN |
489 SYSTEM_I2C_EXT1_CLK_EN |
490 SYSTEM_I2S1_CLK_EN |
491 SYSTEM_SPI2_DMA_CLK_EN |
492 SYSTEM_SPI3_DMA_CLK_EN;
493
494 common_perip_clk1 = 0;
495
496 /* Disable some peripheral clocks. */
497 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN0_REG, common_perip_clk);
498 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG, common_perip_clk);
499
500 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, common_perip_clk1);
501 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, common_perip_clk1);
502
503 /* Disable hardware crypto clocks. */
504 CLEAR_PERI_REG_MASK(SYSTEM_PERIP_CLK_EN1_REG, hwcrypto_perip_clk);
505 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, hwcrypto_perip_clk);
506
507 /* Disable WiFi/BT/SDIO clocks. */
508 CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, wifi_bt_sdio_clk);
509 SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
510
511 /* Set WiFi light sleep clock source to RTC slow clock */
512 REG_SET_FIELD(SYSTEM_BT_LPCK_DIV_INT_REG, SYSTEM_BT_LPCK_DIV_NUM, 0);
513 CLEAR_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_8M);
514 SET_PERI_REG_MASK(SYSTEM_BT_LPCK_DIV_FRAC_REG, SYSTEM_LPCLK_SEL_RTC_SLOW);
515
516 /* Enable RNG clock. */
517 periph_module_enable(PERIPH_RNG_MODULE);
518 }
519 #endif /* CONFIG_SOC_SERIES_ESP32C3 */
520
clock_control_esp32_init(const struct device * dev)521 static int clock_control_esp32_init(const struct device *dev)
522 {
523 const struct esp32_clock_config *cfg = dev->config;
524 rtc_cpu_freq_config_t old_config;
525 rtc_cpu_freq_config_t new_config;
526 bool res;
527
528 /* reset default config to use dts config */
529 if (rtc_clk_apb_freq_get() < APB_CLK_FREQ || rtc_get_reset_reason(0) != CPU_RESET_REASON) {
530 rtc_clk_config_t clk_cfg = RTC_CLK_CONFIG_DEFAULT();
531
532 clk_cfg.xtal_freq = xtal_freq[cfg->xtal_freq_sel];
533 clk_cfg.cpu_freq_mhz = cfg->cpu_freq;
534 clk_cfg.slow_freq = rtc_clk_slow_freq_get();
535 clk_cfg.fast_freq = rtc_clk_fast_freq_get();
536 rtc_clk_init(clk_cfg);
537 }
538
539 rtc_clk_fast_freq_set(RTC_FAST_FREQ_8M);
540
541 rtc_clk_cpu_freq_get_config(&old_config);
542
543 const uint32_t old_freq_mhz = old_config.freq_mhz;
544 const uint32_t new_freq_mhz = cfg->cpu_freq;
545
546 res = rtc_clk_cpu_freq_mhz_to_config(cfg->cpu_freq, &new_config);
547 if (!res) {
548 return -ENOTSUP;
549 }
550
551 /* wait uart output to be cleared */
552 esp_rom_uart_tx_wait_idle(0);
553
554 if (cfg->xtal_div >= 0) {
555 new_config.div = cfg->xtal_div;
556 }
557
558 if (cfg->clk_src_sel >= 0) {
559 new_config.source = cfg->clk_src_sel;
560 }
561
562 /* set new configuration */
563 rtc_clk_cpu_freq_set_config(&new_config);
564
565 /* Re-calculate the ccount to make time calculation correct */
566 cpu_hal_set_cycle_count((uint64_t)cpu_hal_get_cycle_count() * new_freq_mhz / old_freq_mhz);
567
568 esp32_clock_perip_init();
569
570 return 0;
571 }
572
573 static const struct clock_control_driver_api clock_control_esp32_api = {
574 .on = clock_control_esp32_on,
575 .off = clock_control_esp32_off,
576 .async_on = clock_control_esp32_async_on,
577 .get_rate = clock_control_esp32_get_rate,
578 .get_status = clock_control_esp32_get_status,
579 };
580
581 #define ESP32_CLOCK_SOURCE \
582 COND_CODE_1(DT_NODE_HAS_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source), \
583 (DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_source)), (-1))
584
585 #define ESP32_CLOCK_XTAL_DIV \
586 COND_CODE_1(DT_NODE_HAS_PROP(0, xtal_div), \
587 (DT_INST_PROP(0, xtal_div)), (-1))
588
589 static const struct esp32_clock_config esp32_clock_config0 = {
590 .clk_src_sel = ESP32_CLOCK_SOURCE,
591 .cpu_freq = DT_PROP(DT_INST(0, DT_CPU_COMPAT), clock_frequency) / 1000000,
592 .xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
593 .xtal_div = ESP32_CLOCK_XTAL_DIV
594 };
595
596 DEVICE_DT_DEFINE(DT_NODELABEL(rtc),
597 &clock_control_esp32_init,
598 NULL,
599 NULL,
600 &esp32_clock_config0,
601 PRE_KERNEL_1,
602 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
603 &clock_control_esp32_api);
604
