1 /*
2 * Copyright (c) 2020 Mohamed ElShahawi.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT espressif_esp32_rtc
8
9 #include <dt-bindings/clock/esp32_clock.h>
10 #include <esp_bit_defs.h>
11 #include <soc/dport_reg.h>
12 #include <esp32/rom/uart.h>
13 #include <esp32/rom/rtc.h>
14 #include <soc/rtc.h>
15 #include <soc/rtc_cntl_reg.h>
16 #include <drivers/uart.h>
17 #include <soc/apb_ctrl_reg.h>
18
19 #include <soc.h>
20 #include <drivers/clock_control.h>
21 #include <sys/util.h>
22 #include "clock_control_esp32.h"
23 #include "driver/periph_ctrl.h"
24 #include <xtensa/core-macros.h>
25
26 struct esp32_clock_config {
27 uint32_t clk_src_sel;
28 uint32_t cpu_freq;
29 uint32_t xtal_freq_sel;
30 uint32_t xtal_div;
31 };
32
33 struct control_regs {
34 /** Peripheral control register */
35 uint32_t clk;
36 /** Peripheral reset register */
37 uint32_t rst;
38 };
39
40 struct bbpll_cfg {
41 uint8_t div_ref;
42 uint8_t div7_0;
43 uint8_t div10_8;
44 uint8_t lref;
45 uint8_t dcur;
46 uint8_t bw;
47 };
48
49 struct pll_cfg {
50 uint8_t dbias_wak;
51 uint8_t endiv5;
52 uint8_t bbadc_dsmp;
53 struct bbpll_cfg bbpll[2];
54 };
55
56
57 #define PLL_APB_CLK_FREQ 80
58
59 #define RTC_PLL_FREQ_320M 0
60 #define RTC_PLL_FREQ_480M 1
61
62 #define DPORT_CPUPERIOD_SEL_80 0
63 #define DPORT_CPUPERIOD_SEL_160 1
64 #define DPORT_CPUPERIOD_SEL_240 2
65
66 #define DEV_CFG(dev) ((struct esp32_clock_config *)(dev->config))
67 #define GET_REG_BANK(module_id) ((uint32_t)module_id / 32U)
68 #define GET_REG_OFFSET(module_id) ((uint32_t)module_id % 32U)
69
70 #define CLOCK_REGS_BANK_COUNT 3
71
72 const struct control_regs clock_control_regs[CLOCK_REGS_BANK_COUNT] = {
73 [0] = { .clk = DPORT_PERIP_CLK_EN_REG, .rst = DPORT_PERIP_RST_EN_REG },
74 [1] = { .clk = DPORT_PERI_CLK_EN_REG, .rst = DPORT_PERI_RST_EN_REG },
75 [2] = { .clk = DPORT_WIFI_CLK_EN_REG, .rst = DPORT_CORE_RST_EN_REG }
76 };
77
78 static uint32_t const xtal_freq[] = {
79 [ESP32_CLK_XTAL_40M] = 40,
80 [ESP32_CLK_XTAL_26M] = 26
81 };
82
83 const struct pll_cfg pll_config[] = {
84 [RTC_PLL_FREQ_320M] = {
85 .dbias_wak = 0,
86 .endiv5 = BBPLL_ENDIV5_VAL_320M,
87 .bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_320M,
88 .bbpll[ESP32_CLK_XTAL_40M] = {
89 /* 40mhz */
90 .div_ref = 0,
91 .div7_0 = 32,
92 .div10_8 = 0,
93 .lref = 0,
94 .dcur = 6,
95 .bw = 3,
96 },
97 .bbpll[ESP32_CLK_XTAL_26M] = {
98 /* 26mhz */
99 .div_ref = 12,
100 .div7_0 = 224,
101 .div10_8 = 4,
102 .lref = 1,
103 .dcur = 0,
104 .bw = 1,
105 }
106 },
107 [RTC_PLL_FREQ_480M] = {
108 .dbias_wak = 0,
109 .endiv5 = BBPLL_ENDIV5_VAL_480M,
110 .bbadc_dsmp = BBPLL_BBADC_DSMP_VAL_480M,
111 .bbpll[ESP32_CLK_XTAL_40M] = {
112 /* 40mhz */
113 .div_ref = 0,
114 .div7_0 = 28,
115 .div10_8 = 0,
116 .lref = 0,
117 .dcur = 6,
118 .bw = 3,
119 },
120 .bbpll[ESP32_CLK_XTAL_26M] = {
121 /* 26mhz */
122 .div_ref = 12,
123 .div7_0 = 144,
124 .div10_8 = 4,
125 .lref = 1,
126 .dcur = 0,
127 .bw = 1,
128 }
129 }
130 };
131
bbpll_configure(rtc_xtal_freq_t xtal_freq,uint32_t pll_freq)132 static void bbpll_configure(rtc_xtal_freq_t xtal_freq, uint32_t pll_freq)
133 {
134 uint8_t dbias_wak = 0;
135
136 const struct pll_cfg *cfg = &pll_config[pll_freq];
137 const struct bbpll_cfg *bb_cfg = &pll_config[pll_freq].bbpll[xtal_freq];
138
139 /* Enable PLL, Clear PowerDown (_PD) flags */
140 CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
141 RTC_CNTL_BIAS_I2C_FORCE_PD |
142 RTC_CNTL_BB_I2C_FORCE_PD |
143 RTC_CNTL_BBPLL_FORCE_PD |
144 RTC_CNTL_BBPLL_I2C_FORCE_PD);
145
146 /* reset BBPLL configuration */
147 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, BBPLL_IR_CAL_DELAY_VAL);
148 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, BBPLL_IR_CAL_EXT_CAP_VAL);
149 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, BBPLL_OC_ENB_FCAL_VAL);
150 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, BBPLL_OC_ENB_VCON_VAL);
151 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, BBPLL_BBADC_CAL_7_0_VAL);
152
153 /* voltage needs to be changed for CPU@240MHz or
154 * 80MHz Flash (because of internal flash regulator)
155 */
156 if (pll_freq == RTC_PLL_FREQ_320M) {
157 dbias_wak = DIG_DBIAS_80M_160M;
158 } else { /* RTC_PLL_FREQ_480M */
159 dbias_wak = DIG_DBIAS_240M;
160 }
161
162 /* Configure the voltage */
163 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias_wak);
164 esp32_rom_ets_delay_us(DELAY_PLL_DBIAS_RAISE);
165
166 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, cfg->endiv5);
167 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, cfg->bbadc_dsmp);
168
169 uint8_t i2c_bbpll_lref = (bb_cfg->lref << 7) | (bb_cfg->div10_8 << 4) | (bb_cfg->div_ref);
170
171 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref);
172 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, bb_cfg->div7_0);
173 I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, ((bb_cfg->bw << 6) | bb_cfg->dcur));
174 }
175
clk_val_to_reg_val(uint32_t val)176 static inline uint32_t clk_val_to_reg_val(uint32_t val)
177 {
178 return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
179 }
180
esp_clk_cpu_freq(void)181 int IRAM_ATTR esp_clk_cpu_freq(void)
182 {
183 return MHZ(esp32_rom_g_ticks_per_us_pro);
184 }
185
esp_clk_apb_freq(void)186 int IRAM_ATTR esp_clk_apb_freq(void)
187 {
188 return MHZ(MIN(esp32_rom_g_ticks_per_us_pro, 80));
189 }
190
ets_update_cpu_frequency(uint32_t ticks_per_us)191 void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)
192 {
193 /* Update scale factors used by ets_delay_us */
194 esp32_rom_g_ticks_per_us_pro = ticks_per_us;
195 esp32_rom_g_ticks_per_us_app = ticks_per_us;
196 }
197
esp32_cpu_freq_to_xtal(int freq,int div)198 static void esp32_cpu_freq_to_xtal(int freq, int div)
199 {
200 ets_update_cpu_frequency(freq);
201
202 uint32_t apb_freq = MHZ(freq);
203 WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
204 /* set divider from XTAL to APB clock */
205 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1);
206 /* adjust ref_tick */
207 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, MHZ(freq) / REF_CLK_FREQ - 1);
208 /* switch clock source */
209 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
210
211 /* lower the voltage */
212 if (freq <= 2) {
213 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
214 } else {
215 REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
216 }
217 }
218
cpuclk_pll_configure(uint32_t xtal_freq,uint32_t cpu_freq)219 static void cpuclk_pll_configure(uint32_t xtal_freq, uint32_t cpu_freq)
220 {
221 uint32_t pll_freq = RTC_PLL_FREQ_320M;
222 uint32_t cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
223
224 switch (cpu_freq) {
225 case ESP32_CLK_CPU_80M:
226 pll_freq = RTC_PLL_FREQ_320M;
227 cpu_period_sel = DPORT_CPUPERIOD_SEL_80;
228 break;
229 case ESP32_CLK_CPU_160M:
230 pll_freq = RTC_PLL_FREQ_320M;
231 cpu_period_sel = DPORT_CPUPERIOD_SEL_160;
232 break;
233 case ESP32_CLK_CPU_240M:
234 pll_freq = RTC_PLL_FREQ_480M;
235 cpu_period_sel = DPORT_CPUPERIOD_SEL_240;
236 break;
237 }
238
239 /* Configure PLL based on XTAL Value */
240 bbpll_configure(xtal_freq, pll_freq);
241 /* Set CPU Speed (80,160,240) */
242 DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, cpu_period_sel);
243 /* Set PLL as CPU Clock Source */
244 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_PLL);
245
246 ets_update_cpu_frequency(cpu_freq);
247
248 /*
249 * Update REF_Tick,
250 * if PLL is the cpu clock source, APB frequency is always 80MHz
251 */
252 REG_WRITE(APB_CTRL_PLL_TICK_CONF_REG, PLL_APB_CLK_FREQ - 1);
253 }
254
clock_control_esp32_on(const struct device * dev,clock_control_subsys_t sys)255 static int clock_control_esp32_on(const struct device *dev,
256 clock_control_subsys_t sys)
257 {
258 ARG_UNUSED(dev);
259 uint32_t bank = GET_REG_BANK(sys);
260 uint32_t offset = GET_REG_OFFSET(sys);
261
262 __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT);
263
264 esp32_set_mask32(BIT(offset), clock_control_regs[bank].clk);
265 esp32_clear_mask32(BIT(offset), clock_control_regs[bank].rst);
266 return 0;
267 }
268
clock_control_esp32_off(const struct device * dev,clock_control_subsys_t sys)269 static int clock_control_esp32_off(const struct device *dev,
270 clock_control_subsys_t sys)
271 {
272 ARG_UNUSED(dev);
273 uint32_t bank = GET_REG_BANK(sys);
274 uint32_t offset = GET_REG_OFFSET(sys);
275
276 __ASSERT_NO_MSG(bank < CLOCK_REGS_BANK_COUNT);
277
278 esp32_clear_mask32(BIT(offset), clock_control_regs[bank].clk);
279 esp32_set_mask32(BIT(offset), clock_control_regs[bank].rst);
280 return 0;
281 }
282
clock_control_esp32_get_status(const struct device * dev,clock_control_subsys_t sys)283 static enum clock_control_status clock_control_esp32_get_status(const struct device *dev,
284 clock_control_subsys_t sys)
285 {
286 ARG_UNUSED(dev);
287 uint32_t bank = GET_REG_BANK(sys);
288 uint32_t offset = GET_REG_OFFSET(sys);
289
290 if (DPORT_GET_PERI_REG_MASK(clock_control_regs[bank].clk, BIT(offset))) {
291 return CLOCK_CONTROL_STATUS_ON;
292 }
293 return CLOCK_CONTROL_STATUS_OFF;
294 }
295
clock_control_esp32_get_rate(const struct device * dev,clock_control_subsys_t sub_system,uint32_t * rate)296 static int clock_control_esp32_get_rate(const struct device *dev,
297 clock_control_subsys_t sub_system,
298 uint32_t *rate)
299 {
300 ARG_UNUSED(sub_system);
301
302 uint32_t xtal_freq_sel = DEV_CFG(dev)->xtal_freq_sel;
303 uint32_t soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL);
304
305 switch (soc_clk_sel) {
306 case RTC_CNTL_SOC_CLK_SEL_XTL:
307 *rate = xtal_freq[xtal_freq_sel];
308 return 0;
309 case RTC_CNTL_SOC_CLK_SEL_PLL:
310 *rate = MHZ(80);
311 return 0;
312 default:
313 *rate = 0;
314 return -ENOTSUP;
315 }
316 }
317
clock_control_esp32_init(const struct device * dev)318 static int clock_control_esp32_init(const struct device *dev)
319 {
320 struct esp32_clock_config *cfg = DEV_CFG(dev);
321
322 /* Wait for UART first before changing freq to avoid garbage on console */
323 esp32_rom_uart_tx_wait_idle(0);
324
325 switch (cfg->clk_src_sel) {
326 case ESP32_CLK_SRC_XTAL:
327 REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, cfg->xtal_div);
328 /* adjust ref_tick */
329 REG_WRITE(APB_CTRL_XTAL_TICK_CONF_REG, xtal_freq[cfg->xtal_freq_sel] - 1);
330 /* switch clock source */
331 REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, RTC_CNTL_SOC_CLK_SEL_XTL);
332 break;
333 case ESP32_CLK_SRC_PLL:
334 esp32_cpu_freq_to_xtal(xtal_freq[cfg->xtal_freq_sel], 1);
335 cpuclk_pll_configure(cfg->xtal_freq_sel, cfg->cpu_freq);
336 break;
337 default:
338 return -EINVAL;
339 }
340
341 /* Enable RNG clock. */
342 periph_module_enable(PERIPH_RNG_MODULE);
343
344 /* Re-calculate the CCOUNT register value to make time calculation correct.
345 * This should be updated on each frequency change
346 * New CCOUNT = Current CCOUNT * (new freq / old freq)
347 */
348 XTHAL_SET_CCOUNT((uint64_t)XTHAL_GET_CCOUNT() * cfg->cpu_freq / xtal_freq[cfg->xtal_freq_sel]);
349 return 0;
350 }
351
352 static const struct clock_control_driver_api clock_control_esp32_api = {
353 .on = clock_control_esp32_on,
354 .off = clock_control_esp32_off,
355 .get_rate = clock_control_esp32_get_rate,
356 .get_status = clock_control_esp32_get_status,
357 };
358
359 static const struct esp32_clock_config esp32_clock_config0 = {
360 .clk_src_sel = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
361 .cpu_freq = DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency),
362 .xtal_freq_sel = DT_INST_PROP(0, xtal_freq),
363 .xtal_div = DT_INST_PROP(0, xtal_div),
364 };
365
366 DEVICE_DT_INST_DEFINE(0,
367 &clock_control_esp32_init,
368 NULL,
369 NULL, &esp32_clock_config0,
370 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,
371 &clock_control_esp32_api);
372
373 BUILD_ASSERT((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) ==
374 MHZ(DT_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_frequency)),
375 "SYS_CLOCK_HW_CYCLES_PER_SEC Value must be equal to CPU_Freq");
376
377 BUILD_ASSERT(DT_NODE_HAS_PROP(DT_INST(0, cdns_tensilica_xtensa_lx6), clock_source),
378 "CPU clock-source property must be set to ESP32_CLK_SRC_XTAL or ESP32_CLK_SRC_PLL");
379
